CN109213531A - A kind of multi-core DSP based on EMIF16 powers on the simplification implementation method of self-starting - Google Patents
A kind of multi-core DSP based on EMIF16 powers on the simplification implementation method of self-starting Download PDFInfo
- Publication number
- CN109213531A CN109213531A CN201811015884.2A CN201811015884A CN109213531A CN 109213531 A CN109213531 A CN 109213531A CN 201811015884 A CN201811015884 A CN 201811015884A CN 109213531 A CN109213531 A CN 109213531A
- Authority
- CN
- China
- Prior art keywords
- core
- program
- powers
- starting
- self
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4405—Initialisation of multiprocessor systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/61—Installation
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Stored Programmes (AREA)
Abstract
A kind of multi-core DSP based on EMIF16 powers on the simplification implementation method of self-starting, belongs to embedded device and powers on bootstrap technical field.The present invention passes through three-level loading procedure, by modifying CMD file, multi-core program is subjected to section storage, and write program burn writing function and second level bootloader, the compiling of multi-core program and programming process are completed under the same CCS engineering, final correct realization multi-core DSP program powers on self-starting.Method provided by the invention has abandoned the cumbersome treatment process that current multi-core DSP powers on self-starting, is compiled it is not necessary that multi-core program to be established to engineering respectively, the step of synthesizing multiple image files manually is omitted, and improves the efficiency of multi-core program load；Using the method for writing programming function in engineering, so that multi-core program programming is convenient；It is simple to power on loading procedure, programmed readability is stronger, highly shortened debugging cycle, and correct, the reliable load operating of multi-core DSP software may be implemented.
Description
Technical field
The invention belongs to embedded devices to power on bootstrap technical field, and in particular to a kind of multicore based on EMIF16
DSP powers on the simplification implementation method of self-starting.
Background technique
As the development and research of signal processing technology deepen continuously, the side of DSP and FPGA combination is generallyd use at this stage
Formula realizes the processing of signal, and wherein FPGA is responsible for being acquired signal, AD conversion, extracts signal parameter etc., and DSP realizes main function
The control of energy carries out the calculating of complicated algorithm for the obtained information of FPGA, and sends calculated result to display terminal.Multicore
Dsp chip is integrated on a single die multiple kernels, has matter in processing speed and ability compared to monokaryon DSP before
Leap, therefore in the various field of signal processing such as communication, space flight and aviation, sonar, radar, industrial detection, electronic warfare, increasingly
More uses multi-core DSP as main processing components.Wherein, the high performance float-point multi core chip that TI company releases
TMS320C6678, represents the mainstream development trend of current multi-core DSP, and monokaryon maximum operating frequency is current up to 1.2GHz
The dsp processor of the 10GHz of industry peak performance.
Dsp chip enters multicore era, brings very big promotion for the processing capacity of signal processing system, but also gives
Dsp software exploitation brings new challenge.Present invention is primarily concerned be the storage of multi-core DSP program and power on self-starting and ask
Topic, this is one of the key difficulties of multi-core DSP development and application.The programming of multi-core DSP at this stage is mainly distinguished using multiple engineerings
It compiles, be converted into image file, then artificially artificially spliced multiple image files, finally establish programming engineering and burnt
It writes in external NOR FLASH.After the compiling that user program passes through TI processor composing software CCS, the executable text of .out is generated
Part..out file can execute user program load into processor in such a way that CCS software loads, but its file format
Determining, which can not achieve, powers on self-starting.TI provides a whole set of tools chain, including third party's crossover tool, by .out
File to can programming image file converted, then by establishing individual CCS engineering as fever writes, by the image text of synthesis
Part programming is into external FLASH.It is this to be converted by multiple-project compiling, tools chain, and the way for establishing programming engineering is very numerous
It is trivial.
Summary of the invention
The purpose of the present invention is to provide the simplification implementation method that a kind of multi-core DSP based on EMIF16 powers on self-starting,
This method in CCS engineering by modifying CMD file, by multi-core program fragmented storage in the address field set in advance, in this way
Multi-core program need to only compile under the same engineering, and unique main function is executed by main core, and the program of other cores should module
Change, i.e., module is packaged by functional form, is the customized memory paragraph of each function in CMD, this is to realize multi-core program
The premise that compiling, program are moved under same engineering.
Under above-mentioned engineering, second level bootloader file is write, and in the NOR FLASH that starts to 0x7000000 of programming,
The program file is write using assembler language, and suffix is .asm file, and major function is responsible for moving for main core program, and opens
Main core is moved to start to work；Programming function is write, is that each core divides reasonable code space in NOR FLASH, CCS's
The function is executed under debug state, directly all moves the data of the L2 SRAM space of each core in NOR FLASH respectively
Corresponding space.
The object of the present invention is achieved like this:
A kind of multi-core DSP based on EMIF16 powers on the simplification implementation method of self-starting, and the multi-core DSP powers on to be opened certainly
It is dynamic to be divided into three-level loading procedure, comprising:
(1) after multi-core DSP electrification reset, program in main core core0 automatic running on piece auto-programming loader RBL,
Corresponding EMIF16 start-up mode is obtained according to hardware pin configuration, PC pointer is pointing directly at the first address under the start-up mode
0x70000000 initializes EMIF interface, and configures phaselocked loop, which is known as level-one load；
(2) second level bootloader in the space 1KB that operation 0x70000000 starts, the NOR FLASH plug-in from EMIF16
In move the application program of main core to core0 L2 SRAM space, after the completion of moving, PC pointer jumps to main core main function entrance
At address _ C_int00, start the application program for executing main core, which is known as two stage loading；
(3) in the program of main core, main core reads the application program of core1~core7 from NOR FLASH, and moves
To the L2 SRAM of core1~core7, then the entry address of respective program is write to the BOOT_MAGIC_ of core1~core7
The address ADDRESS, i.e., last 4 bytes of each L2 SRAM space, finally main core sends IPC to core1~core7 and interrupts
To activate respectively from core, main core load is known as three-level load from the process of core.
Multi-core program need to only compile in an engineering, and unique main function is executed by main core, the program of other cores
It is packaged into respective function body, and is the customized memory paragraph of each function in CMD file, and the address for each section of distribution is long
Should specially before function body definition, one section of following code enough rationally be written in degree:
#pragma CODE_SECTION(core1_program,".test1")；
Wherein what function name core1_program was indicated is the user program of core1, and .test1 is customized section of user
Name, the definition of this section and its positioning in memory are embodied in as follows in CMD file:
MEMORY { USER1:o=0x11800000, l=0x80000 }
SECTION{.test1>USER1}。
User divides the occupied code space of each core in NOR FLASH, and writes programming function；In CCS Debug
State executes the function, directly all moves the data in the L2 SRAM space of each core corresponding in NOR FLASH
Space simplifies programming process.
The second level bootloader is write by user using assembler language, and before the code is placed on L2 SRAM
The space 1KB, and need programming to the preceding space 1KB of NOR FLASH, when system electrification bootstrap, directly in external NOR
FLASH executes this section of code, moves interrupt vector table to Local L2 SRAM space, moves the application program of main core to core0
L2 SRAM space.
A kind of multi-core DSP based on EMIF16 provided by the invention powers on the simplification implementation method of self-starting, using will be more
The storage of core program segmentingization, and program burn writing function and second level bootloader are write, it is final correctly to realize the upper of multi-core DSP program
Electric self-starting.
Compared with existing multi-core DSP powers on self-starting technology, the beneficial effects of the present invention are:
(1) method provided by the invention completes multi-core program under the same CCS engineering, without distinguishing multi-core program
It establishes engineering to be compiled, the step of synthesizing multiple image files manually is omitted, improve the efficiency of multi-core program load.
(2) method provided by the invention uses the method that programming function is write in engineering, executable without what will be generated
File is converted to the process of image file by third party software, so that multi-core program programming is convenient.
(3) it is simple to power on loading procedure for method provided by the invention, program update flexibly, it is readable stronger, may be implemented
Multi-core DSP software is correct, reliably loads and runs, and highly shortened debugging cycle.
Detailed description of the invention
Fig. 1 is the annexation figure of EMIF interface and NOR FLASH；
Fig. 2 is the flow chart of main core loading procedure；
Fig. 3 is flow chart of the main core load from core.
Specific embodiment
Invention is further described in detail with specific implementation method with reference to the accompanying drawing.
Dsp chip used in the present invention is the TMS320C6678 of TI company production, the NOR FLASH memory used
For the MT28GU01GAAA2EGC of Micron company production.
The present invention provides the simplification implementation methods that a kind of multi-core DSP based on EMIF16 powers on self-starting, wherein handling
The automatic load start-up course of device, be by processor after power up or reset, according to the different loading modes of setting, will deposit
The executable code stored up in external nonvolatile storage is automatically loaded into memory, and correctly runs the process of program.With
For TMS320C6678 multi-core DSP, loading mode mainly has: EMIF16, I2C load, SPI load, SRIO load, PCIe
Load, HyperLink etc.；When its loading mode is resetted by 13 external pin BOOTMODE [12:0] i.e. GPIO [13:1]
Hardware state selects.BOOTMODE [2:0] is for selecting loading mode, and BOOTMODE [12:3] is for being arranged the loading mode
The relevant configuration of lower corresponding interface, as shown in table 1.
The corresponding relationship of table 1 BOOTMODE [12:0] pin state and loading mode
The present invention provides the simplification implementation method that a kind of multi-core DSP based on EMIF16 powers on self-starting, and this method utilizes
Program code is moved in the external NOR FLASH of EMIF16 interface, carries out program designation.TMS320C6678 share CE0 CE1
CE2 tetra- address spaces of CE3 can connect FLASH, data width 16Bit or 8Bit is optional.Due to
The design feature of TMS320C6678EMIF16 loading mode powers on after executing level-one loading procedure, and PC pointer can jump to CE0
The first address 0x70000000 in space, therefore, NOR FLASH should be connected to the space CE0 of EMIF16, and specific connection relationship is such as
Shown in Fig. 1.
The present invention is to realize that multi-core DSP compiles simultaneously programming in same file, needs to modify CMD file, reasonably divides
The memory space of memory headroom and outside NOR FLASH with DSP.By taking TMS320C6678 as an example, each kernel has three-level to deposit
Store up space: level-one memory space includes the level data memory L1D of level-one program storage the L1P RAM and 32KB of 32KB
RAM；The second-level storage L2 SRAM of 512KB；The multicore shared drive MSMC SRAM of 4MB.Generally level-one memory space is made
It is used for caching, program code is stored in L2 SRAM and MSMC SRAM.In the present invention storage of multi-core program and its outside
Mapping relations in portion NOR FLASH are as shown in table 2.Principle is that the space length distributed in NOR FLASH should be greater than being equal to
Space length in DSP internal RAM, in order to avoid the case where generating program covers in the solidification of program；The starting point of each core program
Location should be the initial address of ROM block in this FLASH, to facilitate the program code for individually updating some core, because updating
It needs that the erasing of original code data is become FF in a manner of ROM block when program, is the program code for not influencing other cores, each
The program code of multiple cores cannot be stored in ROM block.
When writing user program in CCS, multi-core program compiles in an engineering and should modularization: unique
Main function is executed by main core, and the program of other cores is packaged into respective function body, and is that each function is made by oneself in CMD file
Adopted memory paragraph.For this purpose, needing to modify CMD file in CCS translation and compiling environment, positioned for the storage of program.
The space of 2 TMS320C6678 of table, eight core program is distributed
The effect of CMD file is linked to multiple file destinations of compiled mistake, and memory mapped files are generated
.map with output file .out.Wherein the part MEMORY can drawn with customized DSP internal storage name, position and size
Timesharing divides with the sector of FLASH be consistent as far as possible, subsequent erasable to facilitate；SECTION characterizing part includes system
Each section of configuring condition in memory including definition phase and customized section.
Section is the key concept in file destination, and each file destination includes several sections, customized section of system packet
Program documentaion section .text, data segment .data, array section .vectors, stack segment .stack etc. are included, if user is in programming
CMD file is not modified, then CCS can according to certain rules dismember program at above-mentioned each section, finally by each section of chain when compiling
It is connected together and constitutes output file.If user uses customized section, which will not use the above method to dismember,
And it is stored in this customized section.Obviously, customized section of priority is higher than system definition phase.
In the present invention, the program of multi-core DSP includes 10 parts in table 2, and each part will be carried out with functional form
Encapsulation, is written specified address field.Specific method is that one section of following code is written before function body definition:
#pragma CODE_SECTION(core1_program,".test1")；
Wherein what function name core1_program was indicated is the user program of core1, and .test1 is customized section of user
Name, the definition of this section and its positioning in memory are embodied in as follows in CMD file:
MEMORY { USER1:o=0x11800000, l=0x80000 }
SECTION{.test1>USER1}
It so completes to have been written into the contents of program in core1_program function from address 0x11800000 and open
Begin, in the address field that length is 0x80000.It, only need to will be in FLASH if the program of core1_program has change
This section of program is written to the sector position by the sector erasing that 0x70220000 starts again.
The present invention moves function by writing program, which can will represent all according to the mapping relations of table 2 in RAM
The data of code are directly moved in external NOR FLASH, are eliminated more using third party software conversion executable file, splicing
Core program code, the process for establishing programming engineering.Facts proved that: the data in RAM are program instruction performed by DSP, DSP
When powering on self-starting, CPU goes addressing RAM to find corresponding data according to these program instructions, and then executes program and complete accordingly
Function.So the image file that data in RAM and conventional method generate be it is the same, the method directly moved is than tradition
Easy more of method, without paying close attention to the storage format problem of program code.Under the debug state of CCS, the position of PC pointer is set
It sets, enforces the function, directly the data of the L2 SRAM space of each core are all moved in NOR FLASH and are respectively corresponded to
Space.But the function is not called in principal function, because the function is only used in program Solidification, it is not
The functional function for needing to run after DSP starting.
In the case where above-mentioned preparation process is errorless, the self-starting step provided by the invention that powers on includes:
(1) program after multi-core DSP electrification reset, in main core automatic running on piece auto-programming loader RBL.RBL generation
Code is the software program code for solidifying and residing in DSP internal sheets in read only memory ROM, this section of code solidifies when being factory
One section of code, user can not change.In TMS320C66786678, the storage location of RBL 0x20B00000~
In the space 128KB of 0x20B1FFFF.After DSP electrification reset, main core automatic running RBL code is configured according to hardware pin
Corresponding EMIF16 start-up mode is obtained, and initializes EMIF interface and configuration phaselocked loop, PC pointer is pointing directly at the starting mould
First address 0x70000000 under formula, the process are known as level-one load, and only main core has the permission for executing RBL.
(2) second level bootloader in the space 1KB that operation 0x70000000 starts, this section of program are compiled using assembler language
The a bit of code write, and the code is placed on to the preceding space 1KB of L2 SRAM, and must be before programming to NOR FLASH
The space 1KB.Its major function is: according to the mapping relations of table 2, will represent interrupt vector in EMIF16 plug-in NOR FLASH
The data-moving of 0 program of table and core is to corresponding ram space, after the completion of moving, PC pointer jump to the entry address of main core program _
At C_int00, start the application program for executing core 0, which is known as two stage loading.
So far, the self-starting process that powers on of core 0 has been completed, and Fig. 2 is the flow chart that core 0 loads.
(3) in the program of main core, main core reads the application program of core1~core7 from NOR FLASH, and moves
To the L2 SRAM of core1~core7, then the entry address of respective program is write to the BOOT_MAGIC_ of core1~core7
The address ADDRESS is last 4 bytes of each L2 SRAM space, and finally main core is sent in IPC to core1~core7
Break to activate respectively from core, main core load is known as three-level load from the process of core.
The BOOT_MAGIC_ADDRESS of core1~core7 is located at last 4 bytes of each L2 SRAM space, address
Are as follows: 0x1#87FFFC, wherein # value is 1~7, respectively represents core1~core7；The address is for storing respectively from the exhausted of core program
To entry address.Main core is respectively in IDLE idle state from core in the whole process for powering on self-starting.Main core is in implementation procedure
Middle to send IPC interruption to core1~core7, mode of operation is enabled register: IPCGRx=1, and wherein x value is 1~7, respectively
Represent core1~core7.It since IPCGRx is configuration register, cannot arbitrarily change, rewriting will be by posting to two unlocks
Storage KICK0=0x83E70B13, KICK1=0x95A4F1E0；Then it activates to enabled register assignment from core；After activation again
IPCGRx is locked, i.e. KICK0=0, KICK1=0.
It receives after IPC interrupts, is activated at once, pointer jumps to BOOT_MAGIC_ADDRESS, reads from core from core
The entry address of program then jumps to the entry address of the core program, starts the program for executing the core.Fig. 3 is the load of main core
From the flow chart of core.
Finally it should be noted that the chip model used in the present invention is only used for description technical solution of the present invention, without
It is to limit this technology method, the present invention can modify in the application, be transformed into other chip models, and think all
Such modification, variation are all within the scope of the present invention.
Claims (4)
1. the simplification implementation method that a kind of multi-core DSP based on EMIF16 powers on self-starting, it is characterised in that: the multicore
DSP powers on self-starting and is divided into three-level loading procedure, comprising:
(1) after multi-core DSP electrification reset, program in main core core0 automatic running on piece auto-programming loader RBL, according to
Hardware pin configuration obtains corresponding EMIF16 start-up mode, and PC pointer is pointing directly at the first address under the start-up mode
0x70000000 initializes EMIF interface, and configures phaselocked loop, which is known as level-one load；
(2) second level bootloader in the space 1KB that 0x70000000 starts is run, is removed in the NOR FLASH plug-in from EMIF16
The application program of main core is moved to core0 L2 SRAM space, after the completion of moving, PC pointer is with jumping to main core main function entrance
At location _ C_int00, start the application program for executing main core, which is known as two stage loading；
(3) in the program of main core, main core reads the application program of core1~core7 from NOR FLASH, and moves
The entry address of respective program, is then write the BOOT_MAGIC_ of core1~core7 by the L2 SRAM of core1~core7
The address ADDRESS, i.e., last 4 bytes of each L2 SRAM space, finally main core sends IPC to core1~core7 and interrupts
To activate respectively from core, main core load is known as three-level load from the process of core.
2. a kind of multi-core DSP based on EMIF16 according to claim 1 powers on the simplification implementation method of self-starting, special
Sign is: multi-core program need to only compile in an engineering, and unique main function is executed by main core, and the program of other cores is beaten
It is bundled into respective function body, and is the customized memory paragraph of each function in CMD file, and is the address size of each section of distribution
Specially before function body definition, one section of following code enough rationally should be written:
#pragma CODE_SECTION(core1_program,".test1")；
Wherein what function name core1_program was indicated is the user program of core1, and .test1 is customized section of name of user,
The definition of this section and its positioning in memory are embodied in as follows in CMD file:
MEMORY { USER1:o=0x11800000, l=0x80000 }
SECTION{.test1>USER1}。
3. a kind of multi-core DSP based on EMIF16 according to claim 1 powers on the simplification implementation method of self-starting, special
Sign is: user divides the occupied code space of each core in NOR FLASH, and writes programming function；In CCS Debug shape
State executes the function, and the data in the L2 SRAM space of each core are all directly moved corresponding sky in NOR FLASH
Between, simplify programming process.
4. a kind of multi-core DSP based on EMIF16 according to claim 1 powers on the simplification implementation method of self-starting, special
Sign is: the second level bootloader is write by user using assembler language, and before the code is placed on L2 SRAM
The space 1KB, and need programming to the preceding space 1KB of NOR FLASH, when system electrification bootstrap, directly in external NOR
FLASH executes this section of code, moves interrupt vector table to Local L2 SRAM space, moves the application program of main core to core0
L2 SRAM space.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811015884.2A CN109213531A (en) | 2018-09-01 | 2018-09-01 | A kind of multi-core DSP based on EMIF16 powers on the simplification implementation method of self-starting |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811015884.2A CN109213531A (en) | 2018-09-01 | 2018-09-01 | A kind of multi-core DSP based on EMIF16 powers on the simplification implementation method of self-starting |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109213531A true CN109213531A (en) | 2019-01-15 |
Family
ID=64986599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811015884.2A Pending CN109213531A (en) | 2018-09-01 | 2018-09-01 | A kind of multi-core DSP based on EMIF16 powers on the simplification implementation method of self-starting |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109213531A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109901890A (en) * | 2019-03-07 | 2019-06-18 | 深圳忆联信息***有限公司 | A kind of method, apparatus, computer equipment and the storage medium of controller loading multi-core firmware |
| CN111008045A (en) * | 2019-11-14 | 2020-04-14 | 中国航空工业集团公司洛阳电光设备研究所 | Automatic loading method for off-chip flash high-capacity program |
| CN111597140A (en) * | 2020-04-27 | 2020-08-28 | 深圳市有方科技股份有限公司 | Multi-core device function configuration method and device |
| CN112199121A (en) * | 2020-09-28 | 2021-01-08 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | DSP capacity-expanding and program-loading method according to needs |
| CN112905395A (en) * | 2021-03-12 | 2021-06-04 | 湖南长城银河科技有限公司 | Self-error-correction starting system for heterogeneous multi-core/many-core microprocessor |
| CN114064134A (en) * | 2021-11-12 | 2022-02-18 | 上海华元创信软件有限公司 | Self-guiding method and system suitable for embedded SPARC (spatial Power control processor) architecture processor |
| CN114138360A (en) * | 2021-11-12 | 2022-03-04 | 上海华元创信软件有限公司 | Multi-core programming starting method and system of DSP on Flash |
| CN114741137A (en) * | 2022-05-09 | 2022-07-12 | 潍柴动力股份有限公司 | Software starting method, device, equipment and storage medium based on multi-core microcontroller |
| CN114816273A (en) * | 2022-06-27 | 2022-07-29 | 杭州优智联科技有限公司 | Adaptive optimal configuration method, device and medium for Norflash |
| CN115469901A (en) * | 2022-08-16 | 2022-12-13 | 哈尔滨理工大学 | Dual-core DSP (digital signal processor) detachable remote upgrading system and upgrading method |
| CN117215664A (en) * | 2023-08-21 | 2023-12-12 | 白盒子(上海)微电子科技有限公司 | Quick starting method for multi-core DSP of system on chip |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103902305A (en) * | 2012-12-26 | 2014-07-02 | 中国航空工业集团公司第六三一研究所 | Software long-distance loading and solidifying method based on TI DSP |
| CN105323586A (en) * | 2015-04-07 | 2016-02-10 | 佛山世寰智能科技有限公司 | Shared memory interface used for multi-core parallel video coding and decoding |
| CN106293807A (en) * | 2016-07-26 | 2017-01-04 | 中国航空工业集团公司西安飞行自动控制研究所 | A kind of Flash chip based on DSP guides loading method |
| CN106648803A (en) * | 2016-12-30 | 2017-05-10 | 南京科远自动化集团股份有限公司 | Online upgrading method for DSP chip |
| CN107562504A (en) * | 2017-09-11 | 2018-01-09 | 哈尔滨工程大学 | A kind of serial port implementing method of DSP program segmentings loading |
| CN107656773A (en) * | 2017-09-28 | 2018-02-02 | 中国人民解放军国防科技大学 | Multi-core DSP starting method |
| CN108279935A (en) * | 2016-12-30 | 2018-07-13 | 北京中科晶上科技股份有限公司 | A kind of os starting bootstrap technique for system on chip |
-
2018
- 2018-09-01 CN CN201811015884.2A patent/CN109213531A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103902305A (en) * | 2012-12-26 | 2014-07-02 | 中国航空工业集团公司第六三一研究所 | Software long-distance loading and solidifying method based on TI DSP |
| CN105323586A (en) * | 2015-04-07 | 2016-02-10 | 佛山世寰智能科技有限公司 | Shared memory interface used for multi-core parallel video coding and decoding |
| CN106293807A (en) * | 2016-07-26 | 2017-01-04 | 中国航空工业集团公司西安飞行自动控制研究所 | A kind of Flash chip based on DSP guides loading method |
| CN106648803A (en) * | 2016-12-30 | 2017-05-10 | 南京科远自动化集团股份有限公司 | Online upgrading method for DSP chip |
| CN108279935A (en) * | 2016-12-30 | 2018-07-13 | 北京中科晶上科技股份有限公司 | A kind of os starting bootstrap technique for system on chip |
| CN107562504A (en) * | 2017-09-11 | 2018-01-09 | 哈尔滨工程大学 | A kind of serial port implementing method of DSP program segmentings loading |
| CN107656773A (en) * | 2017-09-28 | 2018-02-02 | 中国人民解放军国防科技大学 | Multi-core DSP starting method |
Non-Patent Citations (2)
| Title |
|---|
| 刘大雪; 陈小文; 嵇薇薇; 许邦建: "基于固化代码的多外设多核数字信号处理器启动设计", 《第十九届计算机工程与工艺年会暨第五届微处理器技术论坛论文集》 * |
| 欧斌; 李敬超; 高霞; 徐彬彬: "基于以太网传输的嵌入式多核DSP自启引导", 《微处理机》 * |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109901890A (en) * | 2019-03-07 | 2019-06-18 | 深圳忆联信息***有限公司 | A kind of method, apparatus, computer equipment and the storage medium of controller loading multi-core firmware |
| CN109901890B (en) * | 2019-03-07 | 2020-12-01 | 深圳忆联信息***有限公司 | Method and device for loading multi-core firmware by controller, computer equipment and storage medium |
| CN111008045A (en) * | 2019-11-14 | 2020-04-14 | 中国航空工业集团公司洛阳电光设备研究所 | Automatic loading method for off-chip flash high-capacity program |
| CN111597140A (en) * | 2020-04-27 | 2020-08-28 | 深圳市有方科技股份有限公司 | Multi-core device function configuration method and device |
| CN111597140B (en) * | 2020-04-27 | 2024-06-07 | 深圳市有方科技股份有限公司 | Multi-core equipment function configuration method and device |
| CN112199121B (en) * | 2020-09-28 | 2023-06-06 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | DSP capacity-expanding loading program method according to need |
| CN112199121A (en) * | 2020-09-28 | 2021-01-08 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | DSP capacity-expanding and program-loading method according to needs |
| CN112905395A (en) * | 2021-03-12 | 2021-06-04 | 湖南长城银河科技有限公司 | Self-error-correction starting system for heterogeneous multi-core/many-core microprocessor |
| CN114138360A (en) * | 2021-11-12 | 2022-03-04 | 上海华元创信软件有限公司 | Multi-core programming starting method and system of DSP on Flash |
| CN114138360B (en) * | 2021-11-12 | 2024-03-26 | 上海华元创信软件有限公司 | Multi-core programming starting method and system for DSP (digital Signal processor) on Flash |
| CN114064134A (en) * | 2021-11-12 | 2022-02-18 | 上海华元创信软件有限公司 | Self-guiding method and system suitable for embedded SPARC (spatial Power control processor) architecture processor |
| CN114064134B (en) * | 2021-11-12 | 2024-02-06 | 上海华元创信软件有限公司 | Self-booting method and system suitable for embedded SPARC architecture processor |
| CN114741137B (en) * | 2022-05-09 | 2024-02-20 | 潍柴动力股份有限公司 | Software starting method, device, equipment and storage medium based on multi-core microcontroller |
| CN114741137A (en) * | 2022-05-09 | 2022-07-12 | 潍柴动力股份有限公司 | Software starting method, device, equipment and storage medium based on multi-core microcontroller |
| CN114816273A (en) * | 2022-06-27 | 2022-07-29 | 杭州优智联科技有限公司 | Adaptive optimal configuration method, device and medium for Norflash |
| CN115469901B (en) * | 2022-08-16 | 2023-05-12 | 哈尔滨理工大学 | Dual-core DSP detachable remote upgrading system and upgrading method |
| CN115469901A (en) * | 2022-08-16 | 2022-12-13 | 哈尔滨理工大学 | Dual-core DSP (digital signal processor) detachable remote upgrading system and upgrading method |
| CN117215664A (en) * | 2023-08-21 | 2023-12-12 | 白盒子(上海)微电子科技有限公司 | Quick starting method for multi-core DSP of system on chip |
| CN117215664B (en) * | 2023-08-21 | 2024-06-11 | 白盒子(上海)微电子科技有限公司 | Quick starting method for multi-core DSP of system on chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109213531A (en) | A kind of multi-core DSP based on EMIF16 powers on the simplification implementation method of self-starting | |
| CN107577483B (en) | Method, storage medium, equipment and the system of component engineering calling main works code | |
| CN100470476C (en) | Program bootstrap method after chip power-on | |
| CN103744713A (en) | Autonomous configuration method for FPGA (field programmable gate array)-based embedded dual-core system | |
| JP2005182809A (en) | Creating file system within file in storage technology-abstracted manner | |
| JP2005174307A (en) | System and method for bimodal device virtualization of actual hardware-based device and idealized hardware-based device | |
| CN102681893B (en) | The cross-platform implementation method of executable program and mobile terminal | |
| CN106933610A (en) | Application program installation package generation method and device and electronic equipment | |
| CN101894039A (en) | Auxiliary generating method and system for embedded device driver | |
| CN106648758B (en) | A kind of multi-core processor BOOT activation system and method | |
| KR20170141205A (en) | A central processing unit having a DSP engine and an enhanced context switch function unit | |
| CN105653330A (en) | SD card based NorFlash programming system and method | |
| CN106909441A (en) | The method that a kind of direct I/O of disk based on JVM is accessed | |
| CN108108191A (en) | A kind of collocation method of SOC chip and SOC chip cpu instruction collection | |
| CN108874458A (en) | A kind of the firmware starting method and multicore SoC device of multicore SoC | |
| CN101349973B (en) | Method for dynamically loading embedded type Java processor microcode instruction set | |
| CN109597611A (en) | Front end data flow control Components Development system, method, equipment and storage medium | |
| CN109542484A (en) | A kind of method and system of online updating FPGA configuration chip | |
| CN102629259A (en) | Read-only file system setting up method in embedded system, device and embedded system | |
| Ellul | Run-time compilation techniques for wireless sensor networks | |
| CN111651382A (en) | Parallelization storage implementation method of data acquisition system based on local bus | |
| WO2022000371A1 (en) | Interface generation method and device, and computer-readable storage medium | |
| US20230385040A1 (en) | Splitting vector processing loops with an unknown trip count | |
| CN112631593B (en) | Many-core distributed shared SPM (remote management application) implementation method based on RMA (remote management architecture) | |
| CN117631631B (en) | Domestic DSP embedded system and functional load reconstruction method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190115 |
|
| RJ01 | Rejection of invention patent application after publication |