CN109150354B - Method for calculating compression correction value in time-triggered Ethernet - Google Patents
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Abstract
The invention relates to a method for calculating a compression correction value in a time-triggered Ethernet. And a unified state machine is adopted to control a calculation process, each new pcf time triggers the state conversion of the state machine, and a result of a time correction value can be obtained immediately after an observation window is finished. The method does not need to specify a calculation method before compression calculation, but continuously and dynamically adjusts the calculation method along with the change of the number of reaching pcf frames, so that all the pcf frames do not need to be cached before calculation, and the compression calculation delay can be reduced; the calculation process is controlled and realized by using a simple finite-state machine, the requirement on the number of registers for storing temporary data is low, and the realization of a hardware circuit is facilitated.
Description
Technical Field
The invention relates to a method for realizing time compression correction value based on hardware circuit on compression controller equipment in time-triggered Ethernet.
Background
In the time-triggered ethernet, in order to implement time synchronization of the nodes of the whole network, a compression Controller (CM) needs to periodically set an observation window, receive pcf frames sent by each compression controller, obtain "standard time" acceptable by each SM by calculating an average value of arrival times of the pcf frames, revise its own time to the "standard time", and then notify each SM of its own standard time synchronization. Assuming that i (i ≧ 1) pcf frames are received by the CM in the observation window, with the arrival time of the 1 st frame as a reference, the arrival time difference between the ith frame and the 1 st frame is input [ i ], and it is apparent that input [1] ═ 0, input [ k ] < input [ k +1], and k ═ 1 … i-1. The time-triggered ethernet specification defines a principle of calculating a Compression correction value CC (Compression _ correction).
When i is 1, CC is input [1]
When i is 2, CC is (input [1] + input [2])/2
When i is 3, CC is input [2]
When i is 4, CC is (input [2] + input [3])/2
When i is 5, CC is (input [2] + input [4])/2
When i >5, CC is the arithmetic mean of the kth maximum input and the kth minimum input. Where k is a configurable parameter, e.g., set to 3 in the case of 2 fault tolerance.
The difficulty of CC calculation is that when an observation window starts, how many pcf frames arrive cannot be estimated, so it cannot be determined which calculation method is specifically used, and usually only the arrival time of all the pcf frames is reserved, and after the observation window ends, the calculation of CC is started. This has two disadvantages, one is the large computational delay and the need to save all pcf frame arrival timestamps.
In the time-triggered Ethernet, the smaller the synchronization interval, the higher the synchronization precision of the whole network, and the reduction of the delay of the compression calculation has important significance for reducing the synchronization interval. Therefore, a compression algorithm is needed to be implemented in a faster manner, and particularly, the compression algorithm can be implemented by being embedded into a time-triggered ethernet special chip in a hardware module manner, however, no relevant implementation method is reported at present.
In addition, different SMs may generate a clustering phenomenon in a complex time-triggered ethernet environment, and at this time, each CM may simultaneously open multiple monitoring windows to monitor pcf frames belonging to different integration periods, which is not considered by the present invention.
Disclosure of Invention
The invention provides a method for compressing and calculating time correction value by a CM (CM), which is mainly characterized in that a unified state machine is adopted to control a calculation process, each new pcf triggers the state conversion of the state machine, and the result of the time correction value can be obtained immediately after an observation window is finished; the method comprises the following specific contents:
basic composition of circuit
The method provided by the invention is suitable for being realized by a hardware circuit, is composed of a deviation calculation module, a compression calculation module and a K calculation module as shown in figure 1. The input signals to the circuit include win _ open, Rx _ pit and a parameter K. Changing win _ open from 0 to 1 represents that an observation window is opened, and changing win _ open from 1 to 0 represents that the observation window is closed; rx _ pit represents the time at which one pcf frame is received at a time; the parameter K is a parameter of system operation, is configured during system initialization, and cannot be changed in the operating process. The output signal of the circuit includes the calculated CC value, and the number of frames of pcf _ num that are involved in calculating the value;
the deviation calculation module acquires the opening time of an observation window by monitoring a Win _ open signal, then takes the arrival time of the first pcf frame received after the window is opened as reference time input [1], and simultaneously calculates the difference value input [ i ] between the time of the subsequent arrival of the pcf frame and the reference time, wherein i is greater than 1. Sending the input value corresponding to each pcf group to a compression calculation module and a K calculation module;
the K calculation module acquires the opening time of the observation window by monitoring a Win _ open signal, receives the Kth maximum input value and the Kth minimum input value in a pcf frame in the whole observation window according to a preset K value, and sends the two values to the compression calculation module;
the compression calculation module is a core module of the circuit, monitors the number of received pcf frames after acquiring the opening time of an observation window by monitoring Win _ open signals, continuously adjusts the calculation method of CC according to the number of the received pcf frames, acquires the latest CC value, and immediately outputs the calculation result of CC once receiving a signal that Win _ open is changed from 1 to 0;
(II) deviation calculation module work flow
The deviation calculation module is provided with a First _ input _ pit register;
(1) when receiving the first RX _ pit after detecting that win _ open changes from 0 to 1:
First_input_pit＝Rx_pit；
input＝0；
(2) when a subsequent RX _ pit is received:
Input＝Rx_pit-First_input_pit；
(III) compression calculation module workflow
The work flow of the compression calculation module is controlled by a finite state machine comprising 7 states, as shown in fig. 2. Wherein the state transition condition of the state machine has been indicated in the figure, the solid line with an arrow indicates that a valid input is received, and the dashed arrow indicates that the observation window is closed (win _ open signal goes to 0);
the operation in each state is as follows, where tmp1 and tmp2 are two variable registers used to compute CC;
(1) idle state:
CC＝0；tmp1＝0；tmp2＝0；pcf_num＝0；
(2) r1 State (after receiving the 1 st pcf frame)
CC＝0；tmp1＝0；tmp2＝0；pcf_num＝1；
(3) R2 State (after receiving the 2 nd pcf frame)
CC＝input>>2；tmp1＝input；pcf_num＝2；
Where > > represents an operation that shifts right by two bits, i.e., divides by 2. At this time, the value of input [2] is saved in tmp 1;
(4) r3 State (after receiving the 3 rd pcf frame)
CC＝tmp1，tmp2＝input；pcf_num＝3；
At this time, the value of input [2] is saved in tmp1, and the value of input [3] is saved in tmp 2;
(5) r4 State (after receiving the 4 th pcf frame)
CC＝(tmp1+tmp2)>>2；tmp2＝input；pcf_num＝4；
At this time, the value of input [2] is saved in tmp1, and the value of input [4] is saved in tmp 2;
(6) r5 State (after receiving the 5 th pcf frame)
CC＝(tmp1+tmp2)>>2；pcf_num＝5；
(7) Rx State (receiving the 6 th and subsequent frames)
CC＝(Kmin+Kmax)>>2；pcf_num＝pcf_num+1；
According to the process, when the number of the effective inputs in the window is not more than 5, the calculation algorithm of the CC in each state is completely different, and when the state machine enters an Rx state, the CC is obtained by averaging the Kmax and the Kmin output by the K calculation module, and completely meets the specification requirement;
(IV) K calculation module work flow
The K calculation module mainly monitors the number and time of receiving pcf frames, and calculates the Kth maximum input value and the Kth minimum input value according to the configured parameter K. The K calculation module is controlled by a finite state machine as shown in fig. 3. Where the state transition condition of the state machine has been indicated in the figure, the solid line with the arrow indicates that a valid input has been received, and the dashed arrow indicates that the observation window is closed (win _ open signal goes to 0). If a valid input signal is received in the waitK state, if pcf _ num < K indicates that K valid pcf frames are not received, the state machine still remains in the state, otherwise, the state machine enters the WaitClose state;
the K calculation module reserves two variable registers, Kmin represents the Kth minimum input value till the current, and Kmax represents the Kth maximum input value till the current. Kmax _ tmp [1] … Kmax _ tmp [ K ] is an array with the length of K and is used for temporarily storing relevant input data;
the operation in each state is as follows:
k _ Idle State:
Kmin＝0；Kmax＝0；Kmax_tmp[i]＝0,i＝1…K；
WaitK status:
Kmin＝input；Kmax＝Kmax_tmp[1]；
Kmax_tmp[i]＝Kmax_tmp[i+1],i＝1…K-1；
Kmax[K]＝input；
waitcose state:
Kmax＝Kmax_tmp[1]；
Kmax_tmp[i]＝Kmax_tmp[i+1],i＝1…K-1；
Kmax[K]＝input；
the value of Kmin is actually the input value for pcf _ num of K, so Kmin does not change in the waitcose state until the state machine returns to the Idle state. In the waitclose state, in the array Kmax _ tmp [ K ], Kmax _ tmp [1] is actually the current Kth largest input value, and Kmax _ tmp [ K ] is the current largest input value. Thus in the waitclose state, each time a new valid input value is received, Kmax _ tmp [ i ] will be replaced by Kmax _ tmp [ i +1], i being 1 … K-1. And Kmax _ tmp [ K ] is set to the latest received input value.
The invention has the advantages that: firstly, a calculation method does not need to be specified before compression calculation, but the calculation method is continuously and dynamically adjusted along with the change of the number of arriving pcf frames, so that all the pcf frames do not need to be cached before calculation, and the compression calculation delay can be reduced; secondly, the calculation process is controlled and realized by using a simple finite state machine, the requirement on the number of registers for storing temporary data is low, and the realization of a hardware circuit is facilitated.
Drawings
FIG. 1 is a schematic diagram of a hardware circuit according to the present invention;
fig. 2 and 3 are circuit clock diagrams.
Detailed Description
The calculation method of the compression correction value in the time-triggered Ethernet is suitable for being realized by a hardware circuit. The following problems are also considered in the specific implementation.
One is that the clocks of all circuits are perfectly synchronized and the state machines of fig. 2 and 3 need to be in idle and K _ idle states, respectively, when the reset signal is active. When each clock rising edge arrives, no effective input arrives, and no Win _ open signal changes, the state of the state machine is kept unchanged;
secondly, in practical implementation, RX _ pit, input, and CC signals in fig. 1 need to use extra valid signals with 1 bit width, such as RX _ pit _ v, input _ v, and CC _ v, to identify whether the signals are valid in the current clock cycle. Whether the output pcf _ num signal is effective or not can be identified by CC _ v;
in addition, when the hardware implementation logic can conveniently call FIFO storage resources, the array Kmax _ tmp [ K ] can be implemented by using FIFO with the depth of K, and the Kmax calculation can be further simplified by using the FIFO first-in first-out characteristic. That is, when the FIFO is not full, the received valid input value is written in, and when the FIFO is full and reaches a new input value, only one value needs to be read from the FIFO and discarded (the current input with the K +1 th size), and at the same time, the newly reached input value (the current maximum input) is written in the FIFO. When the observation window is closed, the first input value read from the FIFO is the final Kmax value.
Claims (2)
1. A method for calculating a compression correction value in a time-triggered Ethernet adopts a unified state machine to control a calculation process, each newly arrived pcf triggers the state conversion of the state machine, and a result of the time correction value is obtained immediately after an observation window is finished; the method is characterized by comprising the following specific contents:
basic composition of circuit
The method is implemented using a circuit that,
the circuit comprises a deviation calculation module, a compression calculation module and a K calculation module,
the input signals to the circuit include win _ open, Rx _ pit and a parameter K,
changing win _ open from 0 to 1 represents that an observation window is opened, and changing win _ open from 1 to 0 represents that the observation window is closed;
rx _ pit represents the time at which one pcf frame is received at a time;
the parameter K is a parameter of system operation, is configured during system initialization and is not changed during operation,
the output signal of the circuit comprises a compression correction value CC obtained by calculation and the number of frames pcf _ num of pcf participating in the calculation of the value;
the method comprises the steps that a deviation calculation module obtains the opening time of an observation window by monitoring a Win _ open signal, then the arrival time of a first pcf frame received after the window is opened is used as reference time input [1], the difference value input [ i ] between the time of a subsequent arrival pcf frame and the reference time is calculated, K > i >1 is calculated, and the input value corresponding to each pcf group is sent to a compression calculation module and a K calculation module;
the K calculation module acquires the opening time of the observation window by monitoring a Win _ open signal, receives the Kth maximum input value and the Kth minimum input value in a pcf frame in the whole observation window according to a preset K value, and sends the two values to the compression calculation module;
the compression calculation module is a core module of the circuit, monitors the number of received pcf frames after acquiring the opening time of an observation window by monitoring Win _ open signals, continuously adjusts the calculation method of CC according to the number of the received pcf frames, acquires the latest CC value, and immediately outputs the calculation result of CC once receiving a signal that Win _ open is changed from 1 to 0;
(II) deviation calculation module work flow
The deviation calculation module is provided with a First _ input _ pit register;
(1) when receiving the first RX _ pit after detecting that win _ open changes from 0 to 1:
First_input_pit=Rx_pit；
input=0；
(2) when a subsequent RX _ pit is received:
Input=Rx_pit- First_input_pit；
(III) compression calculation module workflow
The work flow of the compression calculation module is controlled by a finite state machine containing 7 states,
the operation in each state is as follows, where tmp1 and tmp2 are two variable registers used to compute CC;
(1) idle state:
CC=0；tmp1=0；tmp2=0；pcf_num=0；
(2) r1 State, after receiving the 1 st pcf frame
CC=0；tmp1=0；tmp2=0；pcf_num=1；
(3) R2 State, after receiving the 2 nd pcf frame
CC=input>>2；tmp1=input；pcf_num=2；
Where > > represents a right shift by two bits, i.e., a divide by 2 operation, at which time the value of input [2] is saved in tmp 1;
(4) r3 state, after receiving the 3 rd pcf frame;
CC=tmp1，tmp2=input；pcf_num=3；
at this time, the value of input [2] is saved in tmp1, and the value of input [3] is saved in tmp 2;
(5) r4 state, after receiving the 4 th pcf frame;
CC=（tmp1+tmp2）>>2；tmp2=input；pcf_num=4；
at this time, the value of input [2] is saved in tmp1, and the value of input [4] is saved in tmp 2;
(6) r5 state, after receiving the 5 th pcf frame;
CC=（tmp1+tmp2）>>2； pcf_num=5；
(7) rx state, receiving the 6 th and subsequent frames;
CC= （Kmin+Kmax）>>2；pcf_num= pcf_num+1；
according to the process, when the number of the effective inputs in the window is not more than 5, the calculation algorithm of the CC in each state is completely different, and when the state machine enters an Rx state, the CC is obtained by averaging the Kmax and the Kmin output by the K calculation module, and completely meets the specification requirement;
(IV) K calculation module work flow
The K calculation module is mainly used for monitoring the number and time of receiving pcf frames and calculating the Kth maximum input value and the Kth minimum input value according to a configured parameter K, the K calculation module is controlled by a finite state machine, a solid line with an arrow indicates that effective input is received, a dotted arrow indicates that an observation window is closed, an effective input signal is received in a waitK state, if pcf _ num < K indicates that K effective pcf frames are not received, the state machine is still kept in the state, and otherwise the state machine enters a waitClose state;
the K calculation module reserves two variable registers, Kmin represents the current Kth minimum input value, Kmax represents the current Kth maximum input value, and Kmax _ tmp [1] … Kmax _ tmp [ K ] is an array with the length of K and is used for temporarily storing related input data;
the operation in each state is as follows:
k _ Idle State:
Kmin=0；Kmax=0；Kmax_tmp[i]=0,i=1…K；
WaitK status:
Kmin=input；Kmax=Kmax_tmp[1]；
Kmax_tmp[i]= Kmax_tmp[i+1],i=1…K-1；
Kmax[K]=input；
waitcose state:
Kmax=Kmax_tmp[1]；
Kmax_tmp[i]= Kmax_tmp[i+1],i=1…K-1；
Kmax[K]=input。
2. a method of calculating compression corrections in a time triggered ethernet network according to claim 1, characterized in that the value of Kmin is actually the input value when pcf _ num is K, so Kmin does not change any more in the waitcose state, and is saved until the state machine returns to the K _ Idle state, in which case in the array Kmax _ tmp [ K ], Kmax _ tmp [1] is actually the current kth largest input value, Kmax _ tmp [ K ] is the current largest input value, so that in the waitcose state, each time a new valid input value is received, Kmax _ tmp [ i ] will be replaced by Kmax _ tmp [ i +1], i =1 … K-1, and kmjp [ K ] is set to the latest received input value.
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