CN109148460A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing method Download PDFInfo
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- CN109148460A CN109148460A CN201710924295.5A CN201710924295A CN109148460A CN 109148460 A CN109148460 A CN 109148460A CN 201710924295 A CN201710924295 A CN 201710924295A CN 109148460 A CN109148460 A CN 109148460A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5381—Crossover interconnections, e.g. bridge stepovers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention relates to semiconductor device and its manufacturing methods.Semiconductor device includes: contact plug；Wiring is electrically connected with above-mentioned contact plug；Connecting pattern is located at the top of above-mentioned wiring；Air gap is expanded between adjacent contact plug, and between adjacent wiring；And cover film, it is located in above-mentioned wiring and above-mentioned connecting pattern, to provide above-mentioned air gap.
Description
Technical field
The present invention relates to electronic devices, relate more specifically to semiconductor device and its manufacturing method.
Background technique
Even if non-volatile memory device is to have cut off power supply, remains on and be able to maintain depositing for stored data
Memory element.Recently, with the integrated level for the two-dimentional non-volatile memory device for forming storage unit with single layer on substrate
The limit is promoted, the three dimensional nonvolatile memory component that storage unit is vertically laminated on substrate is proposed.
Three dimensional nonvolatile memory component includes the interlayer dielectric being alternately laminated and gate electrode, the ditch through them
Storage unit is laminated along channel film in road film.In order to improve the non-volatile memory device for having such three-dimensional structure
Functional reliability, develop various structures and manufacturing method.
Summary of the invention
One embodiment of the invention provides the semiconductor that manufacturing process is easy and has stable structure and improved characteristic
Device and its manufacturing method.
The semiconductor device of one embodiment of the invention includes: contact plug (Contact plug)；Wiring, and it is above-mentioned
Contact plug electrical connection；Connecting pattern is located at the top of above-mentioned wiring；Air gap, between adjacent contact plug, and
It is expanded between adjacent wiring；And cover film, it is located in above-mentioned wiring and above-mentioned connecting pattern, to provide above-mentioned air gap.
The semiconductor device of one embodiment of the invention includes: wiring；First air gap is defined between above-mentioned wiring
Space；Interstice, is located at the lower part of above-mentioned wiring and above-mentioned first air gap, and is directly connected to above-mentioned first air gap；
And contact plug, it is electrically connected through above-mentioned interstice with above-mentioned wiring.
The manufacturing method of the semiconductor device of one embodiment of the invention includes: the step of forming the first expendable film, wherein
First expendable film includes contact plug；The step of forming the second expendable film, wherein second expendable film includes contacting with above-mentioned
The wiring of embolism connection；In the step of forming connecting pattern on above-mentioned second expendable film；Removal is revealed between above-mentioned connecting pattern
The step of above-mentioned first expendable film and above-mentioned second expendable film out；And covering is formed on above-mentioned wiring and above-mentioned connecting pattern
Film, the step of to provide air gap, wherein the air gap is expanded between adjacent contact plug and between adjacent wiring.
It can provide the semiconductor device for having stable structure and improving reliability.In addition, when manufacturing semiconductor device,
It can reduce the difficulty of process, simplify step, reduce expense.
Detailed description of the invention
Fig. 1 a to Fig. 1 e is the figure for the structure for illustrating the semiconductor device of one embodiment of the invention.
Fig. 2 is the sectional view for showing the structure of semiconductor device for the air gap for being applicable in one embodiment of the invention.
Fig. 3 a to Fig. 5 a, Fig. 3 b to Fig. 5 b, Fig. 5 c, Fig. 5 d, Fig. 6 and Fig. 7 are for illustrating one embodiment of the invention
The figure of the manufacturing method of semiconductor device.
Fig. 8 and Fig. 9 is the block diagram for showing the structure of storage system of one embodiment of the invention.
Figure 10 and Figure 11 is the block diagram for showing the structure of computer system of one embodiment of the invention.
Description of symbols
11: contact plug 12: wiring
13: connecting pattern 14: cover film
17: air gap 21: conductive film
22: insulating film 23: memory film
24: channel film 25: calking insulating film
27: 31: the first substance film of interlayer dielectric
32: the second substance films 33: memory film
34: channel film 35: calking insulating film
37: interlayer dielectric 41: contact plug
42: the first expendable films 43: wiring
44: the second expendable films 45: expendable film
45B: connecting pattern 46: mask pattern
47: cover film
Specific embodiment
In the following, being illustrated to the embodiment of the present invention.In the accompanying drawings, thickness and interval are to indicate for ease of description
, the mode that can be exaggerated than actual physical thickness illustrates.In explaining the present invention, omission and the gist of the invention
Unrelated well known structure.When the structural element to each attached drawing assigns appended drawing reference, for identical structural element, even if
Occur in different drawings, also assigning identical appended drawing reference.
Throughout the specification, when being recorded as certain a part with other parts " connection ", not only include " being directly connected to "
The case where, but also between being included therein across other elements and the case where " connecting indirectly ".Throughout the specification, remembering
When carrying structural element a certain for certain a part of " comprising ", without especially opposite record, it is not offered as excluding it
His structural element, but indicate to may also include other structures element.
Fig. 1 a to Fig. 1 e is the figure for the structure for illustrating the semiconductor device of one embodiment of the invention.Fig. 1 a to Fig. 1 c
It is layout, Fig. 1 d and Fig. 1 e are sectional views.
A to Fig. 1 e referring to Fig.1, the semiconductor device of one embodiment of the invention include contact plug 11, wiring 12, connection
Pattern 13, air gap 17 and cover film 14.In addition, semiconductor device may also include interlayer dielectric 15.
Contact plug 11 arranges (I-I ') and the second direction (II-intersected with first direction (I-I ') in a first direction
II ') on.Here, the contact plug 11 arranged on second direction (II-II ') can arrange in such a way that center is consistent,
The contact plug 12 arranged on one direction (I-I ') can be arranged in a manner of off-centring.Dashed line view is used in Fig. 1 d and Fig. 1 e
The contact plug 11 shown indicates the contact plug 11 for being located at relative rear.
Wiring 12 is located at the top of contact plug 11, expands in parallel on second direction (II-II ').Wiring 12 with connect
It touches embolism 11 to be electrically connected, can have width identical with contact plug 11 or the width narrower than contact plug 11.For example, second
The contact plug 11 arranged on direction (II-II ') may be connected to identical wiring 12.Contact plug 11 can be distinguished with memory string
Connection, wiring 12 can be bit line.In addition, wiring 12 can be copper wiring.
Connecting pattern 13 is located at the top of wiring 12, is arranged in a manner of intersecting with wiring 12.For example, wiring 12 can be
Two directions are expanded on (II-II '), and connecting pattern 13 can be expanded on (I-I ') in parallel in a first direction.Alternatively, connecting pattern 13
It can be expanded in parallel on the third direction intersected with first direction (I-I ') and second direction (II-II ').Connection figure as a result,
Case 13 is at least Chong Die with two wirings 12.As reference, in Fig. 1 d and Fig. 1 e, figure is come with the section on first direction (I-I ')
Show wiring 12, connecting pattern 13 is illustrated with section on second direction (II-II ').
Connecting pattern 13 is for fixed by contact plug 11 and wiring 12 in the fabrication process.Each connecting pattern 13 with extremely
Few two wirings 12 directly connect and form network.As a result, by 13 permanent wiring of connecting pattern, wiring is not only supported
12, additionally it is possible to the contact plug 11 that bearing is connect with wiring 12.
Connecting pattern 13 has various forms in the range of intersecting with wiring 12.For example, connecting pattern 13 can be " Z "
Herringbone pattern, wave pattern or the island for having the linear pattern of different width according to region or arranging at predetermined intervals
Pattern.In addition, in order to which effectively bearing contact embolism 11 and wiring 12, connecting pattern 13 can have than 12 wider width of wiring
(W2>W1)。
Cover film 14 is located at the top of wiring 12 and connecting pattern 13, and cover film 14 may include cover connecting pattern 13 the
A part of 14A and second part 14B for filling the space between adjacent connecting pattern 13.Cover film 14 can by with connecting pattern
13 identical or different substances are formed.For example, connecting pattern 13 and cover film 14 may include NDC (N-Doped SiC: N doping
Silicon carbide).
Air gap 17 is between contact plug 11 and between wiring 12.Here, air gap 17 is between contact plug 11, and
It is expanded between wiring 12.In this case, the upper side of air gap 17 can be prescribed by cover film 14 and connecting pattern 13.
For example, the upper side of the region 17AB Chong Die with connecting pattern 13 in air gap 17 can be prescribed by connecting pattern 13, with
The upper side of the region 17AA of 13 non-overlap of connecting pattern can be prescribed by the second part 14B of cover film 14.In addition, gas
The bottom surfaces of gap 17 can be prescribed by substructures such as interlayer dielectric 15, sandwich.
Air gap 17 can have different structures according to level (level).Air gap 17 may include between wiring 12
The first air gap 17A in space and interstice 17B positioned at the lower part of wiring 12 and the first air gap 17B.That is, air gap 17 includes upper
The first air gap 17A in the portion and interstice 17B of lower part.
Air gap 17 has the structure that the first air gap 17A and interstice 17B are directly connected to.That is, air gap 17 has at one
Interstice 17B is directly connected to the structure of multiple first air gap 17A, is not present between the first air gap 17A and interstice 17B
Seperation film.The capacitor between the capacitor and wiring 12 between contact plug 11 can not only be reduced as a result, but also can be reduced
Capacitor between contact plug 11 and wiring 12.
First air gap 17A is located at level corresponding with wiring 12, and interstice 17B is located at layer corresponding with contact plug 11
Face.B referring to Fig.1, interstice 17B have plate form, and contact plug 11 is connect through interstice 17B with wiring 12.Separately
Outside, c, each first air gap 17A can have wire shaped referring to Fig.1, can expand in parallel on second direction (II-II ').
D referring to Fig.1, each first air gap 17A include the region 17AA and and connecting pattern with 13 non-overlap of connecting pattern
The region 17AB of 13 overlappings.Here, the upper side of the region 17AA of non-overlap can be prescribed by cover film 14, the area of overlapping
The upper side of domain 17AB can be prescribed by connecting pattern 13.Interstice 17B includes the area with 13 non-overlap of connecting pattern
The domain 17BA and region 17BB Chong Die with connecting pattern 13.Here, non-overlap region 17BA and overlapping region 17BB each other
Connection.In addition, non-overlap region 17AA and overlapping region 17AB by wiring 12, connecting pattern 13 and cover film 14 that
This separation, is not directly connected, but connected indirectly by interstice 17B.
Each first air gap 17A can have different height according to region.For example, the area with 13 non-overlap of connecting pattern
The height of domain 17AA can be higher than the height of the region 17AB Chong Die with connecting pattern 13.In this case, the region of non-overlap
17AA to 14 intramedullary expansion of cover film, cover film 14 include slot G in bottom surface.Here, slot G is between adjacent wiring 12.In addition,
Upper side (L2 < L3) of the upper side of the region 17AA of non-overlap lower than connecting pattern 13 and the bottom surfaces higher than connecting pattern 13
Or the upper side (L2 > L1) of wiring 12.
In addition, portion expands the case where air gap 17 is than Fig. 1 d more up.Among e referring to Fig.1, the first adjacent air gap 17A
It is configured across wiring 12, therefore the mode of the first air gap 17AA' of the non-overlap upper side that can surround wiring 12 is expanded to
The inside of cover film 14.In this case, the first adjacent air gap 17AA' can surround the upper side of wiring 12 and be directly connected to.
The structure of such first air gap 17AA' can locally exist, and semiconductor device can include the first air gap 17AA of Fig. 1 d simultaneously
With the first air gap 17AA of Fig. 1 e.
According to such as above-mentioned structure, air gap 17 is between contact plug 11 and between wiring 12.Particularly, wiring 12 it
Between the first air gap 17A and contact plug 11 between interstice 17B be directly connected to, therefore contact bolt can be efficiently reduced
Capacitor between plug 11 and wiring 12.Therefore, the loading that wiring can be reduced when semiconductor device is worked, as a result, can
Enough improve the working characteristics of semiconductor device.In addition, it is by connecting pattern 13 that contact plug 11 and wiring 12 is fixed, therefore
It can prevent them from tilting or being disintegrated.Semiconductor device has stable structure as a result,.
Fig. 2 is the sectional view for showing the structure of semiconductor device of the air gap using one embodiment of the invention.
Referring to Fig. 2, has sandwich ST in the lower part of contact plug 11.Sandwich ST may include the conduction being alternately laminated
Film 21 and insulating film 22.It as an example can be that at least one conductive film 21 of topmost is top selection line in conductive film 21,
At least one conductive film 21 of lowest part is lower part selection line, and remaining conductive film 21 is wordline.It can be as another example, lead
At least one conductive film 21 of topmost is selection line in electrolemma 21, at least one conductive film 21 of lowest part is pipe grid (pipe
Gate), remaining conductive film 21 is wordline.
Channel structure CH runs through sandwich ST, is electrically connected with contact plug 11.Each channel structure CH may include ditch
Road film 24, memory film 23 and pad 26.The side wall of the encirclement channel film 24 of memory film 23, it may include charge barrier film, data
At least one of storage film and tunnel insulator film.Here, data storage film may include floating gate, charge trap film, nano dot, phase
Become substance, resistance-variable substance etc..Channel film 24 can have the structure being filled up completely until central area or central area is opened
The pipe structure put.It can be filled with calking insulating film 25 in the central area of the opening of channel film 24.In addition, pad 26 includes conduction
Property substance, is electrically connected with channel structure CH and contact plug 11 respectively.In the accompanying drawings, it is indicated with the channel structure CH that dotted line illustrates
Positioned at the channel structure CH of relative rear.
It is arrived in interlayer dielectric 27 in addition, air gap 17 is expansible.Interstice 17B is expanded to lower part, passes through layer insulation
Film 27 or substructure object carry out the bottom surfaces of regulation interstice 17B.As an example, interstice 17B be expanded to pad 26 it
Between, thus, reduce the capacitor etc. between capacitor, pad 26 and the contact plug 11 between pad 26.As another example, the second gas
Gap 17B is expansible between channel structure CH.In this case, the position of the bottom surfaces of interstice 17B is higher than topmost
The position of the upper side of conductive film 21.That is, interstice 17B is to the lower part in the range of not exposing conductive film 21 of topmost
Expansion.
It, can be in the semiconductor device of three-dimensional structure for including the storage unit of stacking using this according to such as above-mentioned structure
The air gap 17 of one embodiment of invention.In the case where the semiconductor device of three-dimensional structure, memory string is vertically aligned, therefore
Narrower intervals between bit line.Cause the capacitor between bit line as a result, to increase, be loaded into the problems such as increasing.
But an embodiment according to the present invention, the air gap 17 between contact plug 11 are expanded between wiring 12.
Even if the interval as a result, between such as bit line of wiring 12 is reduced, can also be efficiently reduced between wiring 12 by air gap 17
Capacitor.Moreover, additionally it is possible to efficiently reduce between capacitor, contact plug 11 and the wiring 12 between contact plug 11
Capacitor etc. between capacitor, pad 26.
Fig. 3 a to Fig. 5 a, Fig. 3 b to Fig. 5 b, Fig. 5 c, Fig. 5 d, Fig. 6 and Fig. 7 are for half to one embodiment of the invention
The figure that the manufacturing method of conductor device is illustrated.The a figure respectively numbered is layout, and the b figure respectively numbered to d is schemed and Fig. 6 and 7 is
Sectional view.In the following, omit with the above-mentioned duplicate content of description and be illustrated.
Referring to Fig. 3 a and Fig. 3 b, the first expendable film 42 including contact plug 41 is formed on interlayer dielectric 37.For example,
It can be formed after forming the first expendable film 42 through multiple holes of the first expendable film 42.First expendable film 42 can be oxidation
Film, etchable oxidation film and form hole.Furthermore it is possible to which the mode until extending through interlayer dielectric 37 forms hole.Here, hole is arranged
Be listed in first direction (I-I ') and the second direction (II-II ') intersected with first direction (I-I ') on.Here, in second direction
The hole arranged on (II-II ') can arrange in such a way that center is consistent, and the hole arranged on (I-I ') in a first direction can be in
The mode of heart offset arranges.In addition, each hole can have with close lower part and the tapered cross-section of width reduction.Then, Xiang Kong
Interior filling conductive film and form contact plug 41.The contact plug 41 shown in dotted line is indicated positioned at relative rear in the accompanying drawings
Contact plug 41.
As reference, addition forms substructure object before forming interlayer dielectric 37.In the present embodiment, to conduct
Substructure object and formed and include the case where that the sandwich ST of memory string is shown.In the following, to forming sandwich ST's
Method is simply described as follows.
Firstly, the first substance film 31 and the second substance film 32 are alternately laminated and form sandwich ST.Then, it is being formed
After the hole of sandwich ST, memory film 33, channel film 34 and calking insulating film 35 are sequentially formed in each hole.It connects
, after making the recessed a part of thickness of the calking insulating film 35 in channel film 34, pad 36 is formed in recessed area.Then,
It can implement additional process according to the substance of first and second substance film 31.It as an example, is expendable film in the first substance film 31,
In the case that second substance film 32 is insulating film, the first substance film 31 is replaced by conductive film.As another example, in the first substance film
31 be conductive film, in the case that the second substance film 32 is insulating film, by 31 silication of the first substance film.It is used as another example again, the
One substance film 31 is that conductive film replaces the second substance film 32 with insulating film in the case that the second substance film 32 is expendable film.By
This, forms the sandwich ST of the storage unit including stacking.
In addition, the substructure object for having various structure and functions can be formed before forming contact plug 41.Exist as a result,
In attached drawing later, omits substructure object and illustrated.
Referring to Fig. 4 a and Fig. 4 b, the second expendable film 44 including wiring 43 is formed on the first expendable film 42.Wiring 43
It can be expanded in parallel on second direction (II-II '), can be bit line.In addition, wiring 43 can be copper film.Second expendable film
44 can be formed by substance identical with the first expendable film 42.For example, the second expendable film 44 can be oxidation film.
For example, formed on the first expendable film 42 after second expendable film 44, formed through the second expendable film 44 and the
The groove expanded on two directions (II-II ').Here, groove is formed as the depth for exposing contact plug 41.Then, to fill ditch
The mode of slot forms conductive film on the second expendable film 44, then makes conductive film in a manner of exposing the surface of the second expendable film 44
Become flat.Wiring 43 is formed as a result,.Each wiring 43 can be with the electricity of contact plug 41 that arranges on second direction (II-II ')
Connection.
As reference, conductive film can also be directly patterned and form wiring 43.For example, on the first expendable film 42
After forming conducting film, conductive film is etched and forms wiring 43.Then, the second expendable film is filled in the space between wiring 43
44。
Referring to Fig. 5 a, connecting pattern 45B is formed on the second expendable film 44.Here, each connecting pattern 45B is located at wiring
43 top at least intersects with two wirings 43.In this attached drawing, as an example, illustrates and expand on (I-I ') in a first direction
The connecting pattern 45B for the wire shaped opened, but the shape of connecting pattern 45B, width can be changed to various.
Fig. 5 b to Fig. 5 d is the sectional view for showing the specific forming method of connecting pattern 45B.Firstly, being wrapped referring to Fig. 5 b
Include formation junctional membrane 45 on the second expendable film 44 of wiring 43.Junctional membrane 45 is by losing the first expendable film 42 and the second expendable film 44
Selection is carved to be formed than big substance.For example, junctional membrane 45 includes NDC (N-Doped SiC).In addition, junctional membrane 45 considers at 2 times
The thickness that is lost in etching process and be formed as sufficient thickness.For example, junctional membrane 45 hasExtremelyThickness.
Referring to Fig. 5 c, mask pattern 46 is formed on junctional membrane 45.Mask pattern 46 is used to be patterned junctional membrane 45,
It can be photoresist pattern.Then, by mask pattern 46 as etch stop layer (Etching barrier) and to connection
Film 45 carries out 1 etching to form groove T.At this point, junctional membrane 45 is not etched fully, but remained in the lower part of groove T
The junctional membrane 45 of a part of thickness.For example, to junctional membrane 45 in such a way that the 1/3 of the whole thickness for remaining junctional membrane 45 is below
A part of thickness is etched.Thus, it is possible to which the wiring 43 of lower part is prevented to be exposed.In this attached drawing, by appended drawing reference " 45A "
To illustrate the junctional membrane for etching a part of thickness.
Referring to Fig. 5 d, mask pattern 46 is removed.It, can be not due to only etched a part of thickness of junctional membrane 45A
Mask pattern 46 is removed in the state of the wiring 43 of exposing lower part.Then, in the case where the mask not set separately, to junctional membrane
45A carries out 2 etchings.For example, being etched using etch-back (Etch back) process to junctional membrane 45A.It as a result, will be residual
It stays and is fully etched in the junctional membrane 45A of the lower part of groove T and forms connecting pattern 45B.Here, 46 removing step of mask pattern and
2 etching work procedures of junctional membrane 45A (in-situ) can carry out in situ.
If junctional membrane 45 is fully etched in 1 etching work procedure and exposes wiring 43 in the bottom surface of groove T, then
Mask pattern 46 is removed in the state of exposing wiring 43.But be copper wiring in wiring 43, mask pattern 46 is photoresist
In the case where agent pattern, copper wiring is caused to be damaged during by photoresist pattern molding.As a result, in the present embodiment
It etches junctional membrane 45 in two steps and forms connecting pattern 45B, so that wiring 43 be prevented to be damaged.
Referring to Fig. 6, the first expendable film 42 and the second expendable film 44 exposed between connecting pattern 45B is removed.Make as a result,
The space opening between space and contact plug 41 between wiring 43.At this point, contact plug 41 and wiring 43 are with shape outstanding
State remains on empty space, fixes contact plug 41 and wiring 43 by connecting pattern 45B.Thereby, it is possible to prevent from removing
Contact plug 41 and the inclination of wiring 43 or disintegration during first expendable film 42 and the second expendable film 44.
As reference, it is illustrated as the case where not removing and remain interlayer dielectric 37 in this attached drawing, but can also remove
The film of lower part is also removed together during first expendable film 42 and the second expendable film 44.For example, as before referring to Fig. 2 institute
Illustrate, the interlayer dielectric 37 for being located at the lower part of contact plug 41 can be removed a part, make the regional opening between pad 26.
Referring to Fig. 7, cover film 47 is formed on wiring 32 and connecting pattern 45B.Cover film 47 may include covering connection figure
The first part 47A of the case 45B and second part 47B for filling the space between adjacent connecting pattern 45B.Pass through cover film 47
Carry out regulation air gap 48, air gap 48 is expanded between adjacent contact plug 41 and between adjacent wiring 43.
Air gap 48 may include the first air gap 48A being defined between wiring 43 and be defined between contact plug 43
Interstice 48B.In addition, air gap 48, which can have, is directly connected to the structure of multiple first air gap 48A in an interstice 48B.
The bottom surfaces of air gap 48 are prescribed by interlayer dielectric 37, and the upper side of air gap 48 passes through connecting pattern 45B and cover film
47 and be prescribed.In addition, as described above, interior expansion or to the lower part works expansion of the air gap 48 to cover film 47.
Cover film 47 can be formed using vapour deposition method.In addition, being covered to easily provide air gap 48 using relatively step
Cover film 47 is deposited in lid (step coverage) bad vapour deposition method.For example, NDC (N-DopedSiC) is deposited to be formed
Cover film 47.
In the case where forming cover film 47 using vapour deposition method, along between connecting pattern 45B and connecting pattern 45B
The surface of the wiring 43 of exposing and covering material is deposited.Particularly, using the bad vapour deposition method of step coverage,
Covering material is not deposited along the surface of connecting pattern 45B and wiring 43 and with uniform thickness, in connecting pattern 45B
And covering material is deposited with suspended structure in the surface of wiring 43.It may be deposited in the bottom surface of the second part 47B of cover film 47 as a result,
Suspended structure in two sides connects and the slot G that generates, and air gap 48 may be to 47 interior expansion of cover film.In this case, each
In a first air gap 48A, it is higher than the area Chong Die with connecting pattern 45B with the height of the region 48AA of connecting pattern 45B non-overlap
The height of domain 48AB.In addition, the first adjacent air gap 48AA can surround the upper side positioned at the wiring 43 between them and direct
Connection.
According to such as above-mentioned manufacturing method, utilized using connecting pattern 45B as supporting station, it can be by the first expendable film 42
It is removed together with the second expendable film 44.In addition, can be prevented during removing the first expendable film 42 and the second expendable film 44
Contact plug 41 and wiring 43 tilt.Thereby, it is possible to form semiconductor device with stable structure.
Fig. 8 is the block diagram for showing the structure of storage system of one embodiment of the invention.
Referring to Fig. 8, the storage system 1000 of one embodiment of the invention includes storage device 1200 and controller 1100.
Storage device 1200 is used to store the data information of various data shapes as text, figure, software code etc..
Storage device 1200 can be nonvolatile memory.In addition, storage device 1200 can have above-mentioned a referring to Fig.1 to Fig. 7 and
The structure of explanation, and the manufacturing method that is illustrated according to above-mentioned a referring to Fig.1 to Fig. 7 is manufactured.As embodiment, deposit
Storage device 1200 can include: contact plug；Wiring is electrically connected with above-mentioned contact plug；Connecting pattern is located at above-mentioned wiring
Top；Air gap is expanded between adjacent contact plug, and between adjacent wiring；And cover film, it is located at upper
It states in wiring and above-mentioned connecting pattern, to provide above-mentioned air gap.The structure and manufacturing method and above description of storage device 1200
The case where it is identical, therefore omit illustrate.
Controller 1100 is connect with host and storage device 1200, is carried out response to the request from host and is accessed storage
Device 1200.For example, controller 1100 carries out reading and writing, deletion, background (background) movement etc. of storage device 1200
Control.
Controller 1100 includes RAM (Random Access Memory: random access memory；1110),CPU
(Central Processing Unit: central processing unit；1120), host interface (Host Interface；1130), ECC electricity
Road (Error Correction Code Circuit: error-correcting code circuit；1140), memory interface (Memory
Interface；1150) etc..
Here, RAM 1110 can be used as the high speed between the working storage of CPU 1120, storage device 1200 and host
Buffer storage etc. between buffer storage, storage device 1200 and host.As reference, RAM 1110 can be by SRAM
(Static Random Access Memory: static random access memory), ROM (Read Only Memory: read-only to deposit
Reservoir) etc. replace.
CPU 1120 controls the molar behavior of controller 1100.For example, the operation of CPU 1120 is stored in RAM
1110 flash translation layer (FTL) (Flash Translation Layer；FTL firmware as).
Host interface 1130 executes the interface between host and connects.For example, controller 1100 can pass through USB
(Universal Serial Bus: universal serial bus) agreement, MMC (Multi Media Card: multimedia card) agreement,
PCI (Peripheral Component Interconnection: peripheral component interconnection) agreement, PCI-E (PCI-Express)
Agreement, ATA (Advanced Technology Attachment: advanced technology attachment) agreement, serial ATA (Serial-ATA)
Agreement, Parallel ATA (Parallel-ATA) agreement, SCSI (Small Computer Small Interface: minicomputer
Low profile interface) agreement, ESDI (Enhanced Small Disk Interface: enhancing minidisk interface) agreement and IDE
It is various as (Integrated Drive Electronics: integrated driving electronics) agreement, individual (private) agreement etc.
At least one of interface protocol and communicated with host.
ECC circuit 1140 detects the mistake for including from the data that storage device 1200 is read using error correcting code ECC, and
It is corrected.
Memory interface 1150 executes the interface between storage device 1200 and connects.For example, memory interface 1150 wraps
Include NAND Interface or NOR interface.
As reference, controller 1100 further includes the buffer storage (not shown) for interim storing data.Here, slow
It rushes memory and can be used for temporarily storing and external data are transmitted to by host interface 1130 or interim storage passes through memory
Interface 1150 and the data transmitted from storage device 1200.In addition, controller 1100 further includes storage for carrying out and host
The ROM of the code data of interface connection.
In this way, the storage system 1000 of one embodiment of the invention includes the storage for improving integrated level and improving characteristic
Device 1200, therefore the integrated level and characteristic of storage system 1000 can also be improved.
Fig. 9 is the block diagram for showing the structure of storage system of one embodiment of the invention.In the following, omission and above description
The duplicate content of content and be illustrated.
Referring to Fig. 9, the storage system 1000' of one embodiment of the invention includes storage device 1200' and controller
1100.In addition, controller 1100 includes RAM 1110, CPU 1120, host interface 1130, ECC circuit 1140, memory interface
1150 etc..
Storage device 1200' can be nonvolatile memory.In addition, storage device 1200' can have above-mentioned reference
Fig. 1 a to Fig. 7 and the structure being illustrated, and pass through manufacturing method that above-mentioned a referring to Fig.1 to Fig. 7 is illustrated and carry out
Manufacture.As embodiment, storage device 1200' includes: contact plug；Wiring is electrically connected with above-mentioned contact plug；Connection figure
Case is located at the top of above-mentioned wiring；Air gap is expanded between adjacent contact plug, and between adjacent wiring；
And cover film, it is located in above-mentioned wiring and above-mentioned connecting pattern, to provide above-mentioned air gap.The structure of storage device 1200' and
The case where manufacturing method is with above description is identical, therefore omits and illustrate.
In addition, storage device 1200' is the multi-chip encapsulation body being made of multiple memory chips.Multiple memory chips
It is divided into multiple groups, multiple groups are communicated by first to kth channel (CH1~CHk) with controller 1100.In addition, belonging to
The memory chip of one group is communicated by sharing channel with controller 1100.As reference, can also be deformed into
One channel connects the storage system 1000' of a memory chip.
In this way, the storage system 1000' of one embodiment of the invention includes the storage for improving integrated level and improving characteristic
Device 1200', therefore the integrated level and characteristic of storage system 1000' can also be improved.Particularly, pass through multi-chip encapsulation body
Storage device 1200' is constituted, to increase the data storage capacity of storage system 1000', improves driving speed.
Figure 10 is the block diagram for showing the structure of computer system of one embodiment of the invention.In the following, omitting and above stating
The duplicate content of bright content and be illustrated.
Referring to Fig.1 0, the computer system 2000 of one embodiment of the invention include storage device 2100, CPU 2200,
RAM 2300, user interface 2400, power supply 2500, system bus 2600 etc..
Storage device 2100 stores the data provided by user interface 2400, the data handled by CPU 2200
Deng.In addition, storage device 2100 passes through system bus 2600 and CPU 2200, RAM 2300, user interface 2400, power supply
2500 equal electrical connections.For example, storage device 2100 is connect by controller (not shown) with system bus 2600 or and system
Bus 2600 is directly connected to.In the case where storage device 2100 and system bus 2600 are directly connected to, by CPU 2200,
RAM 2300 etc. and the function of executing controller.
Here, storage device 2100 can be nonvolatile memory.In addition, storage device 2100 has above-mentioned reference
Fig. 1 a to Fig. 7 and the structure illustrated, and manufacturing method that above-mentioned a referring to Fig.1 to Fig. 7 illustrates can be passed through and be manufactured.
As embodiment, storage device 2100 includes: contact plug；Wiring is electrically connected with above-mentioned contact plug；Connecting pattern,
Positioned at the top of above-mentioned wiring；Air gap is expanded between adjacent contact plug, and between adjacent wiring；And it covers
Epiphragma is located in above-mentioned wiring and above-mentioned connecting pattern, to provide above-mentioned air gap.The structure of storage device 2100 and manufacturer
The case where method is with above description is identical, therefore omits and illustrate.
In addition, storage device 2100 can be the multi-chip envelope being made of multiple memory chips as referring to illustrated by Fig. 9
Fill body.
The computer system 2000 for having such structure can be computer, UMPC (Ultra Mobile PC: super shifting
Dynamic personal computer), work station, net book (net-book), PDA (Personal Digital Assistants: a number
Word assistant), portable computer (portable computer), web tablet computer (web tablet), radiophone
(wireless phone), mobile phone (mobile phone), smart phone (smart phone), e-book (e-book),
PMP (Portable Multimedia Player: portable media player), portable game machine, navigation
(navigation) device, flight data recorder (blackbox), digital camera (digital camera), stereotelevision (3-
Dimensional television), digital audio tape (digital audio recorder), digital speech player
(digital audio player), digital video recorder (digital picture recorder), digital image play
Device (digital picture player), digital VTR (digital video recorder), video frequency player
(digital video player), the device received and sent messages in the wireless context, the various electronic devices for constituting home network
In one, constitute computer network various electronic devices in one, constitute teleprocessing network various electronics
One in device, RFID device etc..
In this way, the computer system 2000 of one embodiment of the invention includes the storage dress for improving integrated level and improving characteristic
2100 are set, therefore the characteristic of computer system 2000 can also be improved.
Figure 11 is the block diagram for showing the computer system of one embodiment of the invention.
Referring to Fig.1 1, the computer system 3000 of one embodiment of the invention includes having operating system 3200, using journey
The software layers such as sequence 3100, file system 3300, conversion layer 3400.In addition, computer system 3000 includes storage device 3500 etc.
Hardware layer.
Operating system 3200 can be controlled for being managed to software, the hardware resource etc. of computer system 3000
The program of central processor executes.Application program 3100, can be with as the various application programs implemented in computer system 3000
It is the utility program (utility) executed by operating system 3200.
The expression of file system 3300 is patrolled for what is be managed to data, the file etc. that are present in computer system 3000
Structure is collected, the systematism of the file or data that store storage device 3500 etc. is realized according to rule.It can be according to calculating
Operating system 3200 used in machine system 3000 and determine file system 3300.For example, being Microsoft in operating system 3200
(Microsoft) in the case where window-operating (Windows) system of company, file system 3300 can be FAT (File
Allocation Table: file allocation table), NTFS (NT file system:NT file system) etc..In addition, being in operation
In the case that system 3200 is outstanding Knicks/inner Knicks (Unix/Linux) system, file system 3300 can be EXT
(extended file system: extension file system), UFS (Unix File System:Unix file system), JFS
(Journaling File System: log file system) etc..
In this attached drawing by operating system 3200, application program 3100 and file system 3300 as independent module and into
Diagram is gone, but application program 3100 and file system 3300 may include in operating system 3200.
Conversion layer (Translation Layer；3400) response is carried out to the request from file system 3300 and by ground
Location is converted into the form suitable for storage device 3500.For example, the logical address that conversion layer 3400 generates file system 3300 turns
Change the physical address of storage device 3500 into.Turn here, can store the map information of logical address and physical address to address
Change table (address translation table).For example, conversion layer 3400 can be flash translation layer (FTL) (Flash
Translation Layer；FTL), Common Flash Memory link layer (Universal Flash Storage Link Layer, ULL)
Deng.
Storage device 3500 can be nonvolatile memory.In addition, storage device 3500 can have above-mentioned reference figure
1a to Fig. 7 and the structure illustrated, and manufacturing method that above-mentioned a referring to Fig.1 to Fig. 7 illustrates can be passed through and be manufactured.Make
For embodiment, storage device 3500 includes: contact plug；Wiring is electrically connected with above-mentioned contact plug；Connecting pattern, position
In the top of above-mentioned wiring；Air gap between adjacent contact plug, and is expanded between adjacent wiring；And covering
Film is located in above-mentioned wiring and above-mentioned connecting pattern, to provide above-mentioned air gap.The structure and manufacturing method of storage device 3500
The case where with above description, is identical, therefore omits and illustrate.
Have such structure computer system 3000 divide operating system layer to be executed in upper rank region and
The controller layer that the next rank region executes.Here, application program 3100, operating system 3200 and file system 3300 are included in
In operating system layer, driven by the working storage of computer system 3000.In addition, conversion layer 3400 is included in behaviour
Make system layer or controller layer.
In this way, the computer system 3000 of one embodiment of the invention includes the storage dress for improving integrated level and improving characteristic
3500 are set, therefore the characteristic of computer system 3000 can also be improved.
Here, physical record has been carried out according to embodiment and to technical idea of the invention, it is however noted that, on
Embodiment is stated for being illustrated to technical idea of the invention, rather than for being defined to technical idea of the invention.
In addition, it should be understood by those skilled in the art that the present invention can realize various embodiments within the scope of technical idea.
Claims (35)
1. a kind of semiconductor device, the semiconductor device include:
Contact plug；
Wiring is electrically connected with above-mentioned contact plug；
Connecting pattern is located at the top of above-mentioned wiring；
Air gap is expanded between adjacent contact plug, and between adjacent wiring；And
Cover film is located in above-mentioned wiring and above-mentioned connecting pattern, to provide above-mentioned air gap.
2. semiconductor device according to claim 1, wherein
The interior expansion with the region of above-mentioned connecting pattern non-overlap to above-mentioned cover film in above-mentioned air gap.
3. semiconductor device according to claim 1, wherein
Above-mentioned air gap includes the region Chong Die with above-mentioned connecting pattern and the region with above-mentioned connecting pattern non-overlap, above-mentioned non-heavy
The height in folded region is higher than the height in the region of above-mentioned overlapping.
4. semiconductor device according to claim 1, wherein
The upper side with the upper side in the region of above-mentioned connecting pattern non-overlap lower than above-mentioned connecting pattern in above-mentioned air gap and
Higher than the bottom surfaces of above-mentioned connecting pattern.
5. semiconductor device according to claim 1, wherein
The interior expansion with the region of above-mentioned connecting pattern non-overlap to above-mentioned cover film in above-mentioned air gap, and surround with it is above-mentioned
The upper side of the wiring of connecting pattern non-overlap.
6. semiconductor device according to claim 1, wherein
Above-mentioned cover film includes:
Cover the first part of above-mentioned connecting pattern；And
The second part in the space between above-mentioned connecting pattern is filled,
The bottom surface of above-mentioned second part includes the slot between adjacent wiring.
7. semiconductor device according to claim 1, wherein
Above-mentioned connecting pattern includes nitrogen doped silicon carbide.
8. semiconductor device according to claim 1, wherein
Above-mentioned cover film includes nitrogen doped silicon carbide.
9. semiconductor device according to claim 1, wherein
The semiconductor device further include:
Sandwich is located at the lower part of above-mentioned contact plug, and conductive film and insulating film including being alternately laminated；
Channel film runs through above-mentioned sandwich；And
Above-mentioned channel film and above-mentioned contact plug are electrically connected by pad respectively.
10. semiconductor device according to claim 9, wherein
Above-mentioned air gap is expanded between above-mentioned pad.
11. semiconductor device according to claim 1, wherein
Above-mentioned wiring is bit line.
12. semiconductor device according to claim 1, wherein
Above-mentioned wiring is expanded to first direction, and above-mentioned connecting pattern is expanded to the second direction intersected with above-mentioned first direction.
13. semiconductor device according to claim 1, wherein
Each above-mentioned connecting pattern has than above-mentioned wiring wider width.
14. semiconductor device according to claim 1, wherein
Each above-mentioned connecting pattern is at least above-mentioned with line overlap with two.
15. a kind of semiconductor device, the semiconductor device include:
Wiring；
First air gap is defined in the space between above-mentioned wiring；
Interstice, is located at the lower part of above-mentioned wiring and above-mentioned first air gap, and is directly connected to above-mentioned first air gap；And
Contact plug is electrically connected through above-mentioned interstice with above-mentioned wiring.
16. semiconductor device according to claim 15, wherein
The semiconductor device further include:
Connecting pattern is located at the top of above-mentioned wiring in a manner of intersecting with above-mentioned wiring；And
Cover film covers above-mentioned wiring and above-mentioned connecting pattern.
17. semiconductor device according to claim 16, wherein
The upper side of above-mentioned first air gap is provided by above-mentioned connecting pattern and above-mentioned cover film.
18. semiconductor device according to claim 16, wherein
Each above-mentioned first air gap includes the region Chong Die with above-mentioned connecting pattern and the region with above-mentioned connecting pattern non-overlap,
Interior expansion of the region of above-mentioned non-overlap to above-mentioned cover film.
19. semiconductor device according to claim 16, wherein
Above-mentioned connecting pattern includes nitrogen doped silicon carbide.
20. semiconductor device according to claim 16, wherein
Above-mentioned cover film includes nitrogen doped silicon carbide.
21. a kind of manufacturing method of semiconductor device, comprising:
The step of forming the first expendable film, wherein first expendable film includes contact plug；
The step of forming the second expendable film, wherein second expendable film includes the wiring connecting with above-mentioned contact plug；
In the step of forming connecting pattern on above-mentioned second expendable film；
The step of removing above-mentioned first expendable film and above-mentioned second expendable film exposed between above-mentioned connecting pattern；And
Cover film is formed on above-mentioned wiring and above-mentioned connecting pattern, the step of to provide air gap, wherein the air gap is located at adjacent
Contact plug between and expand between adjacent wiring.
22. the manufacturing method of semiconductor device according to claim 21, wherein
The step of forming above-mentioned connecting pattern include:
In the step of forming junctional membrane on above-mentioned second expendable film；
In the step of forming mask pattern on above-mentioned junctional membrane；
The step of a part of thickness of above-mentioned junctional membrane is etched using aforementioned mask pattern as etch stop layer；
The step of removing aforementioned mask pattern；And
The step of is carried out by etch-back and forms above-mentioned connecting pattern for the above-mentioned junctional membrane for etching a part of thickness.
23. the manufacturing method of semiconductor device according to claim 22, wherein
Aforementioned mask pattern is photoresist pattern, and above-mentioned wiring is copper wiring.
24. the manufacturing method of semiconductor device according to claim 21, wherein
Above-mentioned connecting pattern is intersected with above-mentioned wiring, the above-mentioned connection when removing above-mentioned first expendable film and above-mentioned second expendable film
Pattern supports above-mentioned wiring and above-mentioned contact plug.
25. the manufacturing method of semiconductor device according to claim 21, wherein
In the step of forming above-mentioned cover film, above-mentioned cover film is formed by the bad vapour deposition method of step coverage.
26. the manufacturing method of semiconductor device according to claim 25, wherein
Above-mentioned cover film includes:
Cover the first part of above-mentioned connecting pattern；And
The second part in the space between adjacent connecting pattern is filled,
The bottom surface of above-mentioned second part includes the slot between adjacent wiring.
27. the manufacturing method of semiconductor device according to claim 21, wherein
The interior expansion with the region of above-mentioned connecting pattern non-overlap to above-mentioned cover film in above-mentioned air gap.
28. the manufacturing method of semiconductor device according to claim 21, wherein
It is higher than the region Chong Die with above-mentioned connecting pattern with the height in the region of above-mentioned connecting pattern non-overlap in above-mentioned air gap
Height.
29. the manufacturing method of semiconductor device according to claim 21, wherein
The upper side of air gap between adjacent connecting pattern is lower than the upper side of above-mentioned connecting pattern and is higher than above-mentioned company
The bottom surfaces of map interlinking case.
30. the manufacturing method of semiconductor device according to claim 21, wherein
The interior expansion with the region of above-mentioned connecting pattern non-overlap to above-mentioned cover film in above-mentioned air gap, and surround with it is above-mentioned
The upper side of the wiring of connecting pattern non-overlap.
31. the manufacturing method of semiconductor device according to claim 21, wherein
Above-mentioned connecting pattern includes nitrogen doped silicon carbide.
32. the manufacturing method of semiconductor device according to claim 21, wherein
Above-mentioned cover film includes nitrogen doped silicon carbide.
33. the manufacturing method of semiconductor device according to claim 21, further includes:
Before forming above-mentioned contact plug, the step of forming sandwich, wherein the sandwich includes the conduction being alternately laminated
Film and insulating film；
The step of forming the channel film for running through above-mentioned sandwich；And
The step of forming pad, wherein above-mentioned channel film and above-mentioned contact plug for being electrically connected by the pad respectively.
34. the manufacturing method of semiconductor device according to claim 33, wherein
Above-mentioned air gap is expanded between above-mentioned pad.
35. the manufacturing method of semiconductor device according to claim 21, wherein
Above-mentioned wiring is bit line.
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| KR10-2017-0081379 | 2017-06-27 | ||
| KR1020170081379A KR20190001419A (en) | 2017-06-27 | 2017-06-27 | Semiconductor device and manufacturing method thereof |
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| KR20210031170A (en) | 2019-09-11 | 2021-03-19 | 에스케이하이닉스 주식회사 | Electronic device and method for fabricating the same |
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|---|---|---|---|---|
| US20080042268A1 (en) * | 2006-08-21 | 2008-02-21 | Samsung Electronics Co., Ltd. | Void boundary structures, semiconductor devices having the void boundary structures and methods of forming the same |
| CN101447501A (en) * | 2007-11-29 | 2009-06-03 | 株式会社瑞萨科技 | Semiconductor device and method of manufacturing the same |
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2017
- 2017-06-27 KR KR1020170081379A patent/KR20190001419A/en unknown
- 2017-09-30 CN CN201710924295.5A patent/CN109148460B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080042268A1 (en) * | 2006-08-21 | 2008-02-21 | Samsung Electronics Co., Ltd. | Void boundary structures, semiconductor devices having the void boundary structures and methods of forming the same |
| CN101447501A (en) * | 2007-11-29 | 2009-06-03 | 株式会社瑞萨科技 | Semiconductor device and method of manufacturing the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024093031A1 (en) * | 2022-11-04 | 2024-05-10 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
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