CN109148417A - A kind of hybrid bonded structure and method of wafer - Google Patents
A kind of hybrid bonded structure and method of wafer Download PDFInfo
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- CN109148417A CN109148417A CN201811018709.9A CN201811018709A CN109148417A CN 109148417 A CN109148417 A CN 109148417A CN 201811018709 A CN201811018709 A CN 201811018709A CN 109148417 A CN109148417 A CN 109148417A
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- 239000004020 conductor Substances 0.000 claims abstract description 133
- 230000004888 barrier function Effects 0.000 claims abstract description 103
- 239000000758 substrate Substances 0.000 claims abstract description 77
- 235000012431 wafers Nutrition 0.000 claims description 106
- 239000000463 material Substances 0.000 claims description 20
- 238000004381 surface treatment Methods 0.000 claims description 13
- 238000005229 chemical vapour deposition Methods 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- 238000003860 storage Methods 0.000 claims description 8
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 238000009832 plasma treatment Methods 0.000 claims description 2
- 150000001336 alkenes Chemical class 0.000 claims 1
- 229910002804 graphite Inorganic materials 0.000 claims 1
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- 239000004575 stone Substances 0.000 claims 1
- 239000002184 metal Substances 0.000 description 19
- 229910052751 metal Inorganic materials 0.000 description 19
- 230000008569 process Effects 0.000 description 16
- 239000004065 semiconductor Substances 0.000 description 10
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 7
- 230000007547 defect Effects 0.000 description 7
- 229910021389 graphene Inorganic materials 0.000 description 7
- 239000007769 metal material Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
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- 239000012159 carrier gas Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000003851 corona treatment Methods 0.000 description 2
- 238000010790 dilution Methods 0.000 description 2
- 239000012895 dilution Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 238000012805 post-processing Methods 0.000 description 2
- 230000035484 reaction time Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
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- 239000011800 void material Substances 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of hybrid bonded method of wafer, comprising the following steps: provides the first wafer and the second wafer, first wafer has the first substrate of bonding to be mixed, and second wafer has the second substrate of bonding to be mixed；The first metallic conductor is formed on first substrate, forms the second metallic conductor on second substrate；Barrier layer is formed on the first bonding surface of first metallic conductor and/or the second bonding surface of second metallic conductor；It is bonded first wafer and the second wafer, so that first metallic conductor and second metallic conductor are bonded by the barrier layer, wherein the contact surface between the barrier layer and first bonding surface and/or second bonding surface is plane.
Description
Technical field
The invention mainly relates to field of semiconductor manufacture more particularly to the hybrid bonded structures and method of a kind of wafer.
Background technique
With the development of electronic industry, the function of chip becomes increasingly complex, and size is smaller and smaller, adapts to the new of the demand
Semiconductor technology continues to bring out, such as wafer-level packaging, 3D chip stack, 3D device, silicon-on-insulator wafer, these technologies
Development drive the development of wafer bond techniques.
Wafer bonding is the atom by wafer interface under the action of outside energy, passes through Van der Waals force, molecular force
Even atomic force makes the technology that wafer bonding is integrally formed.Hybrid bonded (such as simultaneously include insulator-insulator bonding, half
Conductor-bonding semiconductor, metal-metal bonding) it is a kind of more commonly used wafer bonding mode, it is widely used in 3D chip
In field, such as the bonding process of cmos image sensor, DRAM, 3D-NAND flash memory and logical device.
It is raised and lowered however as temperature during bonding process, thermal expansion and shrinkage, key can occur for metal volume
The metal (such as copper) for closing interface can occur to migrate and/or spread, while it is (such as thin to also result in metal inside intrisicn defect
The defect state generated in film deposition process) and/or interface flatization during generate various defect states occur migration and cluster,
Empty (Void) will be generated at bonded interface and bond wire, these cavities will will lead to leakage of current, not only seriously
Device reliability and stability are affected, and substantially reduces the service life of device.
Summary of the invention
The technical problem to be solved by the present invention is to the hybrid bonded structures and method of a kind of wafer, at bonded interface
Metal migration and/or diffusion, improve the stability, reliability and service life of device.
In order to solve the above technical problems, the present invention provides a kind of hybrid bonded methods of wafer, comprising the following steps: mention
For the first wafer and the second wafer, first wafer have bonding to be mixed the first substrate, second wafer have to
The second hybrid bonded substrate；The first metallic conductor is formed on first substrate, forms second on second substrate
Metallic conductor；In the first bonding surface of first metallic conductor and/or the second bonding surface of second metallic conductor
Upper formation barrier layer；It is bonded first wafer and the second wafer, so that first metallic conductor and second metal are led
Body is bonded by the barrier layer, wherein the barrier layer is bonded table with first bonding surface and/or described second
Contact surface between face is plane.
In one embodiment of this invention, in the first bonding surface of first metallic conductor and/or second gold medal
Belonging to the step of barrier layer is formed on the second bonding surface of conductor includes: planarization first bonding surface and/or described the
Two bonding surfaces；To after planarization first bonding surface and/or second bonding surface be surface-treated；?
The barrier layer is formed on first bonding surface and/or second bonding surface after surface treatment.
In one embodiment of this invention, the method for the surface treatment is thermal annealing or plasma treatment.
In one embodiment of this invention, first bonding surface and/or second key after the surface treatment
Closing the method that the barrier layer is formed on surface is chemical vapour deposition technique.
In one embodiment of this invention, the material of first metallic conductor and second metallic conductor is copper.
In one embodiment of this invention, the material on the barrier layer is graphene.
In one embodiment of this invention, the barrier layer with a thickness of 1-5nm.
In one embodiment of this invention, the area of first metallic conductor end is greater than second metallic conductor end
The area in portion, and barrier layer is formed in the region not contacted with the second metallic conductor end in the first metallic conductor end.
In one embodiment of this invention, barrier layer further includes between first substrate and first metallic conductor
Region formed barrier layer.
In one embodiment of this invention, barrier layer further includes between second substrate and second metallic conductor
Region formed barrier layer.
In one embodiment of this invention, first wafer is storage array chip, and second wafer is peripheral device
Part chip.
The present invention also provides a kind of hybrid bonded structures of wafer, comprising: the first wafer and the second wafer, described first is brilliant
Circle has the first substrate of bonding to be mixed, and second wafer has the second substrate of bonding to be mixed；First substrate
It is upper that there is the first metallic conductor, there is the second metallic conductor on second substrate；First bonding of first metallic conductor
There is barrier layer, first metallic conductor and described the on second bonding surface of surface and/or second metallic conductor
Two metallic conductors are bonded by the barrier layer；The wherein barrier layer and first bonding surface and/or described the
Contact surface between two bonding surfaces is plane.
In one embodiment of this invention, the material of first metallic conductor and second metallic conductor is copper.
In one embodiment of this invention, the material on the barrier layer is graphene.
In one embodiment of this invention, the barrier layer with a thickness of 1-5nm.
In one embodiment of this invention, the area of first metallic conductor end is greater than second metallic conductor end
The area in portion, and barrier layer is also formed into the region not contacted with the second metallic conductor end in first metallic conductor end
In.
In one embodiment of this invention, the barrier layer is also formed into first substrate and first metallic conductor
Between region.
In one embodiment of this invention, the barrier layer is also formed into second substrate and second metallic conductor
Between region.
In one embodiment of this invention, first wafer is storage array chip, and second wafer is peripheral device
Part chip.
The present invention also provides a kind of three-dimensional storage parts comprising the hybrid bonded structure of wafer as discussed.
Compared with prior art, the invention has the following advantages that the present invention provides a kind of hybrid bonded structures of wafer
And method, wafer include the metallic conductor for connection, the bonding surface of metallic conductor end face and/or is connect with surrounding dielectric matter
Barrier layer is formed in contacting surface, the contact surface between bonding surface and barrier layer is plane, due to the bonding of metallic conductor end face
It is formed with barrier layer on surface, can reduce the irregularity degree (such as recess and/or defect state outstanding) of contact surface, and stops
Intrametallic electromigration and/or the diffusion that metal is interior and metal is to dielectric medium, avoid the formation in cavity, improve the stabilization of device
Property, reliability and service life.
Detailed description of the invention
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates, in which:
Figure 1A -1D is a kind of schematic diagram of empty forming process.
Fig. 2 is the flow chart of a kind of hybrid bonded method of wafer according to an embodiment of the invention.
Fig. 3 A-3D is that the section of the example process of a kind of hybrid bonded method of wafer according to an embodiment of the invention shows
It is intended to.
Fig. 4 is the flow chart of the method according to an embodiment of the invention for forming barrier layer.
Fig. 5 A-5D is the section signal of the example process of the method according to an embodiment of the invention for forming barrier layer
Figure.
Fig. 6 A-6D is the schematic diagram of the hybrid bonded structure of wafer according to some embodiments of the invention.
Specific embodiment
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
It is different from other way described herein using other and implements, therefore the present invention is by the limit of following public specific embodiment
System.
As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one
The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.It is, in general, that term " includes " only prompts to wrap with "comprising"
Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or apparatus
The step of may also including other or element.
When describing the embodiments of the present invention, for purposes of illustration only, indicating that the sectional view of device architecture can disobey general proportion work
Partial enlargement, and the schematic diagram is example, should not limit the scope of protection of the invention herein.In addition, in practical system
It should include the three-dimensional space of length, width and depth in work.
For the convenience of description, herein may use such as " under ", " lower section ", " being lower than ", " following ", " top ", "upper"
Etc. spatial relationship word the relationships of an elements or features shown in the drawings and other elements or feature described.It will reason
Solve, these spatial relationship words be intended to encompass in use or device in operation, other than the direction described in attached drawing
Other directions.For example, being described as be in other elements or feature " below " or " under " if overturning the device in attached drawing
Or the direction of the element of " following " will be changed to " top " in the other elements or feature.Thus, illustrative word " under
Side " and " following " can include upper and lower both direction.Device may also have other directions (to be rotated by 90 ° or in its other party
To), therefore spatial relation description word used herein should be interpreted accordingly.In addition, it will also be understood that being referred to as when one layer at two layers
" between " when, it can be only layer between described two layers, or there may also be one or more intervenient layers.
Such as background technique introduction, hybrid bonded (such as simultaneously include insulator-insulator bonding, semiconductor-semiconductor key
Close, metal-metal bonding) it is a kind of more commonly used wafer bonding mode, it is widely used in 3D chip field, such as CMOS
In the bonding process of imaging sensor, DRAM, 3D-NAND flash memory and logical device.However as being raised and lowered for temperature, key
The metal (such as copper) for closing interface can occur to migrate and/or spread.The migration and/or diffusion of metal at bonded interface will
Cavity is generated at bonded interface and bond wire, these cavities will will lead to leakage of current, and not only seriously affect device
Reliability and stability, and substantially reduce the service life of device.
Figure 1A -1D is a kind of schematic diagram of empty forming process.Empty formation mechenism, is primarily threefold: (1) intrinsic
Defect state: during film (such as metal and/or dielectric medium) deposition, defect state can more or less be introduced.In addition, scheming
1A, before bonding process, wafer to be bonded needs to handle by surface planarisation, such as chemical machinery polishes (Chemical
Mechanical Polishing).Carry out during chemical machinery polishes, unavoidably flattened surface can introduce recess or
Defect state outstanding.(2) in addition, in Figure 1B, in bonding process, temperature is increased to bonding temperature (less than 500 DEG C) by room temperature, temperature
Degree increases the volume expansion for leading to metal 101 (such as copper).After Fig. 1 C, bonding process, wafer is cooled to room temperature, metal
101 shrink, and cavity 102 is caused to deteriorate (such as: quantity increases, and volume becomes larger).(3) further, in the mistake of heating cooling
Cheng Zhong, metallic atom can occur ELECTROMIGRATION PHENOMENON (EM), and can spread between metals and between metal and dielectric medium,
To generate empty (Void).In the electron microscope shown in Fig. 1 D, it can be seen that the generation in cavity 102.Cavity 102 will will lead to
Leakage of current has not only seriously affected device reliability and stability, and substantially reduces the service life of device.
Fig. 2 is the flow chart of a kind of hybrid bonded method of wafer according to an embodiment of the invention.Fig. 3 A-3D is according to this
Invent the diagrammatic cross-section of the example process of a kind of hybrid bonded method of wafer of an embodiment.Below with reference to shown in Fig. 2-3D
The hybrid bonded method of wafer of the present embodiment is described.
In step 202, the first wafer and the second wafer are provided.
Here, the first wafer and the second wafer are two wafers to be bonded.Each wafer undergoes a series of
Technique, to form device.The front of wafer is active face, thereon includes semiconductor devices.The back side of wafer is inactive face,
It is upper not include semiconductor devices usually.First wafer has the first substrate of bonding to be mixed, and the second wafer has key to be mixed
The second substrate closed.First substrate of bonding to be mixed and the second substrate to be mixed at least one be active face.First lining
The material of bottom and the second substrate can be silicon, silicon carbide etc..
Such as in figure 3 a, the first wafer 310 and the second wafer 320 are two wafers to be bonded.Each crystalline substance
Circle all undergoes series of process, to form device.First wafer 310 has the first substrate 311 of bonding to be mixed, and second is brilliant
Second substrate 321 of the circle 320 with bonding to be mixed.First substrate 311 of bonding to be mixed and the second substrate 321 to be mixed
At least one is active face.Such as the first substrate 311 of bonding to be mixed is active face or the second substrate to be mixed
321 be the first substrate 311 of active face or bonding to be mixed and the second substrate 321 to be mixed is all active face.First lining
The material of bottom 311 and the second substrate 321 can be silicon, silicon carbide etc..
In step 204, the first metallic conductor is formed on the first substrate, and the second metallic conductor is formed on the second substrate.
In this step, the first metallic conductor is formed on the first substrate, and the second metallic conductor is formed on the second substrate.
There is the first bonding surface on first metallic conductor, there is the second bonding surface on the second metallic conductor.Bonding surface refers to
Surface to be bonded on metallic conductor.First bonding surface and the second bonding surface can be plane.First bonding surface is
The method for forming the first metallic conductor on one substrate and forming the second metallic conductor on the second substrate can be shape on substrate
At groove, metal material then is filled to flute.The technique of filling metal material can be deposition.First metal material and second
The material of metal material can be copper.
Such as in figure 3b, the first metallic conductor 312 is formed on the first substrate 311, and is formed on the second substrate 312
Two metallic conductors 322.There is the first bonding surface 312a on first metallic conductor 312, have second on the second metallic conductor 322
Bonding surface 322a.First bonding surface 312a and the second bonding surface 322a is plane.311 form first on the first substrate
Metallic conductor 312 and the method that the second metallic conductor 322 is formed on the second substrate 312 can be and groove are formed on the substrate,
Then to trench fill metal material.The technique of filling metal material can be deposition.First metallic conductor 312 and the second metal
The material of conductor 322 can be copper.Show in Fig. 3 B includes 3 the first metallic conductors 312, the second substrate on the first substrate 311
Include 3 the second metallic conductors 322 on 322, however this and represent the number of actual metallic conductor on substrate.
In step 206, in the first bonding surface of the first metallic conductor and/or the second bonding surface of the second metallic conductor
Upper formation barrier layer.
In this step, in the first bonding surface of the first metallic conductor and/or the second bonding table of the second metallic conductor
Barrier layer is formed on face.Contact surface between barrier layer and the first bonding surface and/or the second bonding surface can be plane.?
It further include the region between the first substrate and the first metallic conductor and/or the second lining in some other embodiment of the invention
Region between bottom and the second metallic conductor forms barrier layer.Region between the first substrate and the first metallic conductor and/or
The method that region between second substrate and the second metallic conductor forms barrier layer can be the first deposition resistance in the groove of substrate
Then barrier forms the first metallic conductor and the second metallic conductor over the barrier layer.In some other embodiment of the invention,
When the area of first metallic conductor end is greater than the area of the second metallic conductor end, barrier layer is also formed in the first metallic conductor
In the region not contacted with the second metallic conductor end in end.The material on barrier layer can be graphene, be also possible to other
The material of selective growth.The thickness on barrier layer can be 1-5nm.The method for forming barrier layer can be chemical vapor deposition
(Chemical Vapor Deposition, CVP), such as low-pressure chemical vapor deposition (Low Pressure CVD, LPCVD),
Plasma enhanced chemical vapor deposition (Plasma Enhanced CVD, PECVD), high-density plasma chemical gas phase are heavy
Long-pending (High density Plasma CVD, HDPCVD), Metalorganic chemical vapor deposition (Metal-Organic CVD,
MOCVD)MOCVD.The specific steps for forming barrier layer will be explained below.
Such as in fig. 3 c, barrier layer 330 is formed on the second bonding surface 322a of the second metallic conductor 322.Resistance
Contact surface between barrier 330 and the second bonding surface 322a can be plane.It is appreciated that barrier layer 330 can also be formed
In on the first bonding surface 312a of the first metallic conductor 312, the first substrate 311 and the first metallic conductor can also be formed in
The region between region and/or the second substrate 321 and the second metallic conductor 322 between 312.In the first substrate 311 and first
Region between region and/or the second substrate 321 and the second metallic conductor 322 between metallic conductor 312 forms barrier layer 330
Method can be and first deposit barrier layer 330 in the groove of the first substrate 311 and the second substrate 321, then on barrier layer 330
The first metallic conductor 312 of upper formation and the second metallic conductor 322.It is also to be understood that the area of 312 end of the first metallic conductor is big
Area in 322 end of the second metallic conductor, barrier layer 330 be also formed in 312 end of the first metallic conductor not with the second gold medal
In the region for belonging to the contact of 322 end of conductor.The thickness on barrier layer 330 can be 1-5nm.The method for forming barrier layer 330 can be with
It is chemical vapor deposition, such as selective growth.The material on barrier layer 330 can be graphene, be also possible to other suitable choosings
The material and/or technique of selecting property growth.
In step 208, it is bonded the first wafer and the second wafer.
Here, the first wafer and the second wafer can be conventionally bonded.For example, be first aligned, then into
Row fitting.
For example, as shown in Figure 3 C, the first wafer 310 and the second wafer 320 are aligned.The mode of alignment for example can be with
It is marked by bonding.Then, as shown in Figure 3D, the first wafer 310 and the second wafer 320 are bonded.
In this bonding technology, the first wafer 310 can be both located above as Fig. 3 D, can also be with the second wafer
320 transpositions.
In addition, the first wafer 310 being bonded herein can be storage array chip, the second wafer 320 can be outer
Peripheral device chip.It is to be understood that the embodiment of the present invention is not limited to this application.
Flow chart has been used to be used to illustrate operation performed by method according to an embodiment of the present application herein.It should be understood that
, the operation of front not necessarily accurately carries out in sequence.On the contrary, various steps can be handled according to inverted order or simultaneously
Suddenly.Meanwhile or during other operations are added to these, or from these processes remove a certain step or number step operation.
Fig. 4 is the flow chart of the method according to an embodiment of the invention for forming barrier layer.Fig. 5 A-5D is according to the present invention
The diagrammatic cross-section of the example process of the method on the formation barrier layer of one embodiment.This reality is described below with reference to shown in Fig. 4-5D
The method for applying the formation barrier layer of example.For ease of description, this sentence on the second bonding surface formed barrier layer be example into
Row explanation.
In step 402, the first bonding surface and/or the second bonding surface are planarized.
In this step, the first bonding surface and/or the second bonding surface are planarized.Planarize the first bonding surface and/
Or second the method for bonding surface can be mechanochemistry and polish.After planarization process, the first bonding surface and/or
Two bonding surfaces are planes, and the height of the plane is lower than the edge of substrate.
In the semiconductor structure 500a shown in Fig. 5 A, after planarization process, bonding surface 520a is plane, and
And the height of plane 520a is lower than the top edge of substrate 510.
In step 404, to after planarization the first bonding surface and/or the second bonding surface be surface-treated.
In this step, to after planarization the first bonding surface and/or the second bonding surface be surface-treated, with
Conducive to the attachment on barrier layer.The method of surface treatment can be thermal annealing or corona treatment.By thermal annealing or plasma
After body processing, metal oxide can be formed on the first bonding surface and/or the second bonding surface.Metal oxide is removed
Later, the first bonding surface and/or the second bonding surface after surface treatment can be formed, convenient for the attachment on barrier layer.
In the semiconductor structure 500b shown in Fig. 5 B, after thermal annealing or corona treatment, bonding surface
520a is upper can to form metal oxide 530 (such as copper oxide).After metal oxide is removed, surface treatment can be formed
Bonding surface later, semiconductor structure 500c as shown in Figure 5 C, convenient for the attachment on barrier layer.
In step 406, barrier layer is formed on the first bonding surface and/or the second bonding surface after the surface treatment.
In this step, barrier layer is formed on the first bonding surface and/or the second bonding surface after the surface treatment.
The method that barrier layer is formed on the first bonding surface and/or the second bonding surface after the surface treatment can be chemical gaseous phase
Deposition.For example, carrying out chemical vapor deposition using graphene predecessor and dilution/carrier gas.By controlling chemical vapor deposition
The thickness on the barrier layer of the long-pending adjustable formation of number reaction time.It is formed after barrier layer, can also include some post-processings
Step, such as chemical machinery are polished with recess etch etc., to remove the barrier material on substrate.
In the semiconductor structure 500d shown in Fig. 5 D, after surface treatment, barrier layer is formed on bonding surface
540.The method that barrier layer 540 is formed on bonding surface can be chemical vapor deposition.For example, using graphene predecessor and
Dilution/carrier gas carries out chemical vapor deposition.By the number reaction time adjustable formation for controlling chemical vapor deposition
The thickness on barrier layer 540.Formed barrier layer 540 after, can also include some post-processing steps, such as chemical machinery polish and
Recess etch etc., to remove the barrier material on substrate 510.
Fig. 6 A-6D is the schematic diagram of the hybrid bonded structure of wafer according to some embodiments of the invention.As shown in Figure 6A, brilliant
Round hybrid bonded structure includes the first wafer 610 and the second wafer 620.First wafer 610 has the first of bonding to be mixed
Substrate 611.Second wafer 620 has the second substrate 621 of bonding to be mixed.611 have the first metallic conductor on first substrate
612.There is the second metallic conductor 622 on second substrate 621.Have on first bonding surface 612a of the first metallic conductor 612
Barrier layer 630.First metallic conductor 612 and the second metallic conductor 622 are bonded by barrier layer 630.Barrier layer 630 and
Contact surface between one bonding surface 612a is plane.
The position that barrier layer 630 is formed can have different variations.Barrier layer 630 can be formed in the first bonding surface
On 612a and the second bonding surface 622a, as shown in Figure 6B.Barrier layer 630 be additionally formed in the first bonding surface 612a and
Region between first substrate 611 and the first metallic conductor 612, as shown in Figure 6 C；Or be formed in the first bonding surface 612a and
Region between second bonding surface 622a and the first substrate 611 and the first metallic conductor 612, as shown in Figure 6 D.In this hair
In bright embodiment, the area of the first metallic conductor end can be identical or different with the area of the second metallic conductor end.?
When the area difference of the area of the first metallic conductor end and the second metallic conductor end, led as Fig. 6 A-6D shows the first metal
The area of 612 end of body is greater than the area of 622 end of the second metallic conductor, and barrier layer 630 is also formed into the first metallic conductor 612
In the region not contacted with 622 end of the second metallic conductor in end.
In one embodiment of this invention, the material of the first metallic conductor 612 and the second metallic conductor 622 can be copper.
In one embodiment of this invention, the material on barrier layer 630 can be graphene.In one embodiment of this invention, barrier layer
630 thickness can be 1-5nm.In one embodiment of this invention, the first wafer 610 can be storage array chip, second
Wafer 620 can be peripheral components chip.
The other details of the present embodiment can refer to production method above, not reinflated herein.
The present invention provides the hybrid bonded structure and method of a kind of wafer, wafer includes the metallic conductor for connection,
Barrier layer is formed on the bonding surface of metallic conductor end face, the contact surface between bonding surface and barrier layer is plane, due to
It is formed with barrier layer on the bonding surface of metallic conductor end face, the shape in cavity can be avoided with the migration and/or diffusion of barrier metal
At improving the service life of device.
Although the present invention is described with reference to current specific embodiment, those of ordinary skill in the art
It should be appreciated that above embodiment is intended merely to illustrate the present invention, can also make in the case where no disengaging spirit of that invention
Various equivalent change or replacement out, therefore, as long as to the variation of above-described embodiment, change in spirit of the invention
Type will all be fallen in the range of following claims.
Claims (20)
1. a kind of hybrid bonded method of wafer, comprising the following steps:
The first wafer and the second wafer are provided, first wafer has the first substrate of bonding to be mixed, second wafer
The second substrate with bonding to be mixed；
The first metallic conductor is formed on first substrate, forms the second metallic conductor on second substrate；
It is formed on the first bonding surface of first metallic conductor and/or the second bonding surface of second metallic conductor
Barrier layer；
It is bonded first wafer and the second wafer, so that first metallic conductor and second metallic conductor are described in
Barrier layer is bonded, wherein connecing between the barrier layer and first bonding surface and/or second bonding surface
Contacting surface is plane.
2. the hybrid bonded method of wafer according to claim 1, which is characterized in that the of first metallic conductor
The step of formation barrier layer, includes: on second bonding surface of one bonding surface and/or second metallic conductor
Planarize first bonding surface and/or second bonding surface；
To after planarization first bonding surface and/or second bonding surface be surface-treated；
The barrier layer is formed on first bonding surface and/or second bonding surface after the surface treatment.
3. the hybrid bonded method of wafer according to claim 2, which is characterized in that the method for the surface treatment is heat
Annealing or plasma treatment.
4. the hybrid bonded method of wafer according to claim 2, which is characterized in that after the surface treatment described
The method that the barrier layer is formed on one bonding surface and/or second bonding surface is chemical vapour deposition technique.
5. the hybrid bonded method of wafer according to claim 1, which is characterized in that first metallic conductor and described
The material of second metallic conductor is copper.
6. the hybrid bonded method of wafer according to claim 1, which is characterized in that the material on the barrier layer is graphite
Alkene.
7. the hybrid bonded method of wafer according to claim 1, which is characterized in that the barrier layer with a thickness of 1-
5nm。
8. the hybrid bonded method of wafer according to claim 1, which is characterized in that first metallic conductor end
Area be greater than second metallic conductor end area, and in the first metallic conductor end not with the second metallic conductor end
Barrier layer is formed in the region of contact.
9. the hybrid bonded method of wafer according to claim 1 or 8, which is characterized in that barrier layer further includes described
Region between first substrate and first metallic conductor forms barrier layer.
10. the hybrid bonded method of wafer according to claim 9, which is characterized in that barrier layer further includes described
Region between two substrates and second metallic conductor forms barrier layer.
11. the hybrid bonded method of wafer according to claim 1, which is characterized in that first wafer is storage battle array
Column chip, second wafer are peripheral components chip.
12. a kind of hybrid bonded structure of wafer, comprising:
First wafer and the second wafer, first wafer have the first substrate of bonding to be mixed, and second wafer has
Second substrate of bonding to be mixed；
There is the first metallic conductor on first substrate, there is the second metallic conductor on second substrate；
There is resistance on second bonding surface of the first bonding surface of first metallic conductor and/or second metallic conductor
Barrier, first metallic conductor and second metallic conductor are bonded by the barrier layer；The wherein barrier layer
Contact surface between first bonding surface and/or second bonding surface is plane.
13. the hybrid bonded structure of wafer according to claim 12, which is characterized in that first metallic conductor and institute
The material for stating the second metallic conductor is copper.
14. the hybrid bonded structure of wafer according to claim 12, which is characterized in that the material on the barrier layer is stone
Black alkene.
15. the hybrid bonded structure of wafer according to claim 12, which is characterized in that the barrier layer with a thickness of 1-
5nm。
16. the hybrid bonded structure of wafer according to claim 12, which is characterized in that first metallic conductor end
Area be greater than the area of second metallic conductor end, and barrier layer is also formed into first metallic conductor end not
In the region contacted with the second metallic conductor end.
17. the hybrid bonded structure of wafer described in 2 or 16 according to claim 1, which is characterized in that the barrier layer is also formed
Region between first substrate and first metallic conductor.
18. the hybrid bonded structure of wafer according to claim 17, which is characterized in that the barrier layer is also formed into institute
State the region between the second substrate and second metallic conductor.
19. the hybrid bonded structure of wafer according to claim 12, which is characterized in that first wafer is storage battle array
Column chip, second wafer are peripheral components chip.
20. a kind of three-dimensional storage part comprising such as the hybrid bonded structure of the described in any item wafers of claim 12-19.
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