CN109147835B - Power supply system and semiconductor package assembly - Google Patents
Power supply system and semiconductor package assembly Download PDFInfo
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- CN109147835B CN109147835B CN201811132440.7A CN201811132440A CN109147835B CN 109147835 B CN109147835 B CN 109147835B CN 201811132440 A CN201811132440 A CN 201811132440A CN 109147835 B CN109147835 B CN 109147835B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 130
- 239000000758 substrate Substances 0.000 claims description 33
- 238000004806 packaging method and process Methods 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
Embodiments of the present disclosure provide a power supply system and a semiconductor package assembly. The power supply system includes: an internal voltage generating circuit for generating at least one internal voltage; wherein the at least one internal voltage is for being provided to the at least one semiconductor chip through the power chip interconnect structure.
Description
Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly, to a power supply system and a semiconductor package assembly.
Background
The advent of mobile consumer electronics devices (e.g., cellular telephones, notebook computers, personal digital assistants, etc.) has increased the need for compact high-performance storage. In many respects, modern developments in semiconductor memory devices can be seen as a process of increasing the maximum number of data bits at a specified operating speed using the smallest possible device. In this context, the term "smallest" generally refers to the smallest area occupied by a memory device in a "lateral" X/Y plane (e.g., a plane defined by the major surface of a printed circuit board or a template block). In general, the limitations of the allowable lateral area occupied by a storage device inspires the storage device designer to vertically integrate the data storage capacity of its device.
It should be noted that the information of the present invention in the above background section is only for enhancing understanding of the background of the present disclosure, and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.
Disclosure of Invention
According to an invention of the present invention, there is provided a power supply system including: an internal voltage generating circuit for generating at least one internal voltage; wherein the at least one internal voltage is for being provided to the at least one semiconductor chip through the power chip interconnect structure.
In one exemplary embodiment of the present disclosure, the internal voltage generating circuit includes: at least one voltage regulator for generating the at least one internal voltage.
In one exemplary embodiment of the present disclosure, the at least one voltage regulator includes a first charge pump circuit, a second charge pump circuit, a third charge pump circuit, a first low dropout linear regulator, a second low dropout linear regulator, and a third low dropout linear regulator; the first to third charge pump circuits are used for outputting a first internal voltage, a second internal voltage and a third internal voltage according to an external voltage respectively; the first to third low dropout linear regulators are configured to output a fourth internal voltage, a fifth internal voltage, and a sixth internal voltage according to the external voltage, respectively; wherein the first internal voltage is greater than the external voltage, and the second internal voltage and the third internal voltage are both opposite in polarity to the external voltage; the fourth to sixth internal voltages are each equal to or less than the external voltage.
In one exemplary embodiment of the present disclosure, the at least one voltage regulator includes a first low dropout linear regulator, a first charge pump circuit, a second low dropout linear regulator, a third low dropout linear regulator, and a fourth low dropout linear regulator; the first to fourth low dropout linear regulators are used for outputting a first internal voltage, a fourth internal voltage, a fifth internal voltage and a sixth internal voltage according to external voltages respectively; the first to second charge pump circuits are respectively used for outputting a second internal voltage and a third internal voltage according to the external voltage; wherein the first internal voltage, the fourth to sixth internal voltages are all less than or equal to the external voltage; the second internal voltage and the third internal voltage are both opposite in polarity to the external voltage.
In one exemplary embodiment of the present disclosure, the power supply system further includes a reference voltage generating circuit for generating a reference voltage; and each voltage regulator is used for outputting the first internal voltage, the second internal voltage, the third internal voltage, the fourth internal voltage, the fifth internal voltage and the sixth internal voltage according to the external voltage, the reference voltage and a power supply enabling signal.
According to one aspect of the present disclosure, there is provided a semiconductor package assembly including: packaging a substrate; the power supply system according to any one of the above embodiments, wherein the power supply system is disposed on the package substrate; at least one semiconductor chip.
In one exemplary embodiment of the present disclosure, the at least one semiconductor chip includes a plurality of semiconductor chips, each of the plurality of semiconductor chips having the same electrical function.
In one exemplary embodiment of the present disclosure, the semiconductor chip is a memory chip.
In one exemplary embodiment of the present disclosure, the semiconductor chip is a DRAM chip.
In one exemplary embodiment of the present disclosure, the plurality of semiconductor chips are vertically stacked in sequence on the power supply system.
In one exemplary embodiment of the present disclosure, the power chip interconnect structure includes a through silicon via.
In one exemplary embodiment of the present disclosure, the plurality of semiconductor chips are respectively disposed directly on the package substrate, and the power supply system is disposed directly on the package substrate.
In one exemplary embodiment of the present disclosure, the power chip interconnect structure includes a metal wire.
In an exemplary embodiment of the present disclosure, the plurality of semiconductor chips are vertically stacked in sequence on the package substrate, and the power supply system is directly disposed on the package substrate.
In one exemplary embodiment of the present disclosure, the diameter of the power chip interconnect structure is related to the number of the at least one semiconductor chip.
In an exemplary embodiment of the present disclosure, further comprising: and the signal chip interconnection structure is used for inputting external control signals to each semiconductor chip and/or inputting data signals to or outputting data signals to each semiconductor chip through the packaging substrate.
In one exemplary embodiment of the present disclosure, each semiconductor chip and the power supply system share a ground power supply provided by the package substrate.
In one exemplary embodiment of the present disclosure, the package size of the power supply system is equal to or smaller than the package size of each semiconductor chip.
Drawings
Various objects, features and advantages of the present disclosure will become more apparent from the following detailed description of the preferred embodiments of the disclosure, when taken in conjunction with the accompanying drawings. The drawings are merely exemplary illustrations of the present disclosure and are not necessarily drawn to scale. In the drawings, like reference numerals refer to the same or similar parts throughout. Wherein:
fig. 1 is a schematic view of a semiconductor package assembly according to the related art;
FIG. 2 is a schematic diagram of another semiconductor package assembly according to the related art;
fig. 3 is a schematic structural view of a semiconductor chip in the related art;
fig. 4 is a schematic view showing a structure of a semiconductor package assembly according to an embodiment of the present disclosure;
fig. 5 is a schematic view showing the structure of another semiconductor package assembly according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram illustrating a configuration of a power supply system according to an embodiment of the present disclosure;
FIG. 7 is a timing diagram based on the power system shown in FIG. 6;
FIG. 8 is a circuit diagram of a Vp charge pump circuit based on the power supply system of FIG. 6;
FIG. 9 is a timing diagram of a charge pump circuit based on the Vp shown in FIG. 8;
FIG. 10 is a circuit diagram generated based on the Vclk of FIG. 8;
FIG. 11 is a circuit diagram generated based on the Vpclken of FIG. 10;
FIG. 12 is a circuit diagram of a Vbb charge pump circuit based on the power supply system shown in FIG. 6;
FIG. 13 is a circuit diagram of a Vnwl charge pump circuit based on the power supply system shown in FIG. 6;
FIG. 14 is a circuit diagram of a Vcore low dropout linear regulator based on the power supply system shown in FIG. 6;
fig. 15 is a circuit diagram of a Veq low dropout linear regulator based on the power supply system shown in fig. 6.
Detailed Description
Exemplary embodiments that embody features and advantages of the present disclosure are described in detail in the following description. It will be understood that the present disclosure is capable of various modifications in the various embodiments, all without departing from the scope of the present disclosure, and that the description and drawings are intended to be illustrative in nature and not to be limiting of the present disclosure.
In the following description of various exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration various exemplary structures, systems, and steps in which aspects of the present disclosure may be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure.
Fig. 1 is a schematic diagram of a semiconductor package assembly in the related art.
As shown in fig. 1, one way in the related art is to vertically stack a plurality of semiconductor chips (e.g., semiconductor memory chips a-D in the drawing) in a vertical Z-plane with respect to a lateral X/Y plane, e.g., a chip on top of a B chip, B chip on top of a C chip, and C chip on top of a D chip.
Stacked semiconductor package assemblies are one type of three-dimensional (3D) integrated circuit. That is, from the perspective of other systems (e.g., a memory controller), the 3D memory device functions as an overall memory device. Data write and data read operations are handled by 3D memory devices to store write data or retrieve read data in a manner that is generally applicable to non-stacked (i.e., single semiconductor chip) memory devices. However, 3D memory devices are capable of storing and providing a greater amount of data per unit of lateral surface area than non-stacked memory devices.
As shown in fig. 1, a semiconductor package assembly 100 having a plurality of stacked semiconductor chips includes a package substrate 101 and semiconductor chips a-D, which are stacked in this order on the package substrate 101.
Each semiconductor chip has a peripheral region on which an electrode pad 102 is disposed. Electrode pads 102 of semiconductor chips a-D are interconnected with electrode pads (not shown) on package substrate 101 by wire-bond 103.
In the semiconductor package aggregate 100 shown in fig. 1, the width of each electrode pad 102 should be about 100 μm or more in order to achieve reliable connection between the bonding wire 103 and the electrode pad 102. In addition, the pitch of the electrode pads 102 cannot be too small, and thus the number of electrode pads 102 provided on the semiconductor chip is limited. At the same time, the bond wires 103 increase the total lateral area occupied by the stacked devices and typically require an interposer, such as RDL (Re-distribution Layer, redistribution layer) 104, between adjacent semiconductor chips in the stack.
Here, if the semiconductor chips a to D are made into DRAM (Dynamic Random Access Memory ) chips, electrode pads 102 should be provided for a larger number of signal terminals, such as address signals, command signals, and data signal line terminals, in addition to the power supply terminals (power supply terminals) and ground terminals. Therefore, the number of electrode pads 102 allocated to the power supply terminal and the ground terminal is limited.
Fig. 2 is a schematic diagram of another semiconductor package assembly according to the related art.
Three-dimensional integrated circuits based on through-silicon vias (Through Silicon Via, TSVs) integrate multiple layers of chips vertically stacked through the through-silicon vias to enable inter-chip communication, and therefore do not require additional lateral area other than that defined by the periphery of the largest chip in the stack. In addition, TSVs shorten the overall length of certain signal paths through the stack of devices, thus helping to speed up operation. Thus, through the use of TSVs or similar stacked fabrication processes, memory (and other) devices implemented using multiple vertically stacked chips are able to store and provide large amounts of data using a single integrated circuit having a relatively small lateral surface area footprint.
As shown in fig. 2, the semiconductor package assembly 200 has a plurality of layers of semiconductor chips a-D having the same size therebetween. A plurality of semiconductor chips a-D having the same size are stacked on each other through a plurality of TSVs 202 and electrode pads 203, thereby achieving electrical connection between the chips. This technique can reduce the size of the semiconductor package aggregate since there is no need to provide bonding pads for the bonding wires.
The semiconductor package assembly 200 of fig. 2 may be a RAM device structure. Specifically, the semiconductor package assembly 200 includes one package substrate 201 and 4 DRAM chips A-D sequentially stacked on the package substrate 201. Within the peripheral region of the DRAM chip and the package substrate 201, a plurality of TSVs 202 pass through each semiconductor chip from the top DRAM chip to the bottom DRAM chip along the Z-direction.
Fig. 3 is a schematic structural view of a semiconductor chip in the related art.
Fig. 3 is a schematic diagram of a single layer DRAM chip in the semiconductor package assembly 200 shown in fig. 2. The DRAM chips A-D in FIG. 2 have the same ports or PINs, such as BA0-2 (Bank Sel), A0-15 (Address signals), RAS/, CAS/, WE/(Command control signals), CLK/(clock signals), CS/, RESET/(RESET signals), DQ [0:15] (data signals), and VDD, VDDQ, VSS, VSSQ, VPP external power signals, etc., and these ports or PINs are connected to TSVs, metal wires (metal wires) or RDLs, and to package PINs (packages, PINs).
Wherein Bank Sel, address, command, CLK, RESET/these control signals or address signals are each electrically connected through the DRAM chips a-D of each layer. VDD, VDDQ, VSS, VSSQ, VPP these external power signals are each electrically connected through the DRAM chips A-D of each tier.
The DRAM memory cell array 301 includes a large number of individual memory cells arranged in association with a matrix of row and column signal lines. Each memory cell is capable of storing write data in response to a write command and providing read data in response to a read command received from an external device (not shown), such as a memory controller or processor. The read/write command results in the generation of certain control signals (e.g., row address, column address, enable signals, etc.) that, along with certain control voltages, are applied to the array of memory cells 301 through associated peripheral devices (e.g., row decoder 302 and column decoder 303).
During a write operation, write data (i.e., data intended to be stored in the memory cell array 301) is transferred from external circuitry (e.g., external memory, external input devices, processors, memory controllers, memory switches, etc.) to the data registers. Once stored in the data register, the write data may be written to the memory cell array 301 by conventional structures and techniques, which may include, for example, sense amplifier and write driver circuitry.
During a read operation, the applied control voltages and the control signal outputs of row decoder 302 and column decoder 303 generally cooperate to identify and select one or more memory cells in memory cell array 301 and facilitate providing a signal indicative of the value of the data stored in the memory cells. The resulting "read data" is typically passed through a read sense amplifier for storage in a data register. The read data stored in the data register may then be provided to external circuitry under the control of the read control circuitry.
As shown in fig. 3, each layer of DRAM chips in fig. 2 includes all the DRAM operation related logic blocks, such as write/read control logic, refresh control, and internal power supplies (e.g., vp, vbb, vnwl, vcore, veq, vplt, etc.), which need to be regulated by the corresponding charge pump circuits or voltage regulators to obtain the correct voltage levels.
Each layer of DRAM chips in the semiconductor package assembly 200 shown in fig. 2 includes a Charge pump circuit and a voltage regulator (voltage regulator), respectively, that is, the DRAM chips a-D have the same internal Power supply circuit, since the DRAM chips need to use a nano-scale high-level process, whereas the Power chips (Power ICs) generally only need to use a micro-scale low-level process, which is 1000 times different from the Power chips, if the Power chips are integrated in the DRAM chips, the efficiency of the Power chips is reduced, for example, from a normal 90% efficiency to about 60% efficiency because the DRAM chip process is not suitable for the Power chips. In addition, integrating the power chip into the DRAM chip can occupy die area, increasing the cost of the DRAM chip. Meanwhile, the DRAM chip has expensive manufacturing process and the power supply has cheap manufacturing process.
Fig. 4 is a schematic view showing a structure of a semiconductor package assembly according to an embodiment of the present disclosure.
As shown in fig. 4, an embodiment of the present invention provides a semiconductor package assembly 400, and the semiconductor package assembly 400 may include: a package substrate 401; a power supply system 402, wherein the power supply system 402 may be disposed on the package substrate 401; at least one semiconductor chip, here, four semiconductor chips a-D are exemplified, but the present disclosure is not limited thereto, and may be adjusted accordingly according to specific requirements.
In an exemplary embodiment, the at least one semiconductor chip may include a plurality of semiconductor chips, each of the plurality of semiconductor chips having the same electrical function.
In an exemplary embodiment, the semiconductor chip may be a memory chip.
In an exemplary embodiment, the semiconductor chip may be a DRAM chip. The present disclosure is not limited in this regard and the semiconductor chip may be any type of chip.
In the embodiment shown in fig. 4, the plurality of semiconductor chips may be vertically stacked in sequence on the power supply system 402. For example, DRAM chip A is vertically stacked on DRAM chip B, DRAM chip B is vertically stacked on DRAM chip C, and DRAM chip C is vertically stacked on DRAM chip D.
In the embodiment shown in fig. 4, the power supply system 402 may input each internal voltage output from the power supply system as a power supply chip interconnection structure through the TSV 403 to each semiconductor chip.
It should be noted that, although fig. 4 only shows an embodiment in which a plurality of semiconductor chips are vertically stacked in sequence on the power supply system, in other embodiments, the plurality of semiconductor chips may be directly disposed on the package substrate 401, that is, the semiconductor chips are disposed adjacent to each other in a lateral plane of the package substrate 401 (side-by-side arrangement), and the power supply system is also directly disposed on the package substrate 401. In other embodiments, the plurality of semiconductor chips may be vertically stacked on the package substrate 401 in turn, and the power supply system may also be directly disposed on the package substrate 401.
In an arrangement in which the individual semiconductor chips are arranged adjacent to each other in the lateral plane of the package substrate 401, the power supply system 402 may input the individual internal voltages output therefrom into the individual semiconductor chips, respectively, through the metal wires as a power chip interconnection structure.
Fig. 5 is a schematic view illustrating a structure of another semiconductor package assembly according to an embodiment of the present disclosure.
As shown in fig. 5, at least one internal voltage output from the power supply system 402 is input to each layer of DRAM chips a-D through corresponding TSVs 403, respectively. Three arrows are shown in fig. 5 for illustration, and not for limiting the amount of internal voltage output by the power supply system 402.
In an exemplary embodiment, a diameter of the power chip interconnect structure is related to the number of the at least one semiconductor chip. For example, the larger the number of stacked semiconductor chips on the power supply system 402, the larger the diameter of the corresponding TSV 403, because the larger the voltage drop that occurs when a signal is transmitted to an upper semiconductor chip through the TSV 403, at this time, the voltage drop can be reduced by increasing the diameter of the TSV 403 or the number of TSVs 403 connected in parallel, so that the values of the same internal voltage received by the semiconductor chips of the respective layers are approximately equal.
In the embodiment shown in fig. 5, each TSV 403 has a diameter of, for example, about 20 μm and is arranged at a pitch of about 50 μm, which is sufficient to prevent a short circuit failure between adjacent TSVs. However, with the possible development of TSV fabrication techniques, these diameters and pitches may be reduced.
With continued reference to fig. 5, the semiconductor package assembly may further include: a signal chip interconnection structure 404, wherein the signal chip interconnection structure 404 may be used to input external control signals (e.g., signals such as Address, command) to each semiconductor chip and/or data signals (e.g., DQ [0-15 ]) to or from each semiconductor chip through the package substrate 401. In an embodiment of the present invention, TSVs may also be used for the signal chip interconnection structure 404.
In the embodiment shown in fig. 5, each of the semiconductor chips a-D and the power supply system 402 may share a ground power supply (not shown) provided by the package substrate 401.
In an exemplary embodiment, the package size of the power supply system may be equal to or smaller than the package size of each semiconductor chip.
For example, in the embodiment shown in fig. 4 and 5, the package size of the power supply system 402 is smaller than the package size of each semiconductor chip a-D.
Fig. 6 is a schematic diagram illustrating a structure of a power supply system according to an embodiment of the present disclosure.
As shown in fig. 6, an embodiment of the present invention provides a power supply system 600, and the power supply system 600 may include: an internal voltage generation circuit 610, the internal voltage generation circuit 610 being operable to generate at least one internal voltage; wherein the at least one internal voltage is used to be supplied to the at least one semiconductor chip (e.g., the DRAM chip in the above-described embodiment, but the present invention is not limited thereto) through a power chip interconnect structure (e.g., TSV or wire-bond).
In an exemplary embodiment, the internal voltage generation circuit 610 may include: at least one voltage regulator for generating the at least one internal voltage.
In an exemplary embodiment, the at least one voltage regulator may include a first charge pump circuit, a second charge pump circuit, a third charge pump circuit, a first low dropout linear regulator, a second low dropout linear regulator, and a third low dropout linear regulator; the first to third charge pump circuits are used for outputting a first internal voltage, a second internal voltage and a third internal voltage according to an external voltage respectively; the first to third low dropout linear regulators are configured to output a fourth internal voltage, a fifth internal voltage, and a sixth internal voltage according to the external voltage, respectively; wherein the first internal voltage is greater than the external voltage, and the second internal voltage and the third internal voltage are both opposite in polarity to the external voltage; the fourth to sixth internal voltages are each equal to or less than the external voltage.
In the disclosed embodiments, a low dropout linear regulator (Low Dropout Regulator, LDO) uses a transistor or field effect transistor (Field Effect Transistor, FET) operating in its linear region to subtract excess voltage from the applied input voltage, resulting in a regulated output voltage. The LDO linear voltage stabilizer has the outstanding advantages of low cost, low noise and small quiescent current. It requires few external components and typically only one or two bypass capacitors. If the input voltage and the output voltage are very close, the high efficiency can be achieved by selecting the LDO, the input current of the LDO is basically equal to the output current, and if the voltage drop is too large, the energy consumption on the LDO is too large, and the efficiency is not high. In other embodiments, a DC-DC converter may be used instead of the LDO in the embodiments of the present disclosure, as the case may be.
In the embodiment shown in fig. 6, taking the semiconductor chip as an example of a DRAM chip, and assuming that each layer of DRAM chip requires Vp, vbb, vnwl, vcore, vplt, veq internal voltages, the at least one voltage regulator may include a first charge pump circuit 611, a second charge pump circuit 612, a third charge pump circuit 613, a first low dropout linear regulator 614, a second low dropout linear regulator 615, and a third low dropout linear regulator 616. The first charge pump circuit 611 may be configured to output the first internal voltage Vp according to the external voltage Vext. The second charge pump circuit 612 may be configured to output the second internal voltage Vbb according to the external voltage Vext. The third charge pump circuit 613 may be configured to output the third internal voltage Vnwl according to the external voltage Vext. The first low dropout linear regulator 614 may output the fourth internal voltage Vcore according to the external voltage Vext. The second low dropout linear regulator 615 may be configured to output the fifth internal voltage Vplt according to the external voltage Vext. The third low dropout linear regulator 616 may be configured to output the sixth internal voltage Veq according to the external voltage Vext.
In the embodiment of the present invention, the first internal voltage Vp is greater than the external voltage Vext, the second internal voltage Vbb and the third internal voltage Vnwl are opposite to the external voltage Vext, for example, vext=1.2v, vp=3.0v, vbb= -0.5V, vnwl= -0.3V, and the above voltage values are only used for illustration, and the present disclosure is not limited thereto.
When the polarity of the input voltage is opposite to that of the output voltage, the inverter in the corresponding charge pump may convert the input positive voltage into the output negative voltage.
In the embodiment of the present invention, the fourth internal voltage Vcore, the fifth internal voltage Vplt, and the sixth internal voltage Veq are all less than or equal to the external voltage Vext, for example, vext=1.2v, vcore=1.0v, and vplt=veq=0.5v, but the disclosure is not limited thereto.
In an exemplary embodiment, the at least one voltage regulator includes a first low dropout linear regulator, a first charge pump circuit, a second low dropout linear regulator, a third low dropout linear regulator, and a fourth low dropout linear regulator; the first to fourth low dropout linear regulators are used for outputting a first internal voltage, a fourth internal voltage, a fifth internal voltage and a sixth internal voltage according to external voltages respectively; the first to second charge pump circuits are respectively used for outputting a second internal voltage and a third internal voltage according to the external voltage; wherein the first internal voltage, the fourth to sixth internal voltages are all less than or equal to the external voltage; the second internal voltage and the third internal voltage are both opposite in polarity to the external voltage.
Also taking fig. 6 as an example, assuming that each layer of semiconductor chips requires Vp, vbb, vnwl, vcore, vplt, veq internal voltages, the at least one voltage regulator may include a first low dropout linear regulator 611, a first charge pump circuit 612, a second charge pump circuit 613, a second low dropout linear regulator 614, a third low dropout linear regulator 615 and a fourth low dropout linear regulator 616. The first low dropout linear regulator 611 may be configured to output the first internal voltage Vp according to the external voltage Vext. The first charge pump circuit 612 may be configured to output the second internal voltage Vbb according to the external voltage Vext. The second charge pump circuit 613 may be configured to output the third internal voltage Vnwl according to the external voltage Vext. The second low dropout linear regulator 614 may output the fourth internal voltage Vcore according to the external voltage Vext. The third low dropout linear regulator 615 may be configured to output the fifth internal voltage Vplt according to the external voltage Vext. The fourth low dropout linear regulator 616 may be configured to output the sixth internal voltage Veq according to the external voltage Vext.
In the embodiment of the disclosure, the first internal voltage Vp, the fourth internal voltage Vcore, the fifth internal voltage Vplt, and the sixth internal voltage Veq may be equal to or less than the external voltage Vext, for example, vext >3.3V, vp=3.0v, vcore=1.0v, vplt=veq=0.5v; the second and third internal voltages Vbb and Vnwl are both opposite in polarity to the external voltage Vext, e.g., vext >3.3V, vbb= -0.5V, vnwl= -0.3V.
With continued reference to fig. 6, the power supply system 600 may further include a reference voltage generation circuit 620, and the reference voltage generation circuit 620 may be configured to generate a reference voltage Vref.
In the embodiment shown in fig. 6, each voltage regulator may be configured to output the first internal voltage Vp, the second internal voltage Vbb, the third internal voltage Vnwl, the fourth internal voltage Vcore, the fifth internal voltage Vplt, and the sixth internal voltage Veq according to the external voltage Vext, the reference voltage Vref, and the power enable signal EN, respectively.
In the embodiment shown in fig. 6, the semiconductor package assembly including the power supply system 600 may further include a signal chip interconnection structure 700, wherein the signal chip interconnection structure 700 may be used to input external control signals (e.g., external power supply VDD/VDDQ, VSS/VSSQ, address signals Address, bank Sel, control signals Command, clock signals CLK or/CLK, etc.) to each semiconductor chip and/or input or output data signals (e.g., DQ [0-15 ]) to each semiconductor chip through a package substrate (not shown) of the semiconductor package assembly. In the embodiment of the present invention, the signal chip interconnection structure 700 may also use TSVs.
It should be noted that, in the embodiment shown in fig. 6, the semiconductor chips in the semiconductor package assembly are taken as DRAM chips as an example, and in other embodiments, if the semiconductor chips in the semiconductor package assembly are other types of chips, the number and types of the internal voltages generated by the corresponding internal voltage generating circuits may also be changed accordingly, and similarly, the external control signals and/or the data signals provided by the signal chip interconnection structures may also be changed accordingly.
Fig. 7 is a timing diagram based on the power supply system shown in fig. 6.
As shown in fig. 7, when the external voltage Vext is at a high level (here, it is assumed that Vext is VDD for example), the power supply enable signal EN continues to wait for the arrival of the high level, and when both VDD and EN are at the high level, the internal voltage generation circuit starts to operate, and after a certain delay, the internal voltage generation circuit outputs the first to sixth internal voltages Vp, vbb, vnwl, vcore, vplt, veq, respectively.
According to the power supply system and the semiconductor packaging assembly, the unified power supply system simultaneously provides the internal voltage required by each semiconductor chip for the plurality of semiconductor chips in the semiconductor packaging assembly, and the power supply system does not need to be integrated in any semiconductor chip, so that the semiconductor chips can be manufactured by adopting a high-order process, and the power supply system is manufactured by adopting a low-order process, and on one hand, the efficiency of the power supply system is improved due to the fact that the power supply system is manufactured in a matched mode; on the other hand, the power supply system does not occupy the wafer area inside the DRAN chip, and the cost of the DRAM chip is reduced.
Fig. 8 is a circuit diagram of a Vp charge pump circuit based on the power supply system shown in fig. 6. Fig. 9 is a timing diagram based on the Vp charge pump circuit shown in fig. 8. Fig. 10 is a circuit diagram generated based on Vpclk of fig. 8. Fig. 11 is a circuit diagram generated based on Vpclken of fig. 10.
As shown in fig. 10, the reference voltage Vref reaches a high level shortly after VDD is supplied, and the external controller enables the EN signal to operate the charge pump circuit of fig. 8, pumping gradually increases Vp voltage. In fig. 9, after Vp reaches the target voltage, the Vpclk signal is stopped, causing the charge pump circuit of fig. 8 to stop operating. If Vp is lower than the target voltage, vpclk starts to be generated, so that the charge pump circuit of fig. 8 starts to operate (pump).
FIG. 10 is a Vclk generation circuit, wherein the generation of Vclk begins when Vclk en is high; when Vpclken is low, vpclk stops being generated. Fig. 11 is a circuit for generating Vpclken, in which the voltage dividing resistors R1 and R2 can be designed according to a specific application scenario.
Fig. 12 is a circuit diagram of a Vbb charge pump circuit based on the power supply system shown in fig. 6. Fig. 13 is a circuit diagram of a Vnwl charge pump circuit based on the power supply system shown in fig. 6.
The principle of fig. 12 and 13 is basically similar to that of fig. 11, and will not be described again here.
Fig. 14 is a circuit diagram of a Vcore low dropout linear regulator based on the power supply system shown in fig. 6. Fig. 15 is a circuit diagram of a Veq low dropout linear regulator based on the power supply system shown in fig. 6.
Taking fig. 14 as an example for illustration, the low dropout linear regulator may employ an OP amplifier (operational amplifier ), the voltage value of which the positive input terminal is connected with the voltage value of Vext after voltage division, the values of R3 and R4 may be adjusted according to a specific application scenario, the negative input terminal inputs the fed-back Vcore, and the Vext connected with the third input terminal of the OP amplifier is used for playing an amplifying and rectifying role.
The resistances of R3 and R4 may be the same or different. Similarly, the resistances of the voltage dividing resistors R5 and R6 in fig. 15 may be the same or different.
Exemplary embodiments of the power supply system and semiconductor package set presented by the present disclosure are described and/or illustrated in detail above. Embodiments of the present disclosure are not limited to the specific embodiments described herein, but rather, components and/or steps of each embodiment may be utilized independently and separately from other components and/or steps described herein. Each component and/or each step of one embodiment may also be used in combination with other components and/or steps of other embodiments. When introducing elements/components/etc. that are described and/or illustrated herein, the terms "a," "an," and "the" are intended to mean that there are one or more of the elements/components/etc. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements/components/etc., in addition to the listed elements/components/etc. Furthermore, the terms "first" and "second" and the like in the claims and in the description are used for descriptive purposes only and not for numerical limitation of their subject matter.
While the methods of making the spacers set forth in the present disclosure have been described in terms of various specific embodiments, those skilled in the art will recognize that the disclosure can be practiced with modification within the spirit and scope of the claims.
Claims (17)
1. A power supply system, comprising:
an internal voltage generation circuit including at least one voltage regulator for generating at least one internal voltage;
wherein the at least one internal voltage is used to supply two or more semiconductor chips stacked through a power chip interconnection structure;
the at least one voltage regulator comprises a first charge pump circuit, a second charge pump circuit, a third charge pump circuit, a first low dropout linear voltage regulator, a second low dropout linear voltage regulator and a third low dropout linear voltage regulator; wherein,
the first to third charge pump circuits are respectively used for outputting a first internal voltage, a second internal voltage and a third internal voltage according to an external voltage;
the first to third low dropout linear regulators are configured to output a fourth internal voltage, a fifth internal voltage, and a sixth internal voltage according to the external voltage, respectively;
wherein the first internal voltage is greater than the external voltage, and the second internal voltage and the third internal voltage are both opposite in polarity to the external voltage; the fourth to sixth internal voltages are each equal to or less than the external voltage.
2. The power supply system of claim 1, further comprising:
a reference voltage generating circuit for generating a reference voltage;
and each voltage regulator is used for outputting the first internal voltage, the second internal voltage, the third internal voltage, the fourth internal voltage, the fifth internal voltage and the sixth internal voltage according to the external voltage, the reference voltage and a power supply enabling signal.
3. A power supply system, comprising:
an internal voltage generation circuit including at least one voltage regulator for generating at least one internal voltage;
wherein the at least one internal voltage is used to supply two or more semiconductor chips stacked through a power chip interconnection structure;
the at least one voltage regulator comprises a first low dropout linear voltage regulator, a first charge pump circuit, a second low dropout linear voltage regulator, a third low dropout linear voltage regulator and a fourth low dropout linear voltage regulator; wherein,
the first to fourth low dropout linear regulators are respectively configured to output a first internal voltage, a fourth internal voltage, a fifth internal voltage, and a sixth internal voltage according to an external voltage;
the first to second charge pump circuits are respectively used for outputting a second internal voltage and a third internal voltage according to the external voltage;
wherein the first internal voltage, the fourth to sixth internal voltages are all less than or equal to the external voltage; the second internal voltage and the third internal voltage are both opposite in polarity to the external voltage.
4. A power supply system according to claim 3, further comprising:
a reference voltage generating circuit for generating a reference voltage;
and each voltage regulator is used for outputting the first internal voltage, the second internal voltage, the third internal voltage, the fourth internal voltage, the fifth internal voltage and the sixth internal voltage according to the external voltage, the reference voltage and a power supply enabling signal.
5. A semiconductor package assembly, comprising:
packaging a substrate;
the power supply system according to any one of claims 1 to 4, which is provided on the package substrate;
at least one semiconductor chip.
6. The semiconductor package assembly of claim 5, wherein the at least one semiconductor chip comprises a plurality of semiconductor chips, each of the plurality of semiconductor chips having the same electrical function.
7. The semiconductor package assembly of claim 6, wherein the semiconductor chip is a memory chip.
8. The semiconductor package assembly of claim 7, wherein the semiconductor chip is a DRAM chip.
9. The semiconductor package assembly of claim 6, wherein the plurality of semiconductor chips are vertically stacked in sequence on the power supply system.
10. The semiconductor package assembly of claim 9, wherein the power chip interconnect structure comprises a through silicon via.
11. The semiconductor package assembly of claim 6, wherein the plurality of semiconductor chips are disposed directly on the package substrate, respectively, and the power supply system is disposed directly on the package substrate.
12. The semiconductor package assembly of claim 11, wherein the power chip interconnect structure comprises metal wires.
13. The semiconductor package assembly of claim 6, wherein the plurality of semiconductor chips are vertically stacked in sequence on the package substrate, the power supply system being disposed directly on the package substrate.
14. The semiconductor package assembly of claim 5, wherein a diameter of the power chip interconnect structure is related to a number of the at least one semiconductor chip.
15. The semiconductor package assembly of claim 5, further comprising:
and the signal chip interconnection structure is used for inputting external control signals to each semiconductor chip and/or inputting data signals to or outputting data signals to each semiconductor chip through the packaging substrate.
16. The semiconductor package assembly of claim 5, wherein each semiconductor chip and the power supply system share a ground power supply provided by the package substrate.
17. The semiconductor package assembly according to claim 5, wherein a package size of the power supply system is equal to or smaller than a package size of each semiconductor chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811132440.7A CN109147835B (en) | 2018-09-27 | 2018-09-27 | Power supply system and semiconductor package assembly |
| PCT/CN2019/108429 WO2020063827A1 (en) | 2018-09-27 | 2019-09-27 | Power supply system and semiconductor package assembly |
| US17/211,550 US11482272B2 (en) | 2018-09-27 | 2021-03-24 | Power supply system and semiconductor package assembly |
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| CN201811132440.7A CN109147835B (en) | 2018-09-27 | 2018-09-27 | Power supply system and semiconductor package assembly |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103493137A (en) * | 2011-03-31 | 2014-01-01 | 英特尔公司 | Energy efficient power distribution for 3D integrated circuit stack |
| CN103814628A (en) * | 2011-09-19 | 2014-05-21 | 莫塞德技术公司 | Voltage regulation for 3d packages and methods of manufacturing same |
| CN105786072A (en) * | 2015-01-14 | 2016-07-20 | 旺宏电子股份有限公司 | Low dropout regulator, regulation device and driving method thereof |
| CN208767023U (en) * | 2018-09-27 | 2019-04-19 | 长鑫存储技术有限公司 | Power-supply system and semiconductor packages aggregate |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011123955A (en) * | 2009-12-11 | 2011-06-23 | Elpida Memory Inc | Semiconductor system |
-
2018
- 2018-09-27 CN CN201811132440.7A patent/CN109147835B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103493137A (en) * | 2011-03-31 | 2014-01-01 | 英特尔公司 | Energy efficient power distribution for 3D integrated circuit stack |
| CN103814628A (en) * | 2011-09-19 | 2014-05-21 | 莫塞德技术公司 | Voltage regulation for 3d packages and methods of manufacturing same |
| CN105786072A (en) * | 2015-01-14 | 2016-07-20 | 旺宏电子股份有限公司 | Low dropout regulator, regulation device and driving method thereof |
| CN208767023U (en) * | 2018-09-27 | 2019-04-19 | 长鑫存储技术有限公司 | Power-supply system and semiconductor packages aggregate |
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