CN109143038A - A kind of the ATE test method and device of S698-T chip - Google Patents
A kind of the ATE test method and device of S698-T chip Download PDFInfo
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- CN109143038A CN109143038A CN201811115596.4A CN201811115596A CN109143038A CN 109143038 A CN109143038 A CN 109143038A CN 201811115596 A CN201811115596 A CN 201811115596A CN 109143038 A CN109143038 A CN 109143038A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
It is provided by the invention a kind of for S698-T chip MFIO module, the ATE test method of SRAM module, the abnormal phenomenon of S698-T chip SRAM can be found in time, the test method can be with the functional characteristic of comprehensive verification S698-T chip SRAM, including the verifying of read-write data function, DC parameter verifying and alternating-current parameter verifying.The phenomenon that can quickly and accurately note abnormalities is tested to S698-T chip SRAM based on J750EX tester table, SOC chip testing efficiency is improved, shortens test period, reduce testing cost.
Description
Technical field
The present invention relates to integrated circuit testing field, in particular to the ATE test method and device of a kind of S698-T chip.
Background technique
With the development of integrated circuit technique, hundreds of millions of devices can integrate on a chip, and can integrate
It is pre-designed and IP (Intellectual Property) core, such as memory core by verifying, microprocessor core, DSP core
Deng.The integrated chip of this diversification has become the integrated system that can handle various information, referred to as System on Chip/SoC SOC
(System On a chip).SOC greatly reduces system cost, shortens the design cycle, accelerates the time of launch.
This new design pattern is that the SOC system integration shortens the design cycle, reduces design risk, but also give the calibration tape of SOC
Great challenge is carried out.
ATE (Automatic Test Equipment, automatic test equipment) is that one kind is carried out by computer control
Device, circuit board and the equipment of chip testing.It replaces hand labor by computer programming, and sequence is tested in the completion of automation
Column.
S698-T chip is a high-performance, highly reliable SoC chip, and highest dominant frequency IUCLK is 200MHz, frequency outside highest
SYSCLK is 100MHz, and core power voltage power supply range is 1.2V ± 0.1V, I O power supply voltage power supply range be 3.3V ±
All input pins and bi-directional pin of 0.3V, S698-T chip can be compatible with 5V input.The addressing of the area chip SRAM S698-T is empty
Between be 1024M byte, be divided into 5 BANK, corresponding 5 pieces select ramsn [4:0].The packing forms of S698-T chip are plastic packaging ball
Shape array package PBGA352, ceramic spherical array package CBGA352 and ceramic aciculiform array package CPGA352.
The multi-functional I/O port MFIO module of S698-T chip, memory SRAM test are different from previous memory test,
S698-T chip SRAM test will carry out again dependence test on the basis of S698-T chip normally starts work.J750EX test
Board is a high integration of Teradyne company of u s company and the test machine of low price, because its cost performance is prominent, opens
It is easy to send out test program, is widely used in the test of digit chip system.Based on J750EX tester table to S698-T core
Piece SRAM tests the phenomenon that can quickly and accurately note abnormalities, and improves SOC chip testing efficiency, shortens test period, reduces and surveys
Try cost.Therefore, the ATE test method for developing a kind of S698-T chip SRAM, the SRAM for being conducive to meet S698-T chip are surveyed
Examination, or even convenient, effectively method is provided to the test of all SOC chips.
Summary of the invention
It is provided by the invention a kind of for the multi-functional I/O port MFIO module of S698-T chip, the ATE of memory SRAM module
Test method can find that the abnormal phenomenon of S698-T chip SRAM, the test method can be with comprehensive verification S698-T in time
The functional characteristic of chip SRAM, including the verifying of read-write data function, DC parameter verifying and alternating-current parameter verifying.Based on J750EX
Tester table tests the phenomenon that can quickly and accurately note abnormalities to S698-T chip SRAM, improves SOC chip testing efficiency, contracting
Short test period reduces testing cost.
Detailed description of the invention
Fig. 1 show one embodiment flow chart of the ATE test method for the S698-T chip that the application is proposed；
Fig. 2 show one embodiment submethod process of the ATE test method for the S698-T chip that the application is proposed
Figure；
Fig. 3 show one embodiment submethod process of the ATE test method for the S698-T chip that the application is proposed
Figure；
Fig. 4 show one embodiment flow chart of the ATE test method for the S698-T chip that the application is proposed；
Fig. 5 show one embodiment function structure chart of the ATE test method for the S698-T chip that the application is proposed；
Fig. 6 show the simulation document storage file format of the ATE test method for the S698-T chip that the application is proposed；
Fig. 7 show the vector file format of the application J750EX tester table identification；
Fig. 8 show the vector file format of ATE test program of the invention.
Specific embodiment
It is carried out below with reference to technical effect of the embodiment and attached drawing to the design of the application, specific structure and generation clear
Chu, complete description, to be completely understood by the purpose, scheme and effect of the application.It should be noted that the case where not conflicting
Under, the features in the embodiments and the embodiments of the present application can be combined with each other.The identical attached drawing mark used everywhere in attached drawing
Note indicates the same or similar part.
Herein described S698-T chip is Embedded control field and a high-performance, highly reliable developed
SoC chip, highest dominant frequency IUCLK are 200MHz, and frequency SYSCLK is 100MHz outside highest, and core power voltage power supply range is
1.2V ± 0.1V, I O power supply voltage power supply range are 3.3V ± 0.3V, all input pins and bi-directional pin of S698-T chip
5V input can be compatible with.S698-T chip SRAM area's addressing space is 1024M byte, is divided into 5 BANK, corresponding 5 pieces choosing
ramsn[4:0].The packing forms of S698-T chip are that plastic packaging ball array encapsulates PBGA352, ceramic spherical array package
CBGA352 and ceramic aciculiform array package CPGA352.
Integrated universal " multi-functional I/O interface MFIO module " in herein described S698-T chip slapper, total number of vias is
The direction on 16 tunnels, each road can be independently arranged with software, and every road I/O port has respective three register (configuration registers
CONFIG, period register CYCLE, duty cycle register DUTY) output characteristics of MFIO is set.
The addressing space of herein described S698-T chip SRAM is 1024M byte, is divided into 5 BANK, corresponding 5 pieces choosing
ramsn[4:0]。
It is the change to the format of data information memory that simulation document of the present invention, which changes into test vector, by simulation document
Format is converted into the vector file format of ATE tester table identification.Selected ATE tester table is J750EX, J750EX test
The vector file format of board identification is as shown in Figure 7.The matched programming software of J750EX tester table is converted into vector file
The vector file format that J750EX test program is used, the vector file format that ATE test program is used are as shown in Figure 8.
The electrical connection of S698-T chip and ATE tester table of the present invention is by the address of S698-T chip, number
It is electrically connected according to, chip select enable signal foot and J750EX tester table signal path, the power supply of supply pin and J750 tester table
The ground of channel electrical connection, ground pin and J750 tester table is electrically connected.The electricity of S698-T chip and J750EX tester table
Gas connection is to be attached by pinboard, and place S698-T chip by installing chip test base additional on pinboard.S698-
All I/O pins of T chip, power supply and ground pin are connect by chip test base with pinboard, and pinboard is placed into J750EX survey
On motherboard in commissioning stage, complete in this way S698-T chip I/O foot, power supply and ground pin respectively with J750EX board channel, electricity
The electrical connection of source foot and ground.
One embodiment flow chart of the ATE test method of S698-T chip shown in referring to Fig.1, the application propose
The ATE test method of S698-T chip, comprising the following steps:
S100 the test code comprising chip parameter) is read in；
It S200 is) test data of ATE tester table identification by the test code conversion；
S300) test data is sent to chip；
S400) the output data that storage chip responds the test data.
Preferably, above-mentioned further includes that will test code to switch to simulation document, and the simulation document is test code
Modelsim simulation document.Referring to Fig. 6, the simulation document of the ATE test method of the S698-T chip proposed by the application is deposited
Store up file format；Fig. 7 show the vector file format of the application J750EX tester table identification；Fig. 8 show of the invention
The vector file format of ATE test program.
Referring to one embodiment flow chart of the ATE test method of S698-T chip shown in Fig. 2, the step S200 packet
Include following postposition step:
S201 the numerical value of chip pin) is read；
S202 chip input clock cycle and/or chip signal foot time-constrain) are read；
S203 the communication setting between chip and tester table) is executed.
Referring to one embodiment flow chart of the ATE test method of S698-T chip shown in Fig. 3, the step S300 packet
Include following previous step:
S301) reference data of chip is loaded into the storage unit of ATE tester table；
S302 the input signal values in the reference data) are obtained；
S303) according to the input signal values to chip input signal.
Specifically, the reference data is the function pattern of MFIO module or SRAM block, by MFIO module or SRAM block
Function pattern be loaded into the storage unit of J750EX tester table.J750EX tester table is provided according to function pattern
Input signal values give S698-T chip to provide pumping signal, S698-T chip makes corresponding function according to pumping signal, then
The signal value that chip is exported, compares with the output signal value stored in function pattern, thus to the function of MFIO into
Row test.
Such as Fig. 4, when needing to carry out the functional test of chip, the step S400 further includes following postposition step:
S500) data of S698-T chip signal output and the reference data are compared.
Further, when S698-T chip signal output data are consistent with the reference data, functional test passes through, otherwise
Not pass through.
Function structure chart referring to Figure 5, the application propose a kind of ATE test device of S698-T chip, including following
Module: module is read in, for reading in the test code comprising chip parameter；First conversion module is used for the test code
Be converted to simulation document；Second conversion module, for the simulation document to be converted to the test vector of ATE tester table identification
File；Module is write, for writing ATE test program；Test module, for testing chip；Memory module, for storing up
Deposit the data of chip output.
The present invention also provides a kind of computer readable storage mediums, are stored thereon with computer instruction.The instruction is located
It manages and is realized when device executes such as the step of any one of aforementioned method.
Embodiment one: DC parameter test is carried out to the MFIO module of S698-T chip.
According to operating condition as defined in S698-T detail specification, be set separately the core voltage of S698-T chip, IO voltage,
The value of input/output voltage, reference voltage carries out DC parameter survey to MFIO using the measuring unit of J750EX tester table
Examination.DC parameter test specifically includes: core power dynamic current Idd, core power quiescent current Idds, I O power supply Static Electro
Iddios is flowed, high/low level leakage current I is inputtedIH/IIL, export high/low level voltage VOH/VOL, short-circuit output current IOS。
Embodiment two: functional test is carried out to the MFIO module of S698-T chip.
According to operating condition as defined in S698-T detail specification, be set separately the core voltage of S698-T chip, IO voltage,
The value of input/output voltage, reference voltage defines the input clock cycle of S698-T chip, defines S698-T chip signal foot
The function pattern of MFIO is loaded into the storage unit of J750EX tester table by time-constrain.J750EX tester table according to
The input signal values that function pattern is provided provide pumping signal to S698-T chip, and S698-T chip is made according to pumping signal
Corresponding function out, then the signal value that chip is exported, compare with the output signal value stored in function pattern, from
And the function of MFIO is tested.
Embodiment three: AC parameter test is carried out to the MFIO module of S698-T chip.
According to operating condition as defined in S698-T detail specification, be set separately the core voltage of S698-T chip, IO voltage,
The value of input/output voltage, reference voltage, define S698-T chip input clock, define S698-T chip signal foot when
Between constrain, the function pattern of MFIO is loaded into the storage unit of J750EX tester table, the alternating-current parameter of MFIO is carried out
Test.Alternating-current parameter includes system clock to output delay time Tgrgpio0, retention time of the system clock to input
Tgrgpio3。
Example IV: DC parameter test is carried out to the SRAM module of S698-T chip.
According to operating condition as defined in S698-T detail specification, be set separately the core voltage of S698-T chip, IO voltage,
The value of input/output voltage, reference voltage carries out DC parameter survey to SRAM using the measuring unit of J750EX tester table
Examination.
The DC parameter test specifically includes: core power dynamic current Idd, core power quiescent current Idds, IO
Power supply quiescent current Iddios inputs high/low level leakage current IIH/IIL, export high/low level voltage VOH/VOL, short circuit output
Electric current IOS。
Embodiment five: functional test is carried out to the SRAM module of S698-T chip.
According to operating condition as defined in S698-T detail specification, be set separately the core voltage of S698-T chip, IO voltage,
The value of input/output voltage, reference voltage defines the input clock cycle of S698-T chip, defines S698-T chip signal foot
The function pattern of SRAM is loaded into the storage unit of J750EX tester table by time-constrain.J750EX tester table according to
The input signal values that function pattern is provided provide pumping signal to S698-T chip, and S698-T chip is made according to pumping signal very much
Corresponding function out, then the signal value that chip is exported, compare with the output signal value stored in function pattern, from
And the function of SRAM is tested.
Embodiment six: AC parameter test is carried out to the SRAM module of S698-T chip.
According to operating condition as defined in S698-T detail specification, be set separately the core voltage of S698-T chip, IO voltage,
The value of input/output voltage, reference voltage, define S698-T chip input clock, define S698-T chip signal foot when
Between constrain, the function pattern of SRAM is loaded into the storage unit of J750EX tester table, the alternating-current parameter of SRAM is carried out
Test.
The alternating-current parameter includes address output delay time Tftmctrl0, chip selection signal RAMSN output delay time
Tftmctrl1, it write enable signal RWEN output delay time Tftmctrl2, data output delay time Tftmctrl3, reads to make
It can signal RAMOEN output delay time Tftmctrl4.
It should be appreciated that the embodiment of the present invention can be by computer hardware, the combination of hardware and software or by depositing
The computer instruction in non-transitory computer-readable memory is stored up to be effected or carried out.Standard volume can be used in the method
Journey technology-includes that the non-transitory computer-readable storage media configured with computer program is realized in computer program,
In configured in this way storage medium make computer operated in a manner of specific and is predefined-according to describing in a particular embodiment
Method and attached drawing.Each program can be realized with the programming language of level process or object-oriented with logical with computer system
Letter.However, if desired, the program can be realized with compilation or machine language.Under any circumstance, the language can be compiling or
The language of explanation.In addition, the program can be run on the specific integrated circuit of programming for this purpose.
Further, this method can be realized in being operably coupled to suitable any kind of computing platform, including
But it is not limited to PC, mini-computer, main frame, work station, network or distributed computing environment, individual or integrated
It computer platform or is communicated with charged particle tool or other imaging devices etc..Each aspect of the present invention can be with storage
No matter machine readable code on non-transitory storage medium or equipment is moveable or is integrated to calculate and put down to realize
Platform, such as hard disk, optically read and/or write-in storage medium, RAM, ROM, so that it can be read by programmable calculator, when depositing
Storage media or equipment can be used for configuration and operation computer to execute process described herein when being read by computer.In addition,
Machine readable code, or part thereof can be transmitted by wired or wireless network.When such media include in conjunction with microprocessor or
When other data processors realize the instruction or program of steps described above, invention as described herein includes that these and other are different
The non-transitory computer-readable storage media of type.When methods and techniques according to the present invention programming, the present invention is also
Including computer itself.
This document describes embodiment of the disclosure, become known for executing optimal mode of the invention including inventor.It is readding
After having read foregoing description, the variation of these embodiments will be apparent those skilled in the art.Inventor wishes skill
Art personnel optionally use such modification, and inventor be intended to by be different from it is as specifically described herein in a manner of practice this public affairs
The embodiment opened.Therefore, through applicable legal permission, the scope of the present disclosure includes describing in this appended claims
The all modifications and equivalent of theme.In addition, the scope of the present disclosure covers any of the above-mentioned element in its all possible modification
Combination, unless herein in addition instruction or otherwise significantly with contradicted by context.
Although description of the invention is quite detailed and especially several embodiments are described, it is not
Any of these details or embodiment or any specific embodiments are intended to be limited to, but should be considered as is by reference to appended
A possibility that claim provides broad sense in view of the prior art for these claims explanation, to effectively cover the present invention
Preset range.In addition, with the foreseeable embodiment of inventor, present invention is described above, its purpose is to be provided with
Description, and those still unforeseen at present change to unsubstantiality of the invention can still represent equivalent modifications of the invention.
Claims (9)
1. a kind of ATE test method of S698-T chip, which comprises the steps of:
S100 the test code comprising chip parameter) is read in；
It S200 is) test data of ATE tester table identification by the test code conversion；
S300) test data is sent to chip；
S400) the output data that storage chip responds the test data.
2. the method according to claim 1, wherein step S200 further includes following postposition step:
S201 the numerical value of chip pin) is read；
S202 chip input clock cycle and/or chip signal foot time-constrain) are read；
S203 the communication setting between chip and tester table) is executed.
3. the method according to claim 1, wherein the chip parameter include at least following one kind, chip
One or more combinations of core voltage, IO voltage, input voltage, output voltage and reference voltage or above-mentioned parameter.
4. according to the method described in claim 3, it is characterized in that, step S300 further includes following previous step,
S301) reference data of chip is loaded into the storage unit of ATE tester table；
S302 the input signal values in the reference data) are obtained；
S303) according to the input signal values to chip input signal.
5. according to the method described in claim 4, it is characterized in that, the reference data is the multi-functional I/O port MFIO base of chip
Quasi- data or memory SRAM reference data.
6. according to claim 1, method described in any one of 4,5, which is characterized in that step S400 further includes following postposition
Step:
S500) data of chip signal output and the reference data are compared.
7. the method according to claim 1, wherein the tester table is J750EX tester table.
8. a kind of ATE test device of S698-T chip, which is characterized in that comprise the following modules:
Module is read in, for reading in the test code comprising chip parameter；
Conversion module, for being the test data of ATE tester table identification by the test code conversion；
Sending module, for sending the test data to chip；
Memory module, the output data that the test data is responded for storage chip.
9. a kind of computer readable storage medium, is stored thereon with computer instruction, it is characterised in that the instruction is held by processor
The step of method as described in any one of claims 1 to 7 is realized when row.
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| CN201811115596.4A CN109143038A (en) | 2018-09-25 | 2018-09-25 | A kind of the ATE test method and device of S698-T chip |
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| CN201811115596.4A CN109143038A (en) | 2018-09-25 | 2018-09-25 | A kind of the ATE test method and device of S698-T chip |
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Cited By (7)
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| CN110045266A (en) * | 2019-04-23 | 2019-07-23 | 珠海欧比特宇航科技股份有限公司 | A kind of chip universal testing method and device |
| CN112285529A (en) * | 2020-09-28 | 2021-01-29 | 上海华岭集成电路技术股份有限公司 | Method for controlling relay by using ATE test vector |
| CN112444731A (en) * | 2020-10-30 | 2021-03-05 | 海光信息技术股份有限公司 | Chip testing method and device, processor chip and server |
| CN112630622A (en) * | 2020-12-17 | 2021-04-09 | 珠海芯网测控有限公司 | Method and system for pattern compiling and downloading test of ATE (automatic test equipment) |
| CN113359014A (en) * | 2021-08-11 | 2021-09-07 | 深圳英集芯科技股份有限公司 | Fool-proof method and system for chip test |
| CN117151032A (en) * | 2023-10-27 | 2023-12-01 | 零壹半导体技术(常州)有限公司 | Test method for detecting PCB (printed circuit board) by ATE (automatic test equipment) based on Kelvin |
| CN117829052A (en) * | 2024-01-15 | 2024-04-05 | 上海谐振半导体科技有限公司 | ModelSim and test system joint simulation debugging method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112285529A (en) * | 2020-09-28 | 2021-01-29 | 上海华岭集成电路技术股份有限公司 | Method for controlling relay by using ATE test vector |
| CN112444731A (en) * | 2020-10-30 | 2021-03-05 | 海光信息技术股份有限公司 | Chip testing method and device, processor chip and server |
| CN112630622A (en) * | 2020-12-17 | 2021-04-09 | 珠海芯网测控有限公司 | Method and system for pattern compiling and downloading test of ATE (automatic test equipment) |
| CN112630622B (en) * | 2020-12-17 | 2022-05-31 | 珠海芯业测控有限公司 | Method and system for pattern compiling, downloading and testing of ATE (automatic test equipment) |
| CN113359014A (en) * | 2021-08-11 | 2021-09-07 | 深圳英集芯科技股份有限公司 | Fool-proof method and system for chip test |
| CN117151032A (en) * | 2023-10-27 | 2023-12-01 | 零壹半导体技术(常州)有限公司 | Test method for detecting PCB (printed circuit board) by ATE (automatic test equipment) based on Kelvin |
| CN117151032B (en) * | 2023-10-27 | 2024-01-23 | 零壹半导体技术(常州)有限公司 | Test method for detecting PCB (printed circuit board) by ATE (automatic test equipment) based on Kelvin |
| CN117829052A (en) * | 2024-01-15 | 2024-04-05 | 上海谐振半导体科技有限公司 | ModelSim and test system joint simulation debugging method |
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