CN109119458B - 隔离结构及工艺方法 - Google Patents

隔离结构及工艺方法 Download PDF

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CN109119458B
CN109119458B CN201810832763.0A CN201810832763A CN109119458B CN 109119458 B CN109119458 B CN 109119458B CN 201810832763 A CN201810832763 A CN 201810832763A CN 109119458 B CN109119458 B CN 109119458B
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许昭昭
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623Buried supplementary region, e.g. buried guard ring
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

本发明公开了一种隔离结构,在P型衬底上具有P型外延,在P型外延中,形成有环形的N型深阱,以及位于环形中心区域的P阱;环形的N型深阱与P阱之间间隔外延层;所述的环形的N型深阱的下方还具有N型埋层,P阱的下方具有P型埋层;N型深阱中还包含有环形的N阱;在P型外延的表面具有场氧层,在场氧层中开有窗口,分别将N阱,以及P阱引出;所述的P型埋层,其正下方的衬底中还具有N型注入区,P型埋层和N型注入区两者互不接触。本发明在P型埋层的正下方形成N型注入区。N型掺杂改变了P型埋层下方的电势分布,拓宽了耗尽区的宽度,从而提高了该隔离结构的击穿电压。本发明工艺方法只调整了注入,无需增加额外的工艺步骤。

Description

隔离结构及工艺方法
技术领域
本发明涉及半导体器件领域,特别是指一种隔离结构,本发明还涉及所述隔离结构的工艺方法。
背景技术
常规的隔离结构如图1所示。隔离时电压偏置为:左边的N型重掺杂区109接正电压(接地),中间的P型重掺杂110接地(接地),右边的N型重掺杂接地(接正电压)。即以上两种偏压方式都有可能存在。
图2为常规隔离结构击穿时的耗尽区分布(左边N型重掺杂区接正电压)。可以看出,当击穿发生时,中间的P型埋层102和P型外延层104在横向上只被耗尽了一半。即该结构的耐压只由整个隔离结构的左半边(右半边)来决定。因此击穿电压等于由N型埋层103和中间的P型外延层104及P型埋层102构成的PN结的击穿电压。
拓宽耗尽区的宽度使得中间的P型埋层102和P型外延层104在横向上全部耗尽有利于提高隔离的击穿电压,减小隔离占用的面积,降低制造成本。
发明内容
本发明所要解决的技术问题在于提供一种隔离结构,能提高隔离结构的击穿电压。
本发明所要解决的另一技术问题在于提供所述隔离结构的工艺方法,工艺简单并控制制造成本。
为解决上述问题,本发明所述的隔离结构,在P型衬底上具有P型外延,在P型外延中,形成有环形的N型深阱,以及位于环形中心区域的P阱;环形的N型深阱与P阱之间间隔外延层。
所述的环形的N型深阱的下方还具有N型埋层,P阱的下方还具有P型埋层。
所述的环形的N型深阱中,还包含有环形的N阱。
在P型外延的表面具有场氧层,在场氧层中开有窗口,分别将N阱,以及P阱引出。
所述的P型埋层,其正下方的衬底中还具有N型注入区,P型埋层和N型注入区两者互不接触。
进一步地,所述的N型注入区为高能量的N型离子注入,注入能量为500~2000keV,注入的剂量为1E11~5E13cm-2
进一步地,所述的N型注入区,在P型埋层下方调节电场的电势分布,拓宽耗尽区的宽度,即N型注入区能辅助P型埋层与P型外延层耗尽,提高隔离结构的击穿电压。
本发明所述的隔离结构的工艺方法,在利用光刻胶在P型衬底上进行选择性注入P型埋层时,首先进行一次高能量的N型离子注入,在衬底中形成N型注入区;然后再进行P型埋层的离子注入,即P型埋层的形成和N型注入区的形成采用同一光刻掩膜版。
进一步地,所述的高能量的N型离子注入,注入能量为500~2000keV,注入的剂量为1E11~5E13cm-2
进一步地,所述的高能量的N型离子注入,采用的光刻胶的厚度要大于仅制作P型埋层的工艺中的光刻胶厚度。
本发明所述的隔离结构,在P型埋层的正下方形成N型注入区。N型掺杂改变了P型埋层下方的电势分布,拓宽了耗尽区的宽度。即N型注入区能帮助中间的P型埋层和P型外延层在横向上耗尽,从而提高了该隔离结构的击穿电压。当N型掺杂使得中间的P型外延层和P型埋层在横向上全被耗尽时,击穿电压达到最大值。本发明工艺方法只调整了注入,无需增加额外的工艺步骤,因此有利于降低制造成本。
附图说明
图1 是现有的隔离结构示意图。
图2 是现有的隔离结构的电场仿真图,图中显示耗尽区只使用了一半。
图3 是本发明的隔离结构示意图。
图4 是本发明的隔离结构的工艺步骤示意图,图中形成N型埋层。
图5 是本发明的隔离结构的工艺步骤示意图,图中形成N型注入区及P型埋层。
图6 是本发明与传统隔离结构的击穿电压仿真对比图。
图7 是本发明与传统隔离结构的电场分布仿真对比图。
附图标记说明
101—P型衬底, 102—P型埋层,103—N型埋层, 104—P型外延层,105—P阱,106—N型深阱, 107—N阱, 108—场氧区,109—N型重掺杂区,110—P型重掺杂区,111—高能量的N型注入区,112—光刻胶。
具体实施方式
本发明所述的隔离结构,如图3所示,在P型衬底上具有P型外延,在P型外延中,形成有环形的N型深阱,以及位于环形中心区域的P阱;环形的N型深阱与P阱之间间隔外延层。
所述的环形的N型深阱的下方还具有N型埋层,P阱的下方还具有P型埋层。所述的环形的N型深阱中,还包含有环形的N阱。在P型外延的表面具有场氧层,在场氧层中开有窗口,分别将N阱,以及P阱引出。所述的P型埋层,其正下方的衬底中还具有N型注入区,P型埋层和N型注入区两者互不接触。
用光刻胶在P型衬底上选择性注入P型埋层的时候,增加一道高能量的N型掺杂注入,即在P型埋层的正下方形成N型注入区111。N型掺杂111改变了P型埋层下方的电势分布,拓宽了耗尽区的宽度。如图7所示,即111能帮助中间的P型埋层和P型外延层耗尽,从而提高了该隔离结构的击穿电压。当N型掺杂111使得中间的P型外延层和P型埋层全被耗尽时,该击穿电压达到最大值。本方法拓宽了耗尽区的宽度使得中间的P型埋层和P型外延层在横向上全部耗尽,有利于提高隔离的击穿电压,如图6所示,本发明与传统隔离结构相比,击穿电压能提升约20V。减小隔离占用的面积,降低制造成本。
本发明所述的隔离结构的工艺方法,首先如图4所示,在P型衬底上注入形成N型埋层103。然后在利用光刻胶112打开P型埋层的注入窗口,在P型衬底上进行选择性注入P型埋层时,首先进行一次注入能量为500~2000keV,注入的剂量为1E11~5E13cm-2的高能量的N型离子注入,在衬底中形成N型注入区,如图5所示。由于高能量的N型离子注入,采用的光刻胶的厚度要比传统的仅制作P型埋层的工艺中的光刻胶厚度要厚一些。
然后再进行P型埋层的离子注入,即P型埋层的形成和N型注入区的形成采用同一光刻掩膜版。
再去除光刻胶,淀积外延形成P型外延层,形成STI场氧,选择性注入形成N型深阱106、P阱105、N阱107、N型重掺杂区109、P型重掺杂区110,并通过后段工艺将109和110引出,形成如图3所示的结构。
本方法只调整了注入,无需增加额外的工艺步骤,因此有利于降低制造成本。
以上仅为本发明的优选实施例,并不用于限定本发明。对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。

Claims (6)

1.一种隔离结构,在P型衬底上具有P型外延,在P型外延中,形成有环形的N型深阱,以及位于环形中心区域的P阱;环形的N型深阱与P阱之间间隔外延层;
所述的环形的N型深阱的下方还具有N型埋层,P阱的下方还具有P型埋层;
所述的环形的N型深阱中,还包含有环形的N阱;
在P型外延的表面具有场氧层,在场氧层中开有窗口,分别将N阱,以及P阱引出;
其特征在于:所述的P型埋层,其正下方的衬底中还具有N型注入区,P型埋层和N型注入区在横向上具有相同的尺寸;P型埋层和N型注入区两者互不接触。
2.如权利要求1所述的隔离结构,其特征在于:所述的N型注入区为高能量的N型离子注入,注入能量为500~2000keV,注入的剂量为1E11~5E13cm-2
3.如权利要求1所述的隔离结构,其特征在于:所述的N型注入区,在P型埋层下方调节电场的电势分布,拓宽耗尽区的宽度,即N型注入区能辅助P型埋层与P型外延层耗尽,提高隔离结构的击穿电压。
4.制造如权利要求1所述的隔离结构的工艺方法,其特征在于:在利用光刻胶在P型衬底上进行选择性注入P型埋层时,首先进行一次高能量的N型离子注入,在衬底中形成N型注入区;然后再进行P型埋层的离子注入,即P型埋层的形成和N型注入区的形成采用同一光刻掩膜版。
5.如权利要求4所述的隔离结构的工艺方法,其特征在于:所述的高能量的N型离子注入,注入能量为500~2000keV,注入的剂量为1E11~5E13cm-2
6.如权利要求4所述的隔离结构的工艺方法,其特征在于:所述的高能量的N型离子注入,采用的光刻胶的厚度要大于仅制作P型埋层的工艺中的光刻胶厚度。
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