CN109103144A - A kind of array substrate and preparation method thereof, display panel - Google Patents
A kind of array substrate and preparation method thereof, display panel Download PDFInfo
- Publication number
- CN109103144A CN109103144A CN201810972621.4A CN201810972621A CN109103144A CN 109103144 A CN109103144 A CN 109103144A CN 201810972621 A CN201810972621 A CN 201810972621A CN 109103144 A CN109103144 A CN 109103144A
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- array substrate
- preparation
- insulating layer
- metal
- metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70216—Mask projection systems
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Abstract
The present invention provides a kind of array substrate and preparation method thereof, display panel, belongs to field of display technology, can solve the problems, such as that the light exposure deficiency between existing two metal line causes two lines to be connected to and can not normally transmit signal together.The preparation method of array substrate of the invention, multiple spaced strip projected parts are provided in the insulating layer of formation, the protrusion can will be padded at the portion for the metal layer being subsequently formed, it is equivalent to the closer apart from exposure machine of the position that it can make metal layer respective protrusions, therefore light exposure is larger, after exposing in this way, line situation will not occur between the adjacent metal wire of formation.
Description
Technical field
The invention belongs to field of display technology, and in particular to a kind of array substrate and preparation method thereof, display panel.
Background technique
Liquid crystal display panel includes the area wiring (Fan-out) in the display area (Active Area) and edge of display area.With
The development of display technology, display product need to shield design with narrow frame, comprehensively to realize perfect visual effect, this just needs to subtract
The line spacing of small wiring region.It prescribes a time limit when wires design reaches exposure machine resolution pole, wiring region is easy to happen defect, such as adjacent
Light exposure between two metal lines is insufficient or can not be exposed, and will lead to two lines and be connected to can not normally transmit signal together.
Summary of the invention
The present invention causes two lines to be connected to for the light exposure deficiency between existing two metal line can not normally pass together
The problem of delivery signal, provides a kind of array substrate and preparation method thereof, display panel.
Solving technical solution used by present invention problem is:
A kind of preparation method of array substrate, including following preparation step:
Insulating layer is formed on the substrate, includes wiring region at the position at at least partly edge of the substrate；In wiring region,
The insulating layer has multiple spaced strip projected parts away from the face of substrate；
Metal layer is formed above the insulating layer for completing above-mentioned steps；
By the metal layer patterning of wiring region, so that at position between two protrusions of the correspondence of the metal layer and correspondence
It is different that the position of protrusion is in the light exposure received in patterning process.
Optionally, where perpendicular to the substrate on the direction in face, the size range of the protrusion is 200-4000
Ethylmercurichlorendimide.
Optionally, the formation insulating layer includes following preparation step:
Insulating coating is formed on the substrate using insulating materials；
Insulating coating is patterned using halftone exposure technique, obtains having in the face away from substrate of wiring region multiple
The insulating layer of strip projected parts.
Optionally, where perpendicular to the substrate on the direction in face, the size range of the insulating coating is 4200-
8000 Ethylmercurichlorendimides.
Optionally, metal wire is formed at the position between two protrusions of the correspondence of the metal layer, makes the metal layer
Respective protrusions position at formed metal wire interval；The spacing of two adjacent metal wires is 1-10 μm, the metal wire
Line width be 1-10 μm.
Optionally, described by the metal layer patterning of wiring region is that mask plate is used to be exposed with by the gold of wiring region
Belong to pattern layers, the mask plate includes the mask strip of multiple splicings, and two adjacent mask strips have overlap edge, the insulation
The strip projected parts are arranged in the position of the corresponding overlap edge of layer.
Optionally, a plurality of spaced metal wire is formed at the position of the respective protrusions of the metal layer, it is adjacent
Two raised spacing are 70-120 μm, and the width of the protrusion is 5-40 μm.
Optionally, the insulating layer is gate insulating layer, and the metal wire is data line, the method also includes:
Before forming gate insulating layer, in the step of viewing area forms grid；
Forming the step of forming active layer, pixel electrode between gate insulating layer and metal layer.
The present invention also provides a kind of array substrates, adopt and prepare to be formed with the aforedescribed process.
The present invention also provides a kind of display panels, including above-mentioned array substrate.
Detailed description of the invention
Fig. 1 is the schematic top plan view of array substrate prepared by the method for the embodiment of the present invention 1；
Fig. 2 is the flow diagram of array substrate prepared by the method for the embodiment of the present invention 1；
Fig. 3 is the schematic process flow diagram of array substrate prepared by the method for the embodiment of the present invention 2；
Fig. 4 is a kind of schematic cross-section in part of array substrate prepared by the method for the embodiment of the present invention 2；
Fig. 5 is another schematic cross-section in part of array substrate prepared by the method for the embodiment of the present invention 2；
Wherein, appended drawing reference are as follows: 1, substrate；2, wiring region；30, gate insulating layer；3, insulating layer；31, raised；4, metal
Layer；40, metal wire.
Specific embodiment
Technical solution in order to enable those skilled in the art to better understand the present invention, with reference to the accompanying drawing and specific embodiment party
Present invention is further described in detail for formula.
Embodiment 1:
The present embodiment provides a kind of preparation methods of array substrate, as shown in Figure 1 and Figure 2, including following preparation step:
Insulating layer 3 is formed on substrate 1, includes wiring region 2 at the position at at least partly edge of the substrate 1；In cloth
Line area 2, the insulating layer 3 have multiple spaced strip projected parts 31 away from the face of substrate 1；
Metal layer 4 is formed above the insulating layer 3 for completing above-mentioned steps；
The metal layer 4 of wiring region 2 is patterned, so that at the position between two protrusions 31 of the correspondence of the metal layer 4
It is different that the light exposure received in patterning process is in the position of respective protrusions 31.
The preparation method of the array substrate of the present embodiment is provided with multiple spaced items in the insulating layer 3 of formation
Shape protrusion 31, the protrusion 31 can will be padded at the portion for the metal layer 4 being subsequently formed, metal can be made by being equivalent to it
The position of 4 respective protrusions 31 of layer it is closer apart from exposure machine, therefore light exposure is larger, in this way after exposure, the adjacent metal of formation
Line situation will not occur between line 40.
Embodiment 2:
The present embodiment provides a kind of preparation methods of array substrate, as shown in Figure 3, Figure 4, including following preparation step:
Optionally, S01, using gate mask plate (Gate Mask), being formed by patterning processes includes grid and grid line
Figure.Wherein, grid is formed in viewing area, and grid line is formed in the wiring region on viewing area periphery.
Optionally, S02, on the substrate for completing above-mentioned steps, using patterning processes, being formed in viewing area includes active layer
Figure；Specifically, polysilicon film can be initially formed, a layer photoresist is then formed on polysilicon film, and photoresist is carried out
Then exposure and imaging carries out dry etching to polysilicon film, to form the figure for including active layer.
Optionally, S03, complete above-mentioned steps substrate on, viewing area formed pixel electrode；Specifically, can be first
Transparent conductive metal film is formed, using patterning processes, forms the figure including pixel electrode.Wherein, transparent conductive metal film is adopted
With electrically conducting transparents such as indium gallium zinc (IGZO), indium zinc oxide (IZO), tin indium oxide (ITO) or indium gallium tin (InGaSnO)
The formation of at least one of material.
S04, complete above-mentioned steps substrate on, formed gate insulating layer 30, wherein in wiring region, the grid is exhausted
Edge layer 30 has multiple spaced strip projected parts 31 away from the face of substrate 1.
As the optional embodiment of one of the present embodiment, the formation gate insulating layer 30 is walked including following preparation
It is rapid:
S04a, insulating coating is formed on the substrate using insulating materials；Specifically, chemistry can be enhanced with using plasma
Vapor deposition mode, low-pressure chemical vapor deposition mode, sub-atmospheric CVD mode or electron cyclotron resonance chemistry gas
Phase depositional mode or sputtering mode form insulating coating.
More specifically, where perpendicular to the substrate on the direction in face, the size range of the insulating coating is 4200-
8000 Ethylmercurichlorendimides.
That is, compared to the prior art, the thickness of the insulating coating in the present embodiment wants thick, for example, if existing skill
Insulation coating layer thickness in art is 4000 Ethylmercurichlorendimides, 200-4000 Ethylmercurichlorendimide or so is thickened in the present embodiment, wherein the part thickened
To be subsequently formed strip projected parts 31.
S04b, insulating coating is patterned using halftone exposure technique, is obtained in the face away from substrate 1 of wiring region 2
The gate insulating layer 30 with multiple strip projected parts 31.
Specifically, can use intermediate tone mask version in the step, intermediate tone mask version includes non-transmissive region, half transmitting
Region, transmission region, use positive photoresist.Wherein, transmission region is corresponded at the via hole of gate insulating layer 30, wiring region 2
Non-transmissive region is corresponded at the position of metal wire 40, the position between metal wire 40 corresponds to half transmitting region.Gate insulating layer 30
It after single exposure, etching, is then ashed, is then performed etching again to making, the position of corresponding metal wire 40
Gate insulating layer 30 with a thickness of 4000 Ethylmercurichlorendimides, the gate insulating layer 30 of the position of respective protrusions 31 with a thickness of 4200-
8000 Ethylmercurichlorendimides；I.e. on the direction perpendicular to the 1 place face of substrate, raised 31 size range is 200-4000 angstroms
Rice.
S05a, Source and drain metal level is formed above the gate insulating layer 30 for completing above-mentioned steps；Specifically, can use
At least one of molybdenum, molybdenum niobium alloy, aluminium, aluminium neodymium alloy, titanium or copper form source and drain metal electrodes film.
S05b, by the metal layer patterning of wiring region 2 so that the position between two protrusions 31 of the correspondence of the metal layer
Place forms metal wire 40, makes the interval that metal wire 40 is formed at the position of the respective protrusions 31 of the metal layer.
In a specific embodiment, as shown in figure 4, the spacing h1 of two adjacent metal wires is 1-10 μm, the gold
The line width h2 for belonging to line is 1-10 μm.
That is, a protrusion corresponds to the interval of two metal lines in the present embodiment, i.e., two adjacent protrusions are intermediate
Limit a metal line.
Inventors have found that usually laser is drawn along the Y-direction of exposure mask when mask fabrication in prior art exposure process
It is divided into the laggard line mask of multiple scanning areas to draw, the scanning area of two neighboring mask strip has certain overlapping, to ensure
The formation of mask pattern；Overlay regions multiple in this way can generate periodic difference, and after exposure, the position of corresponding overlay region will expose
Amount is insufficient, and signal can not normally be transmitted together by causing two lines to be connected to.
As the optional embodiment of one of the present embodiment, described by the metal layer patterning of wiring region 2 is using covering
Film version is exposed with by the metal layer patterning of wiring region 2, and the mask plate includes the mask strip of multiple splicings, and adjacent two
A mask strip has overlap edge, and the strip projected parts 31 are arranged in the position of the corresponding overlap edge of the insulating layer 3.
It is be easy to causeing the insufficient position of light exposure to be correspondingly arranged strip projected parts 31 in the present embodiment, can solve adjacent two
The problem of periodicity light exposure deficiency caused by the scanning area overlapping of a mask strip.
Specifically, a patterning processes can be used, formation includes the figure of source electrode, drain electrode, data line.Wherein, source electrode,
Drain electrode is formed in viewing area, and data line is formed in the wiring region 2 on viewing area periphery.
As shown in figure 4, will be at the portion of Source and drain metal level by the protrusion 31 of gate insulating layer 30 in the present embodiment
Padded, therefore the light exposure closer apart from exposure machine of position of Source and drain metal level respective protrusions 31 can be made by being equivalent to protrusion 31
It is larger, after exposing in this way, line situation will not occur between the adjacent metal wire 40 of formation, the data line for the metal that can be formed
Spacing be h1.
In another embodiment, it is set as shown in figure 5, forming a plurality of interval at the position of the respective protrusions of the metal layer
The metal wire set, two adjacent raised spacing are 70-120 μm, and the width of the protrusion is 5-40 μm.
That is, the corresponding multiple data lines of a protrusion that the method for the present embodiment is formed, raised width is 5-40 μ
m.It is understood that two adjacent protrusions are intermediate to limit a plurality of metal wire.
Optionally, S06, complete above-mentioned steps substrate 1 on form passivation layer；Specifically, it can be initially formed passivating film,
Then a patterning processes are used, the figure including passivation layer is formed.
Optionally, S07, complete above-mentioned steps substrate 1 on form public electrode；Specifically, can be initially formed transparent
Then conductive metal film uses patterning processes, form the figure including public electrode.Wherein, transparent conductive metal film uses oxygen
The transparent conductive materials such as change indium gallium zinc (IGZO), indium zinc oxide (IZO), tin indium oxide (ITO) or indium gallium tin (InGaSnO)
At least one of formed.
In the corresponding attached drawing of the present embodiment, the size of each structure sheaf, thickness etc. shown in attached drawing are only to illustrate.In technique reality
In existing, the projected area of each structure sheaf on substrate be may be the same or different, needed for being realized by etching technics
Each structure sheaf projected area；Meanwhile structure shown in attached drawing does not limit the geometry of each structure sheaf yet, such as can be attached drawing institute
The rectangle shown can also be that trapezoidal or other etchings are formed by shape, can equally be realized by etching.
Embodiment 3:
The present embodiment provides a kind of array substrates, adopt and prepare to be formed with the aforedescribed process.
The array substrate of the present embodiment includes substrate, the insulating layer above substrate, and above insulating layer
Metal wire；It include wiring region at the position at at least partly edge of substrate, in wiring region, the insulating layer deviates from the face of substrate
With multiple spaced strip projected parts, the metal wire relies on the strip projected parts to be formed, so that between two protrusions
Metal wire is formed at position, makes the interval that metal wire is formed at the position of respective protrusions.The array substrate of the present embodiment it is adjacent
Metal wire between line situation will not occur.
Embodiment 4:
Present embodiments provide a kind of display panel comprising any one of the above array substrate.The array of display base
Plate can be with are as follows: liquid crystal display panel, Electronic Paper, mobile phone, tablet computer, television set, display, laptop, Digital Frame,
Any products or components having a display function such as navigator.
It is understood that the principle that embodiment of above is intended to be merely illustrative of the present and the exemplary implementation that uses
Mode, however the present invention is not limited thereto.For those skilled in the art, essence of the invention is not being departed from
In the case where mind and essence, various changes and modifications can be made therein, these variations and modifications are also considered as protection scope of the present invention.
Claims (10)
1. a kind of preparation method of array substrate, which is characterized in that including following preparation step:
Insulating layer is formed on the substrate, includes wiring region at the position at at least partly edge of the substrate；It is described in wiring region
Insulating layer has multiple spaced strip projected parts away from the face of substrate；
Metal layer is formed above the insulating layer for completing above-mentioned steps；
By the metal layer patterning of wiring region, so that at position between two protrusions of the correspondence of the metal layer and respective protrusions
To be in the light exposure that receives in patterning process different for position.
2. the preparation method of array substrate according to claim 1, which is characterized in that the face where perpendicular to the substrate
Direction on, the size range of the protrusion is 200-4000 Ethylmercurichlorendimide.
3. the preparation method of array substrate according to claim 1, which is characterized in that the formation insulating layer includes following
Preparation step:
Insulating coating is formed on the substrate using insulating materials；
Insulating coating is patterned using halftone exposure technique, obtains that there are multiple strips in the face away from substrate of wiring region
The insulating layer of protrusion.
4. the preparation method of array substrate according to claim 3, which is characterized in that the face where perpendicular to the substrate
Direction on, the size range of the insulating coating is 4200-8000 Ethylmercurichlorendimide.
5. the preparation method of array substrate according to claim 1, which is characterized in that correspondence two of the metal layer are convex
Metal wire is formed at position between rising, makes the interval that metal wire is formed at the position of the respective protrusions of the metal layer；It is adjacent
The spacing of two metal wires be 1-10 μm, the line width of the metal wire is 1-10 μm.
6. the preparation method of array substrate according to claim 1, which is characterized in that the metal layer figure by wiring region
Case is that mask plate is used to be exposed so that by the metal layer patterning of wiring region, the mask plate includes the exposure mask of multiple splicings
Item, two adjacent mask strips have overlap edge, and the strip projected parts are arranged in the position that the insulating layer corresponds to the overlap edge.
7. the preparation method of array substrate according to claim 6, which is characterized in that the respective protrusions of the metal layer
A plurality of spaced metal wire is formed at position, two adjacent raised spacing are 70-120 μm, the width of the protrusion
It is 5-40 μm.
8. according to the preparation method of array substrate described in claim 1, which is characterized in that the insulating layer is gate insulating layer,
The metal wire is data line, the method also includes:
Before forming gate insulating layer, in the step of viewing area forms grid；
Forming the step of forming active layer, pixel electrode between gate insulating layer and metal layer.
9. a kind of array substrate, which is characterized in that prepare to be formed using the described in any item methods of claim 1-8.
10. a kind of display panel, which is characterized in that including array substrate as claimed in claim 9.
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| CN201810972621.4A CN109103144B (en) | 2018-08-24 | 2018-08-24 | Array substrate, preparation method thereof and display panel |
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| CN201810972621.4A CN109103144B (en) | 2018-08-24 | 2018-08-24 | Array substrate, preparation method thereof and display panel |
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| CN109103144B CN109103144B (en) | 2021-08-27 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112164871A (en) * | 2020-09-28 | 2021-01-01 | 京东方科技集团股份有限公司 | Antenna, preparation method thereof and electronic device |
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