CN109103111B - Forming method of PMOS structure - Google Patents

Forming method of PMOS structure Download PDF

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CN109103111B
CN109103111B CN201811133099.7A CN201811133099A CN109103111B CN 109103111 B CN109103111 B CN 109103111B CN 201811133099 A CN201811133099 A CN 201811133099A CN 109103111 B CN109103111 B CN 109103111B
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type substrate
ion implantation
ions
implantation process
gate oxide
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CN109103111A (en
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刘星
黄炜
徐静静
周俊
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Wuhan Xinxin Integrated Circuit Co ltd
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

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  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Manufacturing & Machinery (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention relates to the technical field of semiconductors, in particular to a forming method of a PMOS structure, which comprises the following steps: step S1, providing an N-type substrate, wherein the upper surface of the N-type substrate is provided with a stacked gate oxide layer and a gate structure; step S2, lightly doping the exposed upper surface of the N-type substrate by a first ion implantation process to form a lightly doped source/drain structure in the N-type substrate; step S3, forming a side wall structure on the side wall of the grid structure; step S4, heavily doping the exposed upper surface of the N-type substrate by adopting a second ion implantation process to form a heavily doped source drain structure in the N-type substrate; wherein the first and second ion implantation processes form a total content of 1 x 10^14/cm in the N-type substrate2～2*10^15/cm2The fluoride ion of (a); the phenomenon that boron ions penetrate through the gate oxide can be improved, the quality of the gate oxide is improved, and meanwhile, the negative bias instability of a PMOS structure is inhibited.

Description

Forming method of PMOS structure
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for forming a PMOS structure.
Background
Metal-Oxide-Semiconductor Field Effect transistors (MOSFETs) can be divided into two categories, namely N-channel and P-channel, a P-channel silicon MOSFET has two P + regions on an N-type silicon substrate, which are called a source and a drain, respectively, no conduction is established between the two electrodes, and when sufficient positive voltage is applied to the source, the N-type silicon surface under the gate presents a P-type inversion layer, which becomes a channel connecting the source and the drain. Changing the gate voltage changes the hole density in the channel and thus changes the resistance of the channel. Such MOSFETs are known as P-channel enhancement mode field effect transistors. If the P-type inversion layer channel exists on the surface of the N-type silicon substrate without applying a grid voltage, the resistance of the channel can be increased or reduced by applying proper bias voltage. Such MOSFETs are known as P-channel depletion mode field effect transistors.
For a P-type MOSFET applied under a low voltage condition, when fluorine ions and boron ions are implanted to form shallow doped source and drain, the implantation amount of the fluorine ions and the boron ions is not proper, and silicon-hydrogen bonds which easily cause unstable negative bias of a device can be formed in a wafer. Moreover, the variation of the implantation amount of fluorine ions may cause boron ion punch-through phenomenon because fluorine ions may promote the diffusion of boron ions, resulting in that a part of boron ions enter into the gate oxide layer, causing deterioration of the quality of the gate oxide layer, and a dielectric breakdown voltage is lowered, thereby resulting in a reduction of device reliability.
Disclosure of Invention
In order to solve the above problem, the present invention provides a method for forming a PMOS structure, wherein the method comprises:
step S1, providing an N-type substrate, wherein the upper surface of the N-type substrate is provided with a stacked gate oxide layer and a gate structure;
step S2, lightly doping the exposed upper surface of the N-type substrate by using a first ion implantation process to form a lightly doped source/drain structure in the N-type substrate;
step S3, forming a side wall structure on the side wall of the grid structure;
step 4, heavily doping the exposed upper surface of the N-type substrate by adopting a second ion implantation process to form a heavily doped source-drain structure in the N-type substrate;
wherein the first and second ion implantation processes form a total content of 1 x 10^14/cm in the N-type substrate2～2*10^15/cm2The fluoride ion of (2).
In the above formation method, in step S2, the ion species implanted by the first ion implantation process are boron difluoride ions and boron ions.
The above forming method, wherein the implantation amount of the boron difluoride ions is 5 x 10^13/cm2～5*10^14/cm2(ii) a The implantation amount of the boron ions is 0/cm2～5*10^14/cm2。
In the above formation method, in step S4, the ion species implanted by the second ion implantation process are boron difluoride ions and fluorine ions.
In the above formation method, the implantation amount of the boron difluoride ions is 0/cm2～5*10^14/cm2(ii) a The injection amount of the fluorine ions is 5 x 10^13/cm2～1.0*10^15/cm2。
In the above formation method, in step S1, the gate oxide layer is formed to have a thickness of 20A to 80A.
In the above formation method, in step S1, the gate oxide layer is formed using silicon dioxide.
In the above forming method, in step S1, the N-type substrate is formed by using an N-type doped silicon substrate.
In the above forming method, in step S1, the gate structure is formed by using a polysilicon material.
Has the advantages that: the forming method of the PMOS structure can improve the phenomenon that boron ions penetrate through a gate oxide layer, improve the quality of the gate oxide layer and inhibit the negative bias instability of the PMOS structure.
Drawings
FIG. 1 is a flow chart illustrating steps in a method for forming a PMOS structure according to an embodiment of the present invention;
FIGS. 2-5 are schematic structural diagrams illustrating steps of a method for forming a PMOS structure according to an embodiment of the present invention.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
In a preferred embodiment, as shown in fig. 1, a method for forming a PMOS structure is provided, and the formed PMOS structure can be as shown in fig. 2 to 5, wherein the method for forming the PMOS structure can include:
step S1, providing an N-type substrate 10, where an active area AA and a peripheral edge area EG surrounding the active area AA can be defined on the N-type substrate 10, and the upper surface of the N-type substrate 10 in the active area AA is prepared with a stacked gate oxide layer 20 and a gate structure 30;
step S2, lightly doping the exposed upper surface of the N-type substrate 10 in the active area AA by using a first ion implantation process to form a lightly doped source/drain structure 50 in the N-type substrate 10;
step S3, forming a sidewall structure 60 on the sidewall of the gate structure 30;
step S4, heavily doping the exposed upper surface of the N-type substrate 10 in the active region by using a second ion implantation process to form a heavily doped source/drain structure 51 in the N-type substrate 10;
wherein the first ion implantation process and the second ion implantation process form a total content of 1 x 10^14/cm in the N-type substrate 102～2*10^15/cm2The fluoride ion of (2).
In the above technical solution, the formed PMOS structure may be used for low voltage condition; through multiple tests, the content of fluorine ions is 1 x 10^14/cm in the integrity test process of the gate oxide layer2～2*10^15/cm2In time, the waveform generated by the voltage test can meet the test requirement; typically, it may be, for example, 2 x 10 x 14/cm2Or 4 x 10^14/cm2Or 6 x 10^14/cm2Or 8 x 10^14/cm2Or 1 x 10^15/cm2Etc.; the generation of silicon-hydrogen bonds in the wafer forming the PMOS structure can be inhibited to a certain extent by controlling the injection amount of fluorine ions, so that the instability of negative bias voltage is inhibited; as shown in fig. 5, the sidewall structure 60 may form a certain blocking effect during the second ion implantation process, so that a low concentration region is formed in the channel at the blocking position near the source/drain, and the low concentration region also bears a part of voltage, thereby effectively reducing the hot carrier effect; the upper surface of the N-type substrate may be sequentially stacked with a gate oxide layer 20 and a gate structure 30; the PMOS structures formed may be arrayed, and isolation structures 15 for isolating the PMOS structures may be formed in the N-type substrate 10.
In the above technical solution, the heavily doped source/drain structure 51 may include a heavily doped source structure and a heavily doped drain structure, and the formed PMOS structure may further include other conventional structures and regions, such as an edge structure formed in an edge region EG, which is a conventional technical means in the art and is not described herein again.
In a preferred embodiment, in step S2, the ion species implanted by the first ion implantation process may be boron difluoride (BF) ion2 +) And boron ion (B)+)。
In the above technical solution, after the boron difluoride ions are implanted in the first ion implantation process, the total content of the fluorine ions formed in the N-type substrate 10 also includes the fluorine ions in the boron difluoride ions implanted in the first ion implantation process.
In the above embodiment, preferably, the implantation amount of the boron difluoride ions is 5 x 10^13/cm2～5*10^14/cm2For example, it may be 1 x 10^14/cm2Or 2 x 10^14/cm2Or 3 x 10^14/cm2Or 4 x 10^14/cm2Etc.; the implantation amount of fluorine ions was 0/cm2～5*10^14/cm2For example, it may be 0.2 x 10 x 14/cm2Or 0.5 x 10^14/cm2Or 1 x 10^14/cm2Or 1.2 x 10^14/cm2Or 2 x 10^14/cm2Or 3 x 10^14/cm2And the like.
In a preferred embodiment, in step S4, the ion species implanted by the second ion implantation process is boron difluoride (BF) ion2 +) And fluorine ion (F)+)。
In the above technical solution, after the boron difluoride ions are implanted in the second ion implantation process, the total content of the fluorine ions formed in the N-type substrate 10 also includes the fluorine ions in the boron difluoride ions implanted in the second ion implantation process.
In the above embodiment, preferably, the implantation amount of boron difluoride ions is 0/cm2～5*10^14/cm2For example, it may be 1 x 10^14/cm2Or 2 x 10^14/cm2Or 3 x 10^14/cm2Or 4 x 10^14/cm2Etc.; the injection amount of fluorine ions is 5 x 10^13/cm2～1.0*10^15/cm2For example, it may be 8 x 10^13/cm2Or 1 x 10^14/cm2Or 3 x 10^14/cm2Or 4 x 10^14/cm2Or 7 x 10^14/cm2Or 9 x 10^14/cm2And the like.
In a preferred embodiment, in step S1, the gate oxide layer 20 is formed to a thickness of 20A to 80A, for example, 30A, 40A, 50A, 60A, 70A, etc.
In a preferred embodiment, in step S2, an ion implantation tool may be used to complete the first ion implantation process.
In a preferred embodiment, in step S1, gate oxide layer 20 may be formed using silicon dioxide.
In a preferred embodiment, in step S1, the N-type substrate 10 may be formed by using an N-type doped silicon substrate, and in other cases, the N-type substrate 10 may also be formed by using other materials.
In a preferred embodiment, in step S1, the gate structure 30 may be formed by using a polysilicon material.
In summary, in the method for forming a PMOS structure provided by the present invention, the first ion implantation process employs boron ions and fluorine ions for implantation, so as to control the content of fluorine ions in the implanted N-type substrate to 10^14/cm2～2*10^15/cm2The method can inhibit the generation of silicon-hydrogen bonds in the wafer forming the PMOS structure to a certain extent, thereby inhibiting the negative bias instability of the formed device, and simultaneously avoiding the excessive diffusion of boron ions into the gate oxide layer caused by fluorine ions, thereby ensuring the insulation effect of the gate oxide layer.
While the specification concludes with claims defining exemplary embodiments of particular structures for practicing the invention, it is believed that other modifications will be made in the spirit of the invention. While the above invention sets forth presently preferred embodiments, these are not intended as limitations.
Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. Therefore, the appended claims should be construed to cover all such variations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to be within the intent and scope of the present invention.

Claims (7)

1. A method for forming a PMOS structure, comprising:
step S1, providing an N-type substrate, wherein the upper surface of the N-type substrate is provided with a stacked gate oxide layer and a gate structure;
step S2, lightly doping the exposed upper surface of the N-type substrate by using a first ion implantation process to form a lightly doped source/drain structure in the N-type substrate;
step S3, forming a side wall structure on the side wall of the grid structure;
step S4, heavily doping the exposed upper surface of the N-type substrate by using a second ion implantation process to form a heavily doped source/drain structure in the N-type substrate;
wherein the first and second ion implantation processes form a total content of 1 x 10^14/cm in the N-type substrate2~2*10^15/cm2The fluoride ion of (a); in step S2, the ion species implanted by the first ion implantation process are boron difluoride ions and boron ions;
in step S4, the ion species implanted by the second ion implantation process are boron difluoride ions and fluorine ions.
2. The method of claim 1, wherein in the step S2, the implantation amount of the boron difluoride ions implanted by the first ion implantation process is 5 x 10^13/cm2~5*10^14/cm2(ii) a The implantation amount of the boron ions is 0/cm2~5*10^14/cm2。
3. The method of claim 1, wherein in the step S4, the implantation amount of the boron difluoride ions implanted by the second ion implantation process is 0/cm2~5*10^14/cm2(ii) a The injection amount of the fluorine ions is 5 x 10^13/cm2~1.0*10^15/cm2。
4. The method of forming of claim 1, wherein the thickness of the gate oxide layer formed by preparation in step S1 is 20A-80A.
5. The method of claim 1, wherein said gate oxide layer is formed using silicon dioxide in step S1.
6. The forming method of claim 1, wherein in the step S1, the N-type substrate is formed by using an N-type doped silicon substrate.
7. The method as claimed in claim 1, wherein in step S1, the gate structure is formed by using polysilicon material.
CN201811133099.7A 2018-09-27 2018-09-27 Forming method of PMOS structure Active CN109103111B (en)

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JPH08335560A (en) * 1995-06-08 1996-12-17 Sanyo Electric Co Ltd Manufacture of semiconductor device
CN101286527A (en) * 2007-04-12 2008-10-15 上海宏力半导体制造有限公司 PMOS structure with dual ion implantation and method therefor
CN101572250A (en) * 2008-04-30 2009-11-04 中芯国际集成电路制造(北京)有限公司 Semiconductor device, p-type MOS transistor and manufacturing method thereof
CN102024701A (en) * 2009-09-09 2011-04-20 中芯国际集成电路制造(上海)有限公司 P-channel metal oxide semiconductor transistor source-drain injection method
CN102097319A (en) * 2009-12-15 2011-06-15 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device
CN102487007A (en) * 2010-12-01 2012-06-06 中芯国际集成电路制造(北京)有限公司 Method for forming semiconductor device
CN103972102A (en) * 2014-04-22 2014-08-06 上海华力微电子有限公司 Ultra-shallow junction forming method and semiconductor device forming method
CN103972108A (en) * 2014-05-20 2014-08-06 上海华力微电子有限公司 Ion implantation method for source drain region of PMOS and preparation method of PMOS
CN104241106A (en) * 2014-09-02 2014-12-24 上海华力微电子有限公司 PMOS source and drain region ion implantation method and PMOS device manufacturing method

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JP2002184984A (en) * 2000-10-26 2002-06-28 Hynix Semiconductor Inc Manufacturing method of semiconductor device
CN103295913B (en) * 2013-06-04 2016-01-27 上海华力微电子有限公司 Improve the method for semiconductor device Negative Bias Temperature Instability

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08335560A (en) * 1995-06-08 1996-12-17 Sanyo Electric Co Ltd Manufacture of semiconductor device
CN101286527A (en) * 2007-04-12 2008-10-15 上海宏力半导体制造有限公司 PMOS structure with dual ion implantation and method therefor
CN101572250A (en) * 2008-04-30 2009-11-04 中芯国际集成电路制造(北京)有限公司 Semiconductor device, p-type MOS transistor and manufacturing method thereof
CN102024701A (en) * 2009-09-09 2011-04-20 中芯国际集成电路制造(上海)有限公司 P-channel metal oxide semiconductor transistor source-drain injection method
CN102097319A (en) * 2009-12-15 2011-06-15 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device
CN102487007A (en) * 2010-12-01 2012-06-06 中芯国际集成电路制造(北京)有限公司 Method for forming semiconductor device
CN103972102A (en) * 2014-04-22 2014-08-06 上海华力微电子有限公司 Ultra-shallow junction forming method and semiconductor device forming method
CN103972108A (en) * 2014-05-20 2014-08-06 上海华力微电子有限公司 Ion implantation method for source drain region of PMOS and preparation method of PMOS
CN104241106A (en) * 2014-09-02 2014-12-24 上海华力微电子有限公司 PMOS source and drain region ion implantation method and PMOS device manufacturing method

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