CN109087901A - Storage device, semiconductor devices and its manufacturing method - Google Patents
Storage device, semiconductor devices and its manufacturing method Download PDFInfo
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- CN109087901A CN109087901A CN201811015658.4A CN201811015658A CN109087901A CN 109087901 A CN109087901 A CN 109087901A CN 201811015658 A CN201811015658 A CN 201811015658A CN 109087901 A CN109087901 A CN 109087901A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/0805—Shape
- H01L2224/08057—Shape in side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/08112—Disposition the bonding area being at least partially embedded in the surface of the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/822—Applying energy for connecting
Abstract
The disclosure provides the manufacturing method of a kind of storage device, semiconductor devices and semiconductor devices, the manufacturing method includes: to provide the first chip and multiple second chips, first chip has the first pad, and each second chip has the second pad, and each second pad is equipped with perforation；Each second chip stacking is set to the first chip, each second pad and the first pad face are arranged；In two second chips of arbitrary neighborhood, the perforation close to the first chip is no more than the perforation far from the first chip；The connecting hole across each perforation is formed, connecting hole exposes the first pad, and connecting hole includes multiple hole sections, and each hole section is located at correspondingly in each second chip, and hole section is identical as the size of perforation of the second pad of the second chip where it；Electric conductor is formed in connecting hole, the first pad and each second pad are connect with electric conductor.The manufacturing method of the disclosure can simplify technique, reduce cost.
Description
Technical field
This disclosure relates to technical field of semiconductors, in particular to a kind of storage device, semiconductor devices and semiconductor
The manufacturing method of device.
Background technique
With the development of semiconductor technology, chip Stack Technology has been widely used in various types of memory, such as DRAM
(Dynamic Random Access Memory, dynamic random access memory) etc..Currently, for the multiple cores for stacking setting
It for piece, needs to connect each chip with shortest path by TSV (Through Silicon Vias, silicon perforation), have
For body, in the prior art, it is generally required that first forming silicon channel on each chip, and conduct piece is formed in silicon channel,
Each chip is stacked again and is arranged, connects the conduct piece in each silicon channel, so that each chip be connected.
But TSV technique is carried out to each chip, and entire manufacturing process can be made to take a long time, process is more, and at
This is higher.
It should be noted that information is only used for reinforcing the reason to the background of the disclosure disclosed in above-mentioned background technology part
Solution, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Summary of the invention
A kind of manufacturing method for being designed to provide storage device, semiconductor devices and semiconductor devices of the disclosure, can
Simplify technique, reduces cost.
According to one aspect of the disclosure, a kind of manufacturing method of semiconductor devices is provided, comprising:
The first chip and multiple second chips are provided, first chip has the first pad, each second chip
The second pad is all had, each second pad is equipped with perforation；
Each second chip stacking is set to first chip, and each second pad and first pad
Face setting；In second chip of the two of arbitrary neighborhood, the perforation close to first chip is not more than far from described first
The perforation of chip；
The connecting hole across each perforation for being right against first pad is formed, the connecting hole exposes described first
Pad, and the connecting hole includes multiple hole sections, each hole section is located at correspondingly in each second chip, the hole
The size of the perforation of second pad of the second chip where Duan Yuqi is identical；
Electric conductor is formed in the connecting hole, first pad and each second pad connect with the electric conductor
It connects.
In a kind of exemplary embodiment of the disclosure, the connecting hole is formed by a hole opening technology.
In a kind of exemplary embodiment of the disclosure, the connecting hole formed across each second pad includes:
Photoresist layer is covered on second chip farthest apart from first chip；
The photoresist layer is exposed and is developed, the second pad of the second chip of the photoresist layer covering is exposed
Perforation；
To first bond-pad etch in the perforation that the photoresist layer exposes, until exposing first pad；
Remove the photoresist layer.
In a kind of exemplary embodiment of the disclosure, the of different sizes of the perforation of different second pads is adhered to separately,
Electric conductor is formed in the connecting hole includes:
Separation layer is formed in the connecting hole inner wall, the separation layer exposes first pad and second pad is remote
Surface from first chip；
The electric conductor is formed in the separation layer, the electric conductor and each second pad be not by the separation layer
The region of covering connects.
In a kind of exemplary embodiment of the disclosure, forming separation layer in the connecting hole inner wall includes:
Spacer material layer is formed in the connecting hole, the spacer material layer covers first pad and described second
Pad is located at the region in connecting hole；
Remove the surface of spacer material layer and second pad far from first chip on first pad
On spacer material layer.
In a kind of exemplary embodiment of the disclosure, the electric conductor is formed in the separation layer includes:
Conductive layer is covered on the second chip farthest apart from first chip, the conductive layer fills the connection
Hole；
Remove the region that the conductive layer is located at other than the connecting hole.
In a kind of exemplary embodiment of the disclosure, it is right against center and the institute of each perforation of first pad
The center for stating the first pad is collinearly arranged.
In a kind of exemplary embodiment of the disclosure, the material of first pad and second pad is metal.
In a kind of exemplary embodiment of the disclosure, the material of first pad is any, institute in copper, aluminium and tungsten
It is any in copper, aluminium and tungsten for stating the material of the second pad.
In a kind of exemplary embodiment of the disclosure, first chip includes:
First substrate；
First insulating layer, is set to first substrate, and first pad is embedded at first insulating layer far from described
The surface of first substrate；
Second chip includes:
Second substrate；
Second insulating layer, the side set on second substrate far from first chip, second pad are embedded at
Surface of the second insulating layer far from second substrate；
Second substrate of second chip nearest apart from first chip is set to first insulating layer far from described the
The surface of one substrate, the second substrate of each second chip and the alternately laminated setting of second insulating layer.
According to one aspect of the disclosure, a kind of semiconductor devices is provided, comprising:
First chip has the first pad；
Multiple second chips, each second chip all have the second pad, and each second pad is equipped with perforation；
Each second chip stacking is set to first chip, and each second pad and first pad are just
To setting；In second chip of the two of arbitrary neighborhood, the perforation close to first chip is not more than far from first core
The perforation of piece；
Connecting hole across each perforation for being right against first pad and exposes first pad, the connection
Hole includes multiple hole sections, and each hole section is located at correspondingly in each second chip, the hole section and where it the
The size of the perforation of second pad of two chips is identical；
Electric conductor, cooperation are set in the connecting hole, first pad and each second pad with the conduction
Body connection.
In a kind of exemplary embodiment of the disclosure, of different sizes, the institute of the perforation of different second pads is adhered to separately
State semiconductor devices further include:
Separation layer is set between the connecting hole inner wall and the electric conductor, and the separation layer exposes first weldering
The surface of disk and second pad far from first chip.
In a kind of exemplary embodiment of the disclosure, it is right against center and the institute of each perforation of first pad
The center for stating the first pad is collinearly arranged.
In a kind of exemplary embodiment of the disclosure, the material of first pad and second pad is metal.
In a kind of exemplary embodiment of the disclosure, the material of first pad is any, institute in copper, aluminium and tungsten
It is any in copper, aluminium and tungsten for stating the material of the second pad.
In a kind of exemplary embodiment of the disclosure, first chip includes:
First substrate；
First insulating layer is set to first one side of substrate, and it is separate that first pad is embedded at first insulating layer
The surface of first substrate；
Second chip includes:
Second substrate；
Second insulating layer, the side set on second substrate far from first chip, second pad are embedded at
Surface of the second insulating layer far from second substrate；
Second substrate of second chip nearest apart from first chip is set to first insulating layer far from described the
The surface of one substrate, the second substrate of each second chip and the alternately laminated setting of second insulating layer.
According to one aspect of the disclosure, a kind of storage device is provided, including semiconductor device described in above-mentioned any one
Part.
Multiple second chips can be stacked first and are arranged in the first chip, then edge by the method, semi-conductor device manufacturing method of the disclosure
The connecting hole for exposing the first pad 11 is formed close to the direction of the first chip, then by electric conductor by each second chip and the
One chip connects.Compared to the scheme of existing each chip difference aperture, the number of hole opening technology can be reduced, to make whole
A manufacturing process is simplified, and time-consuming is also minimized, and advantageously reduces manufacturing cost.
The storage device and semiconductor devices of the disclosure, due in two second chips of arbitrary neighborhood, close to the first chip
Perforation no more than far from the first chip perforation, thus, during fabrication, can first will multiple second chips stack setting first
Chip, then the connecting hole for exposing the first pad is formed along the direction close to the first chip, the first core is then connected by electric conductor
Piece and each second chip can avoid distinguishing aperture to each second chip, advantageously reduce the number of hole opening technology, make entire
Manufacturing process is simplified, and is reduced time-consuming, is reduced manufacturing cost.
It should be understood that above general description and following detailed description be only it is exemplary and explanatory, not
The disclosure can be limited.
Detailed description of the invention
The drawings herein are incorporated into the specification and forms part of this specification, and shows the implementation for meeting the disclosure
Example, and together with specification for explaining the principles of this disclosure.It should be evident that the accompanying drawings in the following description is only the disclosure
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 is the flow chart of the manufacturing method of disclosure embodiment semiconductor devices.
Fig. 2 is the schematic diagram of the first chip in the manufacturing method of disclosure embodiment semiconductor devices.
Fig. 3 is the schematic diagram of the first pad of the first chip in the manufacturing method of disclosure embodiment semiconductor devices.
Fig. 4 is the schematic diagram of the second chip in the manufacturing method of disclosure embodiment semiconductor devices.
Fig. 5 is the schematic diagram of the second pad of the second chip in the manufacturing method of disclosure embodiment semiconductor devices.
Fig. 6 is that the schematic diagram after step S120 is completed in the manufacturing method of disclosure embodiment semiconductor devices.
Fig. 7 is the flow chart of the step S130 of the manufacturing method of disclosure embodiment semiconductor devices.
Fig. 8 is that the schematic diagram after step S1320 is completed in the manufacturing method of disclosure embodiment semiconductor devices.
Fig. 9 is that the schematic diagram after step S1340 is completed in the manufacturing method of disclosure embodiment semiconductor devices.
Figure 10 is the flow chart of the step S140 of the manufacturing method of disclosure embodiment semiconductor devices.
Figure 11 is the flow chart of the step S1410 of the manufacturing method of disclosure embodiment semiconductor devices.
Figure 12 is that the schematic diagram after step S14110 is completed in the manufacturing method of disclosure embodiment semiconductor devices.
Figure 13 is that the schematic diagram after step S14120 is completed in the manufacturing method of disclosure embodiment semiconductor devices.
Figure 14 is the flow chart of the step S1420 of the manufacturing method of disclosure embodiment semiconductor devices.
Figure 15 is that the schematic diagram after step S14210 is completed in the manufacturing method of disclosure embodiment semiconductor devices.
Figure 16 is the schematic diagram of disclosure embodiment semiconductor devices.
In figure: 1, the first chip；11, the first pad；12, the first substrate；13, the first insulating layer；2, the second chip；21,
Second pad；211, it perforates；22, the second substrate；23, second insulating layer；3, connecting hole；4, electric conductor；5, separation layer；100, light
Photoresist layer；200, conductive layer.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to embodiment set forth herein；On the contrary, thesing embodiments are provided so that the present invention will
Fully and completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Identical attached drawing in figure
Label indicates same or similar structure, thus the detailed description that will omit them.
Although the term of relativity, such as "upper" "lower" is used to describe a component of icon for another in this specification
The relativeness of one component, but these terms are in this manual merely for convenient, for example, with reference to the accompanying drawings described in show
The direction of example.It is appreciated that, if making it turn upside down the device overturning of icon, the component described in "upper" will
As the component in "lower".When certain structure is at other structures "upper", it is possible to refer to that certain structural integrity is formed in other structures
On, or refer to that certain structure is " direct " and be arranged in other structures, or refer to that certain structure is arranged by the way that another structure is " indirect " in other knots
On structure.
Term "one", " one ", "the" and " described " to indicate there are one or more elements/component part/etc.；With
Language " comprising " and " having " is to indicate the open meaning being included and refer to element/composition portion in addition to listing
Also may be present except divide/waiting other element/component part/etc.；Term " first ", " second " only use as label, are not
Quantity limitation to its object.
Disclosure embodiment provides a kind of manufacturing method of semiconductor devices, can be used for manufacturing semiconductor devices, should
Semiconductor devices can be stacked chips, such as DRAM etc. will not enumerate herein.
As shown in Figure 1, the manufacturing method of disclosure embodiment may include:
Step S110, the first chip and multiple second chips are provided, first chip has the first pad, each described
Second chip all has the second pad, and each second pad is equipped with perforation, and the perforation of each second pad is at least wrapped
Include two kinds of perforation of different sizes；
Step S120, each second chip stacking is set to first chip, and each second pad and institute
State the setting of the first pad face；In second chip of the two of arbitrary neighborhood, the perforation close to first chip is no more than remote
Perforation from first chip；
Step S130, the connecting hole across each perforation is formed, the connecting hole exposes first pad, and described
Connecting hole includes multiple hole sections, and each hole section is located at correspondingly in each second chip, the hole section and its place
The second chip the second pad perforation size it is identical；
Step S140, electric conductor is formed in the connecting hole, first pad and each second pad are and institute
State electric conductor connection.
Multiple second chips can be stacked first and are arranged in the first chip, then edge by the method, semi-conductor device manufacturing method of the disclosure
The connecting hole for exposing the first pad is formed close to the direction of the first chip, then by electric conductor by each second chip and first
Chip connects, and compared to the scheme of existing each chip difference aperture, the number of hole opening technology can be reduced, to make entire
Manufacturing process is simplified, and time-consuming is also minimized, and advantageously reduces manufacturing cost.
Each step of disclosure embodiment manufacturing method is described in detail below:
As Figure 2-Figure 5, in step s 110, the first chip 1 and the second chip 2 are provided, the quantity of the first chip 1 can
To be one, and there is the first pad 11, which can be with the circuit connection on the first chip 1.
For example, as shown in Figures 2 and 3, the first chip 1 may include the first pad 11, the first substrate 12 and first
Insulating layer 13, in which:
The material of first substrate 12 can be silicon or other semiconductor materials, shape and size do not do particular determination herein.
First insulating layer 13 can be set to the first substrate 12, and its material can be silicon oxide or silicon nitride etc., be also possible to
The mixture of a variety of insulating materials.
First pad 11 can be set to surface of first insulating layer 13 far from the first substrate 12, and the first pad 11 embeddable the
In one insulating layer 13, and the flush with the first insulating layer 13 far from the first substrate 12.Meanwhile first the material of pad 11 can
To be that metal, such as copper, aluminium or tungsten etc. will not enumerate it is of course also possible to be other metal materials herein.First pad
11 shape can be rectangle, it is of course also possible to be round or other shapes.In addition, the quantity of the first pad 11 can be one
It is a or multiple.
The quantity of second chip 2 can be multiple, and each second chip 2 all has the second pad 21, each second weldering
Disk 21 is equipped with perforation 211.
For example, as shown in Figure 4 and Figure 5, the second chip 2 may include the second pad 21, the second substrate 22 and second
Insulating layer 23, in which:
The structure and material of second substrate 22 can be identical as the first substrate 12.
Second insulating layer 23 can be set to 22 side of the second substrate, and the material of second insulating layer 23 can be with 13 phase of the first insulating layer
Together.
Second pad 21 can be set to surface of the second insulating layer 23 far from the second substrate 22, and the second pad 21 embeddable the
In two insulating layers 23, and the flush with second insulating layer 23 far from the second substrate 22.Meanwhile second the material of pad 21 can
To be metal, such as copper, aluminium or tungsten will not enumerate herein it is of course also possible to be other metal materials.Second pad 21
Shape can be rectangle, circle or other shapes.
The quantity of second pad 21 of each second chip 2 can be identical as the quantity of the first pad 11 of the first chip 1.Often
A perforation 211 can be equipped on a second pad 21,211 shape of perforating can be round, rectangle or other shapes.
Meanwhile perforate 211 size can at least two specifications, if but have on same second chip 2 it is multiple perforation 211,
The size of each perforation 211 on second chip 2 is identical, for example, adhering to the of different sizes of the perforation 211 of different second chips 2 separately.
In addition, the thickness of each second pad 21 can be identical as the thickness of the first pad 11.
As shown in fig. 6, in the step s 120, each second chip 2 stacking is set to the first chip 1, and each second pad
21 and 11 face of the first pad be arranged；In two second chips 2 of arbitrary neighborhood, the perforation 211 close to the first chip 1 is no more than remote
Perforation 211 from the first chip 1.
One second chip 2 can be set on the first chip 1, then successively be folded on second chip 2 and set other second chips
2, form stacked structure.Meanwhile during stacking gradually, adjacent the first chip 1 and the second chip 2 can be bonded, phase
Adjacent the second chip 2 bonding.For example, each second insulating layer 23 and the second substrate 22 are alternately laminated in the first insulating layer 13
Surface far from the first substrate 12, the second substrate 22 of the second nearest chip 2 of the first chip of distance 1 and the first insulating layer 13 are remote
Surface bond from the first substrate 12；In adjacent two second chip 2, the second insulating layer 23 of the second chip 2 of lower layer and upper layer
The second chip 2 the second substrate 22 bonding.
In each chip of heap poststack, each second pad 21 and 11 face of the first pad are arranged, i.e., each second pad 21
With the first pad 11 along the lineal layout perpendicular to the first substrate 12.And be right against each perforation 211 of same first pad 11
Center and the center of the first pad 11 are collinearly arranged.If having multiple second pads 21, the first chip 1 on each second chip 2
With multiple first pads 11, have for any first pad 11 of the first chip 1, on each second chip 2 unique
The second pad 21 and its face, correspondingly, also having unique perforation 211 and its face.
For example, the first pad 11 is identical with the shape and size of the second pad 21, and the perforation of each second pad 21
Straight line of 211 center with the center of the first pad 11 along vertical first substrate 12 is collinearly arranged.
In each chip of heap poststack, in two second chips 2 of arbitrary neighborhood, close to the second chip 2 of the first chip 1
Perforation 211 be not more than far from the first chip 1 the second chip 2 perforation 211.For example, the perforation of each second chip 2
211 be circular hole, and the diameter for adhering to the perforation 211 of different second chips 2 separately is not identical, and the diameter of each perforation 211 is along separate
The direction of first chip 1 is gradually increased.It, can be according to the sequence that perforation 211 is gradually increased heap one by one when stacking the second chip 2
It is folded.
As shown in Figure 1, in step s 130, forming the connecting hole 3 across each perforation 211, connecting hole 3 can expose the first weldering
Disk 11, and connecting hole 3 may include multiple hole sections, each hole section is located at correspondingly in each second chip 2, hole section and its where
The aperture of the perforation 211 of second pad 21 of the second chip 2 is identical.
Connecting hole 3 can be formed by a hole opening technology, such as be formed by an etching technics.Certainly, connecting hole 3
Can be by multiple hole opening technology, but the number of hole opening technology can be less than the quantity of the second chip 2, thus compared to the prior art
In for the mode of each chip aperture, can reduce aperture number, simplify technique.
For example, as shown in fig. 7, step S130 may include S1310- step S1340, in which:
In step S1310, photoresist layer 100 is covered on the second farthest chip 2 of the first chip of distance 1.
The photoresist layer 100 can be positive photoresist or negative photoresist, not do particular determination herein.
As shown in figure 8, photoresist layer 100 is exposed and is developed in step S1320, exposes photoresist layer 100 and cover
The perforation 211 of second pad 21 of the second chip 2 of lid.
Photoresist layer 100 can be exposed by mask plate, and developed, at least exposing photoresist layer 100 cover the
The perforation 211 of two pads 21, that is, expose the perforation of the second pad 21 of the second farthest chip 2 of the first chip of distance 1
211.Certainly, entire second pad 21 of second chip 2 can also be exposed.
It in step S1330, is etched in the perforation 211 that photoresist layer 100 exposes to the first pad 11, until exposing the
One pad 11.
It can be performed etching by the perforation 211 that dry etching exposes photoresist layer 100, the region of etching is gradually worn to this
First pad 11 of 211 face of hole extends, until exposing first pad 11, wears to be formed by once etching across each
The material of the connecting hole 3 in hole 211, the first pad 11 and the second pad 21 can be copper, and when carrying out dry etching, copper will not be gone
It removes, and only etches the material in perforation 211.It is of course also possible to use other etching modes, as long as above-mentioned connecting hole can be formed
3, it will not enumerate herein.
The connecting hole 3 that etching is formed may include multiple hole sections, and each hole section is located at correspondingly in each second chip 2, and
Each hole section is identical as the aperture of perforation 211 of the second pad 21 of the second chip 2 where it.If adhering to different second chips separately
2 perforation 211 is of different sizes, and is sequentially reduced to the first chip 1, correspondingly, the diameter of each hole section is also different, and to dew
The first pad 11 out is sequentially reduced, i.e. radial first pad 11 in the hole of connecting hole 3 is gradually reduced.
As shown in figure 9, in step S1340, stripping photolithography glue-line 100.
Remaining photoresist layer 100 can be removed by stripper, light can also be removed by cineration technics or other techniques
Photoresist layer 100, does not do particular determination herein.
As shown in Figure 1, forming electric conductor 4, the first pad 11 and each second pad in connecting hole 3 in step S140
21 connect with electric conductor 4.
The material of electric conductor 4 can be metal, such as copper, aluminium or tungsten, it is of course also possible to be other metal materials, herein
It will not enumerate.In order to keep electric conductor 4 consistent with the electric conductivity of the first pad 11 and the second pad 21, electric conductor 4 and
Identical material can be used in one pad 11 and the second pad 21, such as is all made of copper.It can be by 11 He of the first pad by electric conductor 4
It is connected with each second pad 21 of its face, so that the first chip 1 and each second chip 2 be connected.
For example, as shown in Figure 10, step S140 may include step S1410 and step S1420, in which:
In step S1410, separation layer 5 is formed in 3 inner wall of connecting hole, separation layer 5 exposes the first pad 11 and the second weldering
Surface of the disk 21 far from the first chip 1.
Separation layer 5 can be silica, silicon nitride or other insulating materials with single layer structure, material.Certainly, separation layer 5
It is also possible to multilayered structure, for example, separation layer 5 may include insulation material layer and barrier layer, wherein insulation material layer is formed in company
Connect 3 inner wall of hole.Barrier layer can be formed in insulation material layer inner wall, electric conductor 4 can be stopped to external diffusion, to improve the electricity of chip
Reliability and stability.The material on barrier layer for example, the material of electric conductor 4 is copper, then can hinder depending on the material of electric conductor 4
The material of barrier can be titanium, tantalum, be also possible to other materials, as long as barrier effect can be played.
In one embodiment, separation layer 5 is single layer structure, adheres to the size of the perforation 211 of different second chips 2 not phase separately
Together, and along the direction far from the first chip 1 it is gradually increased, as shown in figure 11, step S1410 may include step S14110 and step
Rapid S14120, in which:
As shown in figure 12, in step S14110, spacer material layer is formed in connecting hole 3, spacer material layer covering the
One pad 11 and the second pad 21 are located at the region in connecting hole 3.
The material of spacer material layer can be silica, can be directly the second of the second farthest chip 2 of the first chip of distance 1
Depositing isolation material layer on insulating layer 23, the spacer material layer are fallen into connecting hole 3, and cover the first pad 11 and the second pad
21 are located at the region in connecting hole 3, are completely covered the inner wall of connecting hole 3.
As shown in figure 13, in step S14120, the spacer material layer and the second pad 21 on the first pad 11 are removed
Spacer material layer on surface far from the first chip 1.
The region on spacer material layer the first pad 11 of covering can be removed by etching liquid, thus at least exposed portion first
Pad 11, so that electric conductor 4 is connect with the first pad 11.Meanwhile it can remove surface of each second pad 21 far from the first chip 1
On spacer material layer, to expose surface of second pad 21 far from the first chip 1, in connecting hole 3 in order to electric conductor 4
It is connect with each second pad 21.
Certainly, in other embodiments, in two adjacent second chips 2, the second pad of second chip 2
21 perforation 211 can be identical as the perforation 211 of the second pad 21 of another the second chip 2, in the case, for the ease of that will lead
Electric body 4 is connect with this two the second pads 21, this two the second pads 21 can be made close to connecting hole by aperture or other means
The lateral opening hole of 3 central axes, so that electric conductor 4 is connect with second pad 21, the technique of aperture is not particularly limited herein.
As shown in Figure 10, in step S1420, electric conductor 4, electric conductor 4 and each second pad 21 are formed in separation layer 5
It is not isolated the region connection of the covering of layer 5.
Conductive material can be filled in separation layer 5, which covers the first pad 11 and each second pad 21 exposes
Region, to obtain electric conductor 4, the shape of electric conductor 4 and the shape of connecting hole 3 match.For example, such as Figure 14 institute
Show, step S1420 may include step S14210 and step S14220, in which:
As shown in figure 15, in step S14210, conductive layer is covered on the second farthest chip 2 of the first chip of distance 1
200, conductive layer 200 fills connecting hole 3.
The mode for forming conductive layer 200 can be sputtering or plating, and but not limited to this, be also possible to vapor deposition or other works
Skill does not do particular determination herein.The part that conductive layer 200 is filled in connecting hole 3 can cover the first pad 11 and each second
The region that pad 21 exposes, to be connected the first pad 11 and each second pad 21 by conductive layer 200.
As shown in figure 16, in step S14220, removal conductive layer 200 is located at the region other than connecting hole 3.
The region that conductive layer 200 is located at other than connecting hole 3 by chemically mechanical polishing or other techniques can be used to remove, connection
Region in hole 3 is electric conductor 4.
Disclosure embodiment also provides a kind of semiconductor devices, and as shown in figure 16, which may include
One chip 1, the second chip 2, connecting hole 3 and electric conductor 4, in which:
First chip 1 can have the first pad 11.
The quantity of second chip 2 be it is multiple, each second chip 2 all has the second pad 21, and each second pad 21 is all provided with
There is perforation 211.
Each stacking of second chip 2 is set to the first chip 1, and each second pad 21 and 11 face of the first pad are arranged；Appoint
It anticipates in two second adjacent chips 2, the perforation 211 close to the first chip 1 is not more than the perforation 211 far from the first chip 1.
Connecting hole 3 passes through each perforation 211 and exposes the first pad 11, and connecting hole 3 may include multiple hole sections, and each hole section is one by one
It is corresponding to be located in each second chip 2, the aperture phase of hole section and the perforation 211 of the second pad 21 of the second chip 2 where it
Together.
Electric conductor 4 can cooperate in connecting hole 3, and the first pad 11 and each second pad 21 are connect with electric conductor 4.
The semiconductor devices of disclosure embodiment can connect the first chip 1 and each by the electric conductor 4 in connecting hole 3
A second chip 2, since the perforation 211 close to the first chip 1 is not more than the perforation 211 far from the first chip 1, thus can be direct
The connecting hole 3 for exposing the first pad 11 is formed along the direction close to the first chip 1, to avoid distinguishing each second chip 2
Aperture advantageously reduces the number of hole opening technology, is simplified entire manufacturing process, reduces time-consuming, reduces manufacturing cost.
The semiconductor devices of disclosure embodiment can also include separation layer 5, and separation layer 5 can be set to 3 inner wall of connecting hole
Between electric conductor 4, and separation layer 5 exposes the surface of the first pad 11 and the second pad 21 far from the first chip 1, can stop to lead
Electric body 4 is to external diffusion, to improve the electrical reliability and stability of chip.
The details of each component of disclosure embodiment semiconductor devices, the corresponding manufacturing method the step of in into
Detailed description is gone, details are not described herein.
Disclosure embodiment also provides a kind of storage device, which may include partly leading for above embodiment
Body device.The storage device can be the memories such as DRAM, nand flash memory.
Those skilled in the art after considering the specification and implementing the invention disclosed here, will readily occur to its of the disclosure
Its embodiment.This application is intended to cover any variations, uses, or adaptations of the disclosure, these modifications, purposes or
Person's adaptive change follows the general principles of this disclosure and including the undocumented common knowledge in the art of the disclosure
Or conventional techniques.The description and examples are only to be considered as illustrative, and the true scope and spirit of the disclosure are by appended
Claim is pointed out.
Claims (17)
1. a kind of manufacturing method of semiconductor devices characterized by comprising
The first chip and multiple second chips are provided, first chip has the first pad, and each second chip has
There is the second pad, each second pad is equipped with perforation；
Each second chip stacking is set to first chip, and each second pad and the first pad face
Setting；In second chip of the two of arbitrary neighborhood, the perforation close to first chip is not more than far from first chip
Perforation；
The connecting hole across each perforation for being right against first pad is formed, the connecting hole exposes first weldering
Disk, and the connecting hole includes multiple hole sections, each hole section is located at correspondingly in each second chip, the hole section
It is identical as the size of perforation of the second pad of the second chip where it；
Electric conductor is formed in the connecting hole, first pad and each second pad are connect with the electric conductor.
2. the manufacturing method according to claim 1, which is characterized in that the connecting hole is formed by a hole opening technology.
3. manufacturing method according to claim 2, which is characterized in that form the connecting hole packet across each second pad
It includes:
Photoresist layer is covered on second chip farthest apart from first chip；
The photoresist layer is exposed and is developed, wearing for the second pad of the second chip of the photoresist layer covering is exposed
Hole；
To first bond-pad etch in the perforation that the photoresist layer exposes, until exposing first pad；
Remove the photoresist layer.
4. the manufacturing method according to claim 1, which is characterized in that adhere to the size of the perforation of different second pads separately
Difference, forming electric conductor in the connecting hole includes:
Separation layer is formed in the connecting hole inner wall, the separation layer exposes first pad and second pad far from institute
State the surface of the first chip；
The electric conductor is formed in the separation layer, the electric conductor is not covered by the separation layer with each second pad
Region connection.
5. manufacturing method according to claim 4, which is characterized in that forming separation layer in the connecting hole inner wall includes:
Spacer material layer is formed in the connecting hole, the spacer material layer covers first pad and second pad
Region in connecting hole；
It removes on the surface of spacer material layer and second pad far from first chip on first pad
Spacer material layer.
6. manufacturing method according to claim 4, which is characterized in that form the electric conductor packet in the separation layer
It includes:
Conductive layer is covered on the second chip farthest apart from first chip, the conductive layer fills the connecting hole；
Remove the region that the conductive layer is located at other than the connecting hole.
7. manufacturing method according to claim 1-6, which is characterized in that be right against each institute of first pad
The center at the center and first pad of stating perforation is collinearly arranged.
8. manufacturing method according to claim 1-6, which is characterized in that first pad and second weldering
The material of disk is metal.
9. manufacturing method according to claim 8, which is characterized in that the material of first pad is in copper, aluminium and tungsten
Any, the material of second pad is any in copper, aluminium and tungsten.
10. manufacturing method according to claim 1-6, which is characterized in that first chip includes:
First substrate；
First insulating layer, is set to first substrate, and first pad is embedded at first insulating layer far from described first
The surface of substrate；
Second chip includes:
Second substrate；
Second insulating layer, the side set on second substrate far from first chip, second pad are embedded at described
Surface of the second insulating layer far from second substrate；
Second substrate of second chip nearest apart from first chip is set to first insulating layer far from first lining
The surface at bottom, the second substrate of each second chip and the alternately laminated setting of second insulating layer.
11. a kind of semiconductor devices characterized by comprising
First chip has the first pad；
Multiple second chips, each second chip all have the second pad, and each second pad is equipped with perforation；
Each second chip stacking is set to first chip, and each second pad is set with the first pad face
It sets；In second chip of the two of arbitrary neighborhood, the perforation close to first chip is no more than separate first chip
Perforation；
Connecting hole across each perforation for being right against first pad and exposes first pad, the connecting hole packet
Multiple hole sections are included, each hole section is located at correspondingly in each second chip, the hole section and the second core where it
The size of the perforation of second pad of piece is identical；
Electric conductor, cooperation are set in the connecting hole, and first pad and each second pad connect with the electric conductor
It connects.
12. semiconductor devices according to claim 11, which is characterized in that adhere to the perforation of different second pads separately
It is of different sizes, the semiconductor devices further include:
Separation layer is set between the connecting hole inner wall and the electric conductor, and the separation layer expose first pad and
Surface of second pad far from first chip.
13. semiconductor devices according to claim 11, which is characterized in that be right against each of first pad and described wear
The center in hole and the center of first pad are collinearly arranged.
14. semiconductor devices according to claim 11, which is characterized in that first pad and second pad
Material is metal.
15. semiconductor devices according to claim 14, which is characterized in that the material of first pad be copper, aluminium and
Any in tungsten, the material of second pad is any in copper, aluminium and tungsten.
16. semiconductor devices according to claim 11, which is characterized in that first chip includes:
First substrate；
First insulating layer, is set to first one side of substrate, and first pad is embedded at first insulating layer far from described
The surface of first substrate；
Second chip includes:
Second substrate；
Second insulating layer, the side set on second substrate far from first chip, second pad are embedded at described
Surface of the second insulating layer far from second substrate；
Second substrate of second chip nearest apart from first chip is set to first insulating layer far from first lining
The surface at bottom, the second substrate of each second chip and the alternately laminated setting of second insulating layer.
17. a kind of storage device, which is characterized in that including the described in any item semiconductor devices of claim 11-16.
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| CN201811015658.4A CN109087901A (en) | 2018-08-31 | 2018-08-31 | Storage device, semiconductor devices and its manufacturing method |
| PCT/CN2019/103362 WO2020043171A1 (en) | 2018-08-31 | 2019-08-29 | Memory device, semiconductor device and method for manufacturing the same |
| US17/182,063 US11462514B2 (en) | 2018-08-31 | 2021-02-22 | Memory device with a through hole structure, semiconductor device and method for manufacturing the same |
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| CN201811015658.4A CN109087901A (en) | 2018-08-31 | 2018-08-31 | Storage device, semiconductor devices and its manufacturing method |
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| WO2020043171A1 (en) * | 2018-08-31 | 2020-03-05 | Changxin Memory Technologies, Inc. | Memory device, semiconductor device and method for manufacturing the same |
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