CN109087314B - FPGA-based linear array image connected domain area rapid marking statistical method - Google Patents

FPGA-based linear array image connected domain area rapid marking statistical method Download PDF

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CN109087314B
CN109087314B CN201810936977.2A CN201810936977A CN109087314B CN 109087314 B CN109087314 B CN 109087314B CN 201810936977 A CN201810936977 A CN 201810936977A CN 109087314 B CN109087314 B CN 109087314B
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ram
data
pixel
label
setting
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CN109087314A (en
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黄继业
谢尚港
龚南飞
高明煜
何志伟
杨宇翔
李芸
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Hangzhou Dianzi University
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/10—Segmentation; Edge detection
    • G06T7/11—Region-based segmentation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/10—Segmentation; Edge detection
    • G06T7/187—Segmentation; Edge detection involving region growing; involving region merging; involving connected component labelling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/60—Analysis of geometric attributes
    • G06T7/62—Analysis of geometric attributes of area, perimeter, diameter or volume

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Abstract

The invention discloses a rapid marking and counting method for the area of a linear array image connected domain based on an FPGA (field programmable gate array), which comprises the following steps of: storing and reading the current pixel, the upper edge pixel and the left edge pixel; and marking and calculating the area of the connected area block. The invention is applied to equipment with high requirement on image processing speed, and marks the connected region of the same area block, thereby realizing the distinguishing of the area blocks and the calculation of the area blocks. In addition, the pixels processed by the method are line pixels acquired by the linear array camera, a large amount of image data does not need to be stored, only two lines of pixels need to be stored, and the pixels are kept to be updated continuously, so that the rapid marking and processing of the image connected domain can be completed.

Description

FPGA-based linear array image connected domain area rapid marking statistical method
Technical Field
The invention belongs to the field of industrial machine vision, and relates to a rapid marking and counting method for an area of a linear array image connected domain based on an FPGA (field programmable gate array).
Background
At present, the image connected domain area calculation method can only be used in occasions with low requirements on processing speed, and an image connected domain area calculation method which can be realized at high speed is lacked. Current methods are generally implemented by the CPU, which requires a long time for connected domain labeling and area calculation of an image due to its sequential execution mode. Moreover, for real-time images, the traditional method is used for realizing the calculation of the area of the connected domain, and a large amount of pixel data needs to be stored, which not only greatly increases the requirements on the performance of the memory, but also seriously slows down the running speed of the system. If the method is applied to high-speed real-time images, such as in a material sorting device, the falling speed of the material is extremely high, and it is obviously difficult to meet the requirement of high-speed real-time performance.
Disclosure of Invention
The invention provides a method for rapidly marking and counting the area of a linear array image connected domain based on an FPGA (field programmable gate array), aiming at the defects of the prior art, the method can be applied to equipment with high requirements on image processing speed to mark the connected domain of the same area block, and can realize the distinguishing of the area blocks and the calculation of the area blocks. In addition, the pixels processed by the method are line pixels acquired by the linear array camera, a large amount of image data does not need to be stored, only two lines of pixels need to be stored, and the pixels are kept to be updated continuously, so that the rapid marking and processing of the image connected domain can be completed.
In order to achieve the purpose, the technical scheme of the invention is a rapid marking statistical method for the area of a linear array image connected domain based on an FPGA, which comprises the following steps:
storing and reading the current pixel, the upper edge pixel and the left edge pixel;
and marking and calculating the area of the connected area block.
Preferably, the storing and reading of the current pixel, the upper edge pixel and the left edge pixel specifically includes the following steps:
setting the input of the comparator as a current pixel and a background pixel, and if the current pixel is the background, outputting the current pixel as 0; if not, outputting the current pixel as 1;
setting the number of pixels in a row as N, setting a flag register start _ flag and a pixel counter cnt, starting to input a first pixel at I +1 clocks, generating a high-level pulse by the start _ flag, and starting to count by the pixel counter cnt;
setting two RAMs as RAM _ clr _ one and RAM _ clr _ two respectively, wherein the two RAMs alternately store pixels in a current line and pixels in a previous line, and setting a switching flag register RAM _ change _ flag for switching; when the switching flag register ram _ change _ flag is 1, storing the pixels in the current line in ram _ clr _ one and storing the pixels in the previous line in ram _ clr _ two; when the switching flag register ram _ change _ flag is 0, storing the pixels in the current line in ram _ clr _ two, and storing the pixels in the previous line in ram _ clr _ one;
storing the pixels of the current line in ram _ clr _ one, inputting a pixel clr _ in at an I + n clock, storing the pixels in ram _ clr _ one at an I + n +1 clock, reading data of a cnt-1 address by using an address as a pixel counter cnt, and obtaining a data _ now _ in of the current pixel at an I + n +2 clock; reading data with the address of cnt-1 in ram _ clr _ two at the clock I + n +1, and obtaining an upper pixel data _ up _ in at the clock I + n + 2; setting a register data _ cnt _ in and recording the serial number of the current pixel, wherein the data _ cnt _ in is cnt-2;
register the current pixel of I + n +1 clock as the left pixel of I + n +2 clock, and record as data _ left _ in.
Preferably, the marking and area calculating of the connected area block specifically includes the following steps:
registering the output current pixel data _ now _ in, the upper side pixel data _ up _ in, the left side pixel data _ left _ in and the pixel serial number data _ cnt _ in, and obtaining the current pixel data _ now, the upper side pixel data _ up _ in, the left side pixel data _ left and the pixel serial number data _ cnt which are aligned strictly at an I + n +3 clock;
setting two RAMs as RAM _ label _ one and RAM _ label _ two respectively, wherein the two RAMs are used for alternately storing the mark value of the pixel in the current row and the mark value of the pixel in the previous row, and setting a switching flag register RAM _ label _ change _ flag for switching; when the switch flag register ram _ label _ change _ flag is 1, the current line mark is stored in ram _ label _ one, and the previous line mark is stored in ram _ label _ two; when the switch flag register ram _ label _ change _ flag is 0, the current line flag is stored in ram _ label _ two, and the previous line flag is stored in ram _ label _ one;
the current line mark is stored in ram _ label _ one, the current mark label _ now is determined at an I + n +3 clock, the label _ now is stored in ram _ label _ one, the address is data _ cnt, the current mark label _ now of the current clock is label _ left of a next clock I + n +4 clock, the data of the address data _ cnt in ram _ label _ two is read at the I + n +3 clock, and the mark label _ up is obtained at the I + n +4 clock;
if the current pixel data _ now is 1, setting the input of the comparator A as the left pixel data _ left and 1, and if the input of the comparator A is equal to the left pixel data _ left, setting the current flag to be the same as the left flag; otherwise, setting the input of the comparator B as an upper edge pixel data _ up and 1, and if the input of the comparator B is equal to the upper edge pixel data _ up and 1, setting the current mark as the same as the upper edge mark; otherwise, setting the register label _ new to represent a new mark, setting the current mark label _ now to be the same as the new mark label _ new, and increasing the value of the new mark label _ new by 1;
setting two RAMs as RAM _ set _ one and RAM _ set _ two respectively for storing the relationship between the mark and the connected domain, wherein the RAM _ set _ one and the RAM _ set _ two share one write-in port and the read ports are different; reading data with a ram _ set _ one address as label _ left and reading data with a ram _ set _ two address as label _ up as set _ up at an I + n +4 clock; setting the input of the comparator as an upper relation value label _ up and a current label _ now, and saving the smaller value into am _ set _ one and ram _ set _ two, wherein the address is the larger value of the two data;
setting two RAMs as RAM _ sum _ one and RAM _ sum _ two respectively at an I + n +6 clock to store the areas of the connected area blocks, wherein the RAM _ sum _ one and the RAM _ sum _ two share a write-in port and the read ports are different; 4 times the pixel clock, and each pixel clock carries out 4 steps of operation; after frequency multiplication, setting a comparator at the 1 st clock, and if the set _ up is not 0, setting the read address of ram _ sum _ one as the set _ up; setting the write addresses of RAM _ sum _ one and RAM _ sum _ two as label _ new, setting the write data as 0, and clearing the RAM; at the 2 nd clock, setting a comparator, if set _ up and set _ left are not equal and are not 0, reading data of a set _ left address from ram _ sum _ two, setting the write addresses of ram _ sum _ one and ram _ sum _ two as the larger value of the set _ up and the set _ left, and setting the write data as 0; in the 3 rd clock, the area sum _ data _ rd of the set _ up address and the area sum _ data _ rd2 of the set _ left address are obtained, a comparator is set, if the set _ up is not 0, the writing addresses of ram _ sum _ one and ram _ sum _ two are set as the set _ up, the writing data is sum _ data _ rd +1, and the area of the upper side area block is increased by 1; at the 4 th clock, setting a comparator, if set _ up and set _ left are not equal and are not 0, setting the write addresses of ram _ sum _ one and ram _ sum _ two as the smaller value of the set _ up and set _ left, writing data as sum _ data _ rd + sum _ data _ rd2, and combining the areas of the same connected domain;
2Nrepresenting the number of pixels in a row, at I +2NAnd (5) finishing scanning of pixels in one row by a clock to obtain the connected domain area sum _ data after finishing scanning of the pixels in the previous row.
The invention has the following beneficial effects:
the static area array image connected domain algorithm is modified and applied to the high-speed linear array image, so that the execution speed of the image connected domain algorithm is greatly improved, the storage capacity of the image is saved, and the delay time of linear array image processing and the requirement of a system on the performance of a memory are greatly reduced.
Drawings
FIG. 1 is a flowchart of the steps of a method for rapidly marking and counting the area of a connected domain of a linear array image based on an FPGA according to an embodiment of the invention;
fig. 2 is a flowchart of specific steps of S10 in the method for rapid tag statistics of the area of the linear array image connected domain based on the FPGA according to the embodiment of the present invention;
fig. 3 is a flowchart of specific steps of S20 in the method for rapid tag statistics of the area of the linear array image connected domain based on the FPGA according to the embodiment of the present invention;
fig. 4 is a schematic diagram of a clock in the method for rapidly marking and counting the area of the connected domain of the linear array image based on the FPGA according to the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
On the contrary, the invention is intended to cover alternatives, modifications, equivalents and alternatives which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, certain specific details are set forth in order to provide a better understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details.
Referring to fig. 1, a technical solution of the present invention, which is an embodiment of the present invention, is a flow chart of steps of a method for rapidly marking and counting an area of a linear array image connected domain based on an FPGA, and includes the following steps:
s10, storing and reading the current pixel, the upper edge pixel and the left edge pixel;
and S20, marking and calculating the area of the connected area block.
In a specific embodiment, referring to fig. 2 and 3, the specific steps of S10 and S20 include:
s111, setting the input of the comparator as a current pixel and a background pixel, and if the current pixel is the background, outputting the current pixel as 0; if not, outputting the current pixel as 1;
s121, setting the number of pixels in one line to be N, setting a flag register start _ flag and a pixel counter cnt, wherein in I +1 clock, the first pixel starts to be input, the start _ flag generates a high-level pulse, and the pixel counter cnt starts to count;
s131, setting two RAMs as RAM _ clr _ one and RAM _ clr _ two respectively, wherein the two RAMs alternately store pixels in a current line and pixels in a previous line, and setting a switching flag register RAM _ change _ flag for switching; when the switching flag register ram _ change _ flag is 1, storing the pixels in the current line in ram _ clr _ one and storing the pixels in the previous line in ram _ clr _ two; when the switching flag register ram _ change _ flag is 0, storing the pixels in the current line in ram _ clr _ two, and storing the pixels in the previous line in ram _ clr _ one;
s141, storing the pixels of the current line in ram _ clr _ one, inputting a pixel clr _ in at an I + n clock, storing the pixels in ram _ clr _ one at an I + n +1 clock, reading data of a cnt-1 address by using an address as a pixel counter cnt, and obtaining data _ now _ in of the current pixel at an I + n +2 clock; reading data with the address of cnt-1 in ram _ clr _ two at the clock I + n +1, and obtaining an upper pixel data _ up _ in at the clock I + n + 2; setting a register data _ cnt _ in and recording the serial number of the current pixel, wherein the data _ cnt _ in is cnt-2;
s151, register the current pixel of I + n +1 clock as the left pixel of I + n +2 clock, and record as data _ left _ in.
S211, registering the output current pixel data _ now _ in, the upper side pixel data _ up _ in, the left side pixel data _ left _ in and the pixel serial number data _ cnt _ in, and obtaining a current pixel data _ now, the upper side pixel data _ up _ in, the left side pixel data _ left and the pixel serial number data _ cnt which are strictly aligned at an I + n +3 clock;
s221, setting two RAMs as RAM _ label _ one and RAM _ label _ two respectively, wherein the RAMs are used for alternately storing the mark value of the pixel in the current row and the mark value of the pixel in the previous row, and setting a switching flag register RAM _ label _ change _ flag for switching; when the switch flag register ram _ label _ change _ flag is 1, the current line mark is stored in ram _ label _ one, and the previous line mark is stored in ram _ label _ two; when the switch flag register ram _ label _ change _ flag is 0, the current line flag is stored in ram _ label _ two, and the previous line flag is stored in ram _ label _ one;
s231, storing a current line mark in ram _ label _ one, determining a current mark label _ now at an I + n +3 clock, storing the label _ now in the ram _ label _ one, wherein the address is data _ cnt, the current mark label _ now of the current clock is label _ left of a next clock I + n +4 clock, reading data of the address data _ cnt in ram _ label _ two at the I + n +3 clock, and obtaining an upper mark label _ up at the I + n +4 clock;
s241, if the current pixel data _ now is 1, setting the input of the comparator A as a left pixel data _ left and 1, and if the current pixel data _ now is equal to the left pixel data _ left, setting the current flag to be the same as the left flag; otherwise, setting the input of the comparator B as an upper edge pixel data _ up and 1, and if the input of the comparator B is equal to the upper edge pixel data _ up and 1, setting the current mark as the same as the upper edge mark; otherwise, setting the register label _ new to represent a new mark, setting the current mark label _ now to be the same as the new mark label _ new, and increasing the value of the new mark label _ new by 1;
s251, setting two RAMs as RAM _ set _ one and RAM _ set _ two respectively for storing the relationship between the mark and the connected domain, wherein the RAM _ set _ one and the RAM _ set _ two share one writing port, and the reading ports are different; reading data with a ram _ set _ one address as label _ left and reading data with a ram _ set _ two address as label _ up as set _ up at an I + n +4 clock; setting the input of the comparator as an upper relation value label _ up and a current label _ now, and saving the smaller value into am _ set _ one and ram _ set _ two, wherein the address is the larger value of the two data;
s261, setting two RAMs as RAM _ sum _ one and RAM _ sum _ two respectively at an I + n +6 clock, wherein the two RAMs are used for saving the area of a connected area block, and the RAM _ sum _ one and the RAM _ sum _ two share one write-in port and different read ports; 4 times the pixel clock, and each pixel clock carries out 4 steps of operation; after frequency multiplication, setting a comparator at the 1 st clock, and if the set _ up is not 0, setting the read address of ram _ sum _ one as the set _ up; setting the write addresses of RAM _ sum _ one and RAM _ sum _ two as label _ new, setting the write data as 0, and clearing the RAM; at the 2 nd clock, setting a comparator, if set _ up and set _ left are not equal and are not 0, reading data of a set _ left address from ram _ sum _ two, setting the write addresses of ram _ sum _ one and ram _ sum _ two as the larger value of the set _ up and the set _ left, and setting the write data as 0; in the 3 rd clock, the area sum _ data _ rd of the set _ up address and the area sum _ data _ rd2 of the set _ left address are obtained, a comparator is set, if the set _ up is not 0, the writing addresses of ram _ sum _ one and ram _ sum _ two are set as the set _ up, the writing data is sum _ data _ rd +1, and the area of the upper side area block is increased by 1; at the 4 th clock, setting a comparator, if set _ up and set _ left are not equal and are not 0, setting the write addresses of ram _ sum _ one and ram _ sum _ two as the smaller value of the set _ up and set _ left, writing data as sum _ data _ rd + sum _ data _ rd2, and combining the areas of the same connected domain;
S271，2Nrepresenting the number of pixels in a row, at I +2NAnd (5) finishing scanning of pixels in one row by a clock to obtain the connected domain area sum _ data after finishing scanning of the pixels in the previous row.
Referring to fig. 4, which is a clock diagram of an embodiment of the present invention, pixel data input at I + n clock goes through the following steps:
s10, storing and reading the current pixel, the upper edge pixel and the left edge pixel;
and S20, marking and calculating the area of the connected area block.
Before proceeding, an initialization description is given,
1. setting two RAMs as RAM _ label _ one and RAM _ label _ two respectively, wherein the two RAMs are used for alternately storing the mark value of the pixel in the current row and the mark value of the pixel in the previous row, and setting a switching flag register RAM _ label _ change _ flag for switching; when the switch flag register ram _ label _ change _ flag is 1, the current line mark is stored in ram _ label _ one, and the previous line mark is stored in ram _ label _ two; when the switch flag register ram _ label _ change _ flag is 0, the current line flag is stored in ram _ label _ two, and the previous line flag is stored in ram _ label _ one.
2. The two RAMs are respectively set as RAM _ set _ one and RAM _ set _ two for storing the relationship between the mark and the connected domain, and the RAM _ set _ one and the RAM _ set _ two share one writing port and different reading ports.
3. Setting two RAMs as RAM _ sum _ one and RAM _ sum _ two respectively to store the area of the connected area block, wherein the RAM _ sum _ one and the RAM _ sum _ two share one write port, and the read ports are different.
In a specific embodiment, the specific step of S10 may be as follows:
s110, inputting the pixel clr _ in at the I + n clock, writing the pixel clr _ in into the memory ram _ clr _ one, and setting the address as the pixel counter cnt.
S120, reading data with the cnt-1 address in ram _ clr _ one at an I + n +1 clock, and obtaining a current pixel data _ now _ in at an I + n +2 clock; reading data with the address of cnt-1 in ram _ clr _ two, and obtaining an upper pixel data _ up _ in at an I + n +2 clock; setting a register data _ cnt _ in and recording the serial number of the current pixel, wherein the data _ cnt _ in is cnt-2; register data _ now _ in as the left pixel of I + n +2 clock, denoted as data _ left _ in.
The specific steps of S20 may be as follows:
s210, at an I + n +2 clock, registering the obtained current pixel data _ now _ in, the upper side pixel data _ up _ in, the left side pixel data _ left _ in and the pixel serial number data _ cnt _ in, and obtaining the current pixel data _ now, the upper side pixel data _ up _ in, the left side pixel data _ left and the pixel serial number data _ cnt which are strictly aligned at an I + n +3 clock;
s220, registering the label _ now obtained by the previous pixel processing at the I + n +3 clock, namely label _ left of the next clock I + n +4 clock; reading data of the address data _ cnt in the ram _ label _ two, and obtaining an upper label _ up at an I + n +4 clock;
s230, obtaining label _ left at the clock I + n +4, and marking label _ up at the upper side. If the current pixel data _ now is 1, setting the input of the comparator A as the left pixel data _ left and 1, and if the input of the comparator A is equal to the left pixel data _ left, setting the current flag to be the same as the left flag; otherwise, setting the input of the comparator B as an upper edge pixel data _ up and 1, and if the input of the comparator B is equal to the upper edge pixel data _ up and 1, setting the current mark as the same as the upper edge mark; otherwise, setting the register label _ new to represent a new mark, setting the current mark label _ now to be the same as the new mark label _ new, and increasing the value of the new mark label _ new by 1; reading data with a ram _ set _ one address as label _ left, and reading data with a ram _ set _ two address as label _ up, and recording as label _ up; setting the input of the comparator as an upper relation value label _ up and a current label _ now, and saving the smaller value into am _ set _ one and ram _ set _ two, wherein the address is the larger value of the two data;
s240, at the clock I + n +5, carrying out 4 times of frequency on the pixel clock, and carrying out 4 steps of operation on each pixel clock; after frequency multiplication, setting a comparator at the 1 st clock (P100), and if the set _ up is not 0, setting the read address of ram _ sum _ one as the set _ up; setting the write addresses of RAM _ sum _ one and RAM _ sum _ two as label _ new, setting the write data as 0, and clearing the RAM; at the 2 nd clock (P110), setting a comparator, if set _ up and set _ left are not equal and are not both 0, reading data of a set _ left address from ram _ sum _ two, and setting write addresses of ram _ sum _ one and ram _ sum _ two to the larger value of the set _ up and set _ left, the write data being 0; at the 3 rd clock (P120), the area sum _ data _ rd of the set _ up address and the area sum _ data _ rd2 of the set _ left address are obtained, a comparator is set, if the set _ up is not 0, the writing addresses of ram _ sum _ one and ram _ sum _ two are set as the set _ up, the writing data is sum _ data _ rd +1, and the area of the upper side area block is increased by 1; at the 4 th clock (P130), setting a comparator, if set _ up and set _ left are not equal and are not 0, setting the write addresses of ram _ sum _ one and ram _ sum _ two as the smaller value of set _ up and set _ left, writing data as sum _ data _ rd + sum _ data _ rd2, and combining the areas of the same connected domain;
at this time, the operation for the pixel 1 input at I + n is completed, and since the present architecture is a pipeline architecture, the operations of S10 and S20 are also performed for the pixel 2 input at I + n +1 clock.
The method modifies the static area array image connected domain algorithm, so that the static area array image connected domain algorithm is applied to the high-speed linear array image, the execution speed of the image connected domain algorithm is greatly improved, the storage capacity of the image is saved, and the delay time of linear array image processing and the requirement of a system on the performance of a memory are greatly reduced.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (1)

1. A rapid marking statistical method for an area of a linear array image connected domain based on an FPGA is characterized by comprising the following steps:
storing and reading the current pixel, the upper edge pixel and the left edge pixel;
marking and calculating the area of the connected area block;
the storing and reading of the current pixel, the upper edge pixel and the left edge pixel specifically comprises the following steps:
setting the input of the comparator as a current pixel and a background pixel, and if the current pixel is the background, outputting the current pixel as 0; if not, outputting the current pixel as 1;
setting the number of pixels in a row as N, setting a flag register start _ flag and a pixel counter cnt, starting to input a first pixel at I +1 clocks, generating a high-level pulse by the start _ flag, and starting to count by the pixel counter cnt;
setting two RAMs as RAM _ clr _ one and RAM _ clr _ two respectively, wherein the two RAMs alternately store pixels in a current line and pixels in a previous line, and setting a switching flag register RAM _ change _ flag for switching; when the switching flag register ram _ change _ flag is 1, storing the pixels in the current line in ram _ clr _ one and storing the pixels in the previous line in ram _ clr _ two; when the switching flag register ram _ change _ flag is 0, storing the pixels in the current line in ram _ clr _ two, and storing the pixels in the previous line in ram _ clr _ one;
storing the pixels of the current line in ram _ clr _ one, inputting a pixel clr _ in at an I + n clock, storing the pixels in ram _ clr _ one at an I + n +1 clock, reading data of a cnt-1 address by using an address as a pixel counter cnt, and obtaining a data _ now _ in of the current pixel at an I + n +2 clock; reading data with the address of cnt-1 in ram _ clr _ two at the clock I + n +1, and obtaining an upper pixel data _ up _ in at the clock I + n + 2; setting a register data _ cnt _ in and recording the serial number of the current pixel, wherein the data _ cnt _ in is cnt-2;
registering the current pixel of the I + n +1 clock as the left pixel of the I + n +2 clock, and recording as data _ left _ in;
the marking and area calculation of the communicated area block specifically comprises the following steps:
registering the output current pixel data _ now _ in, the upper side pixel data _ up _ in, the left side pixel data _ left _ in and the pixel serial number data _ cnt _ in, and obtaining the current pixel data _ now, the upper side pixel data _ up _ in, the left side pixel data _ left and the pixel serial number data _ cnt which are aligned strictly at an I + n +3 clock;
setting two RAMs as RAM _ label _ one and RAM _ label _ two respectively, wherein the two RAMs are used for alternately storing the mark value of the pixel in the current row and the mark value of the pixel in the previous row, and setting a switching flag register RAM _ label _ change _ flag for switching; when the switch flag register ram _ label _ change _ flag is 1, the current line mark is stored in ram _ label _ one, and the previous line mark is stored in ram _ label _ two; when the switch flag register ram _ label _ change _ flag is 0, the current line flag is stored in ram _ label _ two, and the previous line flag is stored in ram _ label _ one;
the current line mark is stored in ram _ label _ one, the current mark label _ now is determined at an I + n +3 clock, the label _ now is stored in ram _ label _ one, the address is data _ cnt, the current mark label _ now of the current clock is label _ left of a next clock I + n +4 clock, the data of the address data _ cnt in ram _ label _ two is read at the I + n +3 clock, and the mark label _ up is obtained at the I + n +4 clock;
if the current pixel data _ now is 1, setting the input of the comparator A as the left pixel data _ left and 1, and if the input of the comparator A is equal to the left pixel data _ left, setting the current flag to be the same as the left flag; otherwise, setting the input of the comparator B as an upper edge pixel data _ up and 1, and if the input of the comparator B is equal to the upper edge pixel data _ up and 1, setting the current mark as the same as the upper edge mark; otherwise, setting the register label _ new to represent a new mark, setting the current mark label _ now to be the same as the new mark label _ new, and increasing the value of the new mark label _ new by 1;
setting two RAMs as RAM _ set _ one and RAM _ set _ two respectively for storing the relationship between the mark and the connected domain, wherein the RAM _ set _ one and the RAM _ set _ two share one write-in port and the read ports are different; reading data with a ram _ set _ one address as label _ left and reading data with a ram _ set _ two address as label _ up as set _ up at an I + n +4 clock; setting the input of the comparator as an upper relation value label _ up and a current label _ now, and saving the smaller value into am _ set _ one and ram _ set _ two, wherein the address is the larger value of the two data;
setting two RAMs as RAM _ sum _ one and RAM _ sum _ two respectively at an I + n +6 clock to store the areas of the connected area blocks, wherein the RAM _ sum _ one and the RAM _ sum _ two share a write-in port and the read ports are different; 4 times the pixel clock, and each pixel clock carries out 4 steps of operation; after frequency multiplication, setting a comparator at the 1 st clock, and if the set _ up is not 0, setting the read address of ram _ sum _ one as the set _ up; setting the write addresses of RAM _ sum _ one and RAM _ sum _ two as label _ new, setting the write data as 0, and clearing the RAM; at the 2 nd clock, setting a comparator, if set _ up and set _ left are not equal and are not 0, reading data of a set _ left address from ram _ sum _ two, setting the write addresses of ram _ sum _ one and ram _ sum _ two as the larger value of the set _ up and the set _ left, and setting the write data as 0; in the 3 rd clock, the area sum _ data _ rd of the set _ up address and the area sum _ data _ rd2 of the set _ left address are obtained, a comparator is set, if the set _ up is not 0, the writing addresses of ram _ sum _ one and ram _ sum _ two are set as the set _ up, the writing data is sum _ data _ rd +1, and the area of the upper side area block is increased by 1; at the 4 th clock, setting a comparator, if set _ up and set _ left are not equal and are not 0, setting the write addresses of ram _ sum _ one and ram _ sum _ two as the smaller value of the set _ up and set _ left, writing data as sum _ data _ rd + sum _ data _ rd2, and combining the areas of the same connected domain;
2Nrepresenting the number of pixels in a row, at I +2NAnd (5) finishing scanning of pixels in one row by a clock to obtain the connected domain area sum _ data after finishing scanning of the pixels in the previous row.
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