CN109085412B - Reverse current detection circuit - Google Patents

Reverse current detection circuit Download PDF

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CN109085412B
CN109085412B CN201710445983.3A CN201710445983A CN109085412B CN 109085412 B CN109085412 B CN 109085412B CN 201710445983 A CN201710445983 A CN 201710445983A CN 109085412 B CN109085412 B CN 109085412B
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CN109085412A (en
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郑辰光
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SG Micro Beijing Co Ltd
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SG Micro Beijing Co Ltd
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    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/14—Indicating direction of current; Indicating polarity of voltage
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only

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Abstract

A reverse current detection circuit is provided, which is advantageous in that a weak reverse current (for example, flowing from VOUT to VIN) can be detected by using a common voltage comparator without using a low offset voltage comparator circuit, it is characterized by comprising a first power MOS tube, wherein the grid electrode of the first power MOS tube is respectively connected with a driving module and a voltage limiting module, and is connected with a grounding terminal through a switch, the source electrode and the drain electrode of the first power MOS tube are respectively and correspondingly connected with two input ends of a voltage comparator, the output end of the voltage comparator is connected with the switch control end of the switch, the positive input end of the voltage comparator is connected with the voltage output end, the negative input end of the voltage comparator is connected with the voltage input end, a current sensor is arranged on a line between the voltage output end and the power MOS tube, the current sensor is connected with a current detection module, and the current detection module is connected with the voltage limiting module.

Description

Reverse current detection circuit
Technical Field
The invention relates to a reverse current detection technology, in particular to a reverse current detection circuit which is beneficial to detecting weak reverse current (such as flowing from a VOUT end to a VIN end) by using a common voltage comparator without adopting a low offset voltage comparator circuit.
Background
With the development of low power consumption technology, there are multiple power supply voltages in the same system, and the reverse current blocking function is more important. In addition, in The background of The wide application of The On The Go technology, The master device/The slave device can be interchanged. To prevent reverse current from flowing from the output port of the low power consumption device and to supply its required quiescent current, the reverse current blocking threshold also becomes lower and lower, e.g. 100mA or 10mA, etc. In some special fields like solar energy, a monitoring circuit with a low reverse current blocking threshold is also needed to improve the energy utilization efficiency.
In recent years, the demand of the market for output current is becoming higher, for example, in the USB PD standard or the field of charging power batteries. Therefore, it is desirable to reduce the equivalent impedance of the transmission path as much as possible to improve the efficiency, and the conventional method of detecting the reverse voltage drop on the transmission path to block the reverse current cannot block the lower reverse current, or is too costly. The reverse current detection circuit is used for blocking weak reverse current, for example, the circuit is connected between an active device and an active device in series, and a path between the devices is closed after low reverse current is detected so as to prevent the active load from supplying power/leaking power to an upstream device.
Disclosure of Invention
The invention provides a reverse current detection circuit aiming at the defects or shortcomings in the prior art, which is beneficial to detecting weak reverse current (such as flowing from a VOUT end to a VIN end) by using a common voltage comparator without adopting a low offset voltage comparator circuit.
The technical scheme of the invention is as follows:
the reverse current detection circuit is characterized by comprising a first power MOS tube, wherein a grid electrode of the first power MOS tube is respectively connected with a driving module and a voltage limiting module and is connected with a grounding end through a switch, a source electrode and a drain electrode of the first power MOS tube are respectively and correspondingly connected with two input ends of a voltage comparator, an output end of the voltage comparator is connected with a switch control end of the switch, a positive input end of the voltage comparator is connected with a voltage output end, a negative input end of the voltage comparator is connected with a voltage input end, a current sensor is arranged on a line between the voltage output end and the power MOS tube and is connected with a current detection module, and the current detection module is connected with the voltage limiting module.
The first power MOS tube is a power NMOS tube, a source electrode of the power NMOS tube is respectively connected with a positive input end and a voltage output end of the voltage comparator, and a drain electrode of the power NMOS tube is respectively connected with a negative input end and a voltage input end of the voltage comparator.
The first power MOS tube is a power NMOS tube, the source electrode of the power NMOS tube is respectively connected with the positive input end of the voltage comparator, the voltage output end of the voltage comparator and the positive input end of the amplifier, the negative input end of the amplifier is respectively connected with the source electrode of the sensing NMOS tube and the source electrode of the third PMOS tube, the grid electrode of the sensing NMOS tube is connected with the grid electrode of the power NMOS tube, the drain electrode of the sensing NMOS tube is connected with the voltage input end, the output end of the amplifier is connected with the grid electrode of the third PMOS tube, and the drain electrode of the third PMOS tube is connected with the grounding end through a first current source.
The drain electrode of the third PMOS tube is respectively connected with the drain electrode and the grid electrode of the fourth NMOS tube, the source electrode of the fourth NMOS tube is grounded, the grid electrode of the fourth NMOS tube is connected with the grid electrode of the fifth NMOS tube, the drain electrode of the fifth NMOS tube is connected with the voltage input end through a second current source, and the source electrode of the fifth NMOS tube is grounded.
The second current source is connected between a grid electrode of a sixth MOS tube and a grid electrode of a seventh MOS tube, the sixth MOS tube is a sixth NMOS tube, the seventh MOS tube is a seventh PMOS tube, a drain electrode of the sixth NMOS tube is mutually connected with a drain electrode of the seventh PMOS tube, a source electrode of the seventh PMOS tube is connected with the grid electrode of the power NMOS tube, and a source electrode of the sixth NMOS tube is grounded through a fourth current source.
The output end of the voltage comparator is connected with the grid electrode of an eighth MOS tube, the eighth MOS tube is an eighth NMOS tube, the source electrode of the eighth NMOS tube is grounded, the drain electrode of the eighth NMOS tube is connected with the grid electrode of the power NMOS tube, the grid electrode of the power NMOS tube is connected with a charge pump, and the charge pump is connected with the voltage input end through a third current source.
The first power MOS tube is a power PMOS tube, a drain electrode of the power PMOS tube is respectively connected with a positive input end of the voltage comparator, a voltage output end of the voltage comparator and a positive input end of the amplifier, a negative input end of the amplifier is respectively connected with a drain electrode of the sensing PMOS tube and a source electrode of the third PMOS tube, a grid electrode of the sensing PMOS tube is connected with a grid electrode of the power PMOS tube, the source electrode of the sensing PMOS tube is connected with the voltage input end, an output end of the amplifier is connected with the grid electrode of the third PMOS tube, and the drain electrode of the third PMOS tube is connected with a grounding end through a first current source.
The drain electrode of the third PMOS tube is respectively connected with the drain electrode and the grid electrode of the fourth NMOS tube, the source electrode of the fourth NMOS tube is grounded, the grid electrode of the fourth NMOS tube is connected with the grid electrode of the fifth NMOS tube, the drain electrode of the fifth NMOS tube is connected with the voltage input end through a second current source, and the source electrode of the fifth NMOS tube is grounded.
The drain electrode of the fifth NMOS tube is connected with the grid electrode of a sixth MOS tube through a second inverting amplifier, the sixth MOS tube is a sixth PMOS tube, the drain electrode of the sixth PMOS tube is connected with the grid electrode of a seventh MOS tube, the seventh MOS tube is a seventh NMOS tube, the drain electrode of the sixth PMOS tube is connected with the drain electrode of the seventh NMOS tube, the source electrode of the seventh NMOS tube is connected with the grid electrode of the power PMOS tube, and the source electrode of the sixth PMOS tube is connected with the voltage input end through a third current source.
The output end of the voltage comparator is connected with the grid electrode of an eighth MOS tube through the first inverting amplifier, the eighth MOS tube is an eighth PMOS tube, the source electrode of the eighth PMOS tube is connected with the voltage input end, the drain electrode of the eighth PMOS tube is divided into two paths, one path is connected with the grid electrode of the power PMOS tube, and the other path is grounded through a fourth current source.
The invention has the following technical effects: the reverse current detection circuit can judge whether the power MOS tube enters a light load state/a reverse state or not through the output current detection circuit, the conduction impedance of the power MOS tube can be actively increased after the power MOS tube enters the light load state/the reverse state, and the absolute value of the gate-source voltage is reduced to achieve the purpose of increasing the conduction impedance of the power MOS tube on the premise that the power MOS tube is ensured to be conducted through the voltage limiting module. The function of detecting weak reverse current is realized by increasing the on-resistance of the power MOS tube, so that the detection of the weak reverse current can be realized by a simple method without designing a low-offset amplifier (A1) circuit.
Drawings
Fig. 1 is a schematic diagram of a first example of a reverse current detection circuit according to the present invention.
Fig. 2 is a schematic diagram of a second embodiment of a reverse current detection circuit according to the present invention.
Fig. 3 is a schematic diagram of a third embodiment of a reverse current detection circuit according to the present invention.
The reference numbers are listed below: 1-a current detection module; 2-a voltage limiting module; 3-a drive module; 4-a current sensor; 5-grounding end; 6-switch control end; 7-a charge pump; m1-first power MOS transistor (e.g., power NMOS transistor, or power PMOS transistor); a1 — voltage comparator; s1-a switching circuit or switch; vG-a gate voltage or a gate voltage value; vLOW-an output signal or an output signal value; VIN-voltage inputA terminal or voltage input value; VOUT-voltage output terminal or voltage output value; vRV-a comparator output voltage; i isOUT-an output current or output current terminal; m2-induction MOS tube; a2-amplifier; m3-third PMOS tube; m4-fourth NMOS tube; m5-fifth NMOS tube; m6-sixth MOS tube; m7-seventh MOS tube; m8-eighth MOS tube; i isB1-a first reference current or first current source; i isB2-a second reference current or a second current source; i isSE-inducing an electric current; i isUP-a third current source or a charge pump current source; i isDW-a fourth current source or a fourth reference current.
Detailed Description
The invention is described below with reference to the accompanying drawings (fig. 1-3).
Fig. 1 is a schematic diagram of a first example of a reverse current detection circuit according to the present invention. Fig. 2 is a schematic diagram of a second embodiment of a reverse current detection circuit according to the present invention. Fig. 3 is a schematic diagram of a third embodiment of a reverse current detection circuit according to the present invention. As shown in fig. 1 to 3, a reverse current detection circuit includes a first power MOS transistor M1, the gates of the first power MOS transistor M1 are respectively connected to the driving module 3 and the voltage limiting module 2, and is connected with a grounding terminal 5 through a switch S1, the source electrode and the drain electrode of the first power MOS tube M1 are respectively and correspondingly connected with two input ends (+ and-) of a voltage comparator A1, the output end of the voltage comparator A1 is connected with the switch control end 6 of the switch S1, the positive input end (+) of the voltage comparator A1 is connected with the voltage output end VOUT, the negative input (-) of the voltage comparator a1 is connected to the voltage input VIN, a current sensor 4 is arranged on a line between the voltage output terminal VOUT and the first power MOS transistor M1, the current sensor 4 is connected with the current detection module 1, and the current detection module 1 is connected with the voltage limiting module 2. The first power MOS transistor M1 is a power NMOS transistor, a source of the power NMOS transistor is connected to the positive input terminal (+) of the voltage comparator a1 and the voltage output terminal VOUT, respectively, and a drain of the power NMOS transistor is connected to the negative input terminal (-) of the voltage comparator a1 and the voltage input terminal VIN, respectively.
The first power MOS transistor M1 is a power NMOS transistorThe source electrodes of the power NMOS transistors are respectively connected to the positive input end (+) of the voltage comparator a1 and the voltage output end VOUT, and the positive input end (+) of the amplifier a2, the negative input end (-) of the amplifier a2 is respectively connected to the source electrode of the sensing NMOS transistor (see the sensing MOS transistor M2 in fig. 2) and the source electrode of the third PMOS transistor M3, the gate electrode of the sensing NMOS transistor is connected to the gate electrode of the power NMOS transistor, the drain electrode of the sensing NMOS transistor is connected to the voltage input end VIN, the output end of the amplifier a2 is connected to the gate electrode of the third PMOS transistor M3, and the drain electrode of the third PMOS transistor M3 is connected to the gate electrode of the first current source IB1To ground terminal 5. The drain of the third PMOS transistor M3 is connected to the drain and the gate of the fourth NMOS transistor M4, respectively, the source of the fourth NMOS transistor M4 is grounded, the gate of the fourth NMOS transistor M4 is connected to the gate of the fifth NMOS transistor M5, and the drain of the fifth NMOS transistor M5 passes through the second current source IB2The voltage input end VIN is connected, and the source of the fifth NMOS transistor M5 is grounded. The second current source IB2The power NMOS transistor is connected between a grid electrode of a sixth MOS transistor M6 and a grid electrode of a seventh MOS transistor M7, the sixth MOS transistor M6 is a sixth NMOS transistor, the seventh MOS transistor M7 is a seventh PMOS transistor, a drain electrode of the sixth NMOS transistor is connected with a drain electrode of the seventh PMOS transistor, a source electrode of the seventh PMOS transistor is connected with the grid electrode of the power NMOS transistor, and a source electrode of the sixth NMOS transistor passes through a fourth current source IDWAnd (4) grounding. The output end of the voltage comparator A1 is connected with the grid electrode of an eighth MOS tube M8, the eighth MOS tube M8 is an eighth NMOS tube, the source electrode of the eighth NMOS tube is grounded, the drain electrode of the eighth NMOS tube is connected with the grid electrode of the power NMOS tube, the grid electrode of the power NMOS tube is connected with the charge pump 7, and the charge pump 7 passes through a third current source IUPThe voltage input terminal VIN is connected.
The first power MOS transistor M1 is a power PMOS transistor, the drain of the power PMOS transistor is connected to the positive input terminal (+) of the voltage comparator a1 and the voltage output terminal VOUT, respectively, and the positive input terminal (+) of the amplifier a2, the negative input terminal (-) of the amplifier a2 is connected to the drain of an induction PMOS transistor (see the induction MOS transistor M2 in fig. 3) and the source of a third PMOS transistor M3, the gate of the induction PMOS transistor is connected to the gate of the power PMOS transistor, and the gate of the induction PMOS transistor is connected to the gate of the power PMOS transistorThe source electrode of the sensing PMOS tube is connected with the voltage input end VIN, the output end of the amplifier A2 is connected with the grid electrode of the third PMOS tube M3, and the drain electrode of the third PMOS tube M3 passes through a first current source IB1And is connected with the ground terminal. The drain of the third PMOS transistor M3 is connected to the drain and the gate of the fourth NMOS transistor M4, respectively, the source of the fourth NMOS transistor M4 is grounded, the gate of the fourth NMOS transistor M4 is connected to the gate of the fifth NMOS transistor M5, and the drain of the fifth NMOS transistor M5 passes through the second current source IB2The voltage input end VIN is connected, and the source of the fifth NMOS transistor M5 is grounded. The drain of the fifth NMOS transistor M5 is connected to the gate of a sixth MOS transistor M6 through a second inverting amplifier, the sixth MOS transistor M6 is a sixth PMOS transistor, the drain of the sixth PMOS transistor is connected to the gate of a seventh MOS transistor M7, the seventh MOS transistor M7 is a seventh NMOS transistor, the drain of the sixth PMOS transistor is connected to the drain of the seventh NMOS transistor, the source of the seventh NMOS transistor is connected to the gate of the power PMOS transistor, and the source of the sixth PMOS transistor passes through a third current source IUPThe voltage input terminal VIN is connected.
The output end of the voltage comparator A1 is connected with the gate of an eighth MOS tube M8 through a first inverting amplifier, the eighth MOS tube M8 is an eighth PMOS tube, the source electrode of the eighth PMOS tube is connected with the voltage input end VIN, the drain electrode of the eighth PMOS tube is divided into two paths, one path is connected with the gate of the power PMOS tube, and the other path is connected with the fourth current source IDWAnd (4) grounding.
Fig. 1 includes a power NMOS (M1), a driving module, a current detection module, a voltage limiting module, a voltage comparator (a1), and a switch (S1). Where VIN is terminated to the power supply and VOUT is terminated to the load. The functions are as follows: when the output current detected by the current detection module is low, the circuit judges that the chip is in a light load mode and the output signal VLOW is effective. This will cause the limit module to operate and pull VG low. And when VG-VOUT becomes low, the equivalent resistance of M1 becomes large. When the equivalent resistance of M1 becomes large, a weak reverse current can create a voltage differential sufficient to flip the a1 comparator, after which VRV is high and S1 is closed. After S1 closes, VG further decreases to zero causing the power NMOS (M1) to turn off. In conclusion, the circuit scheme realizes the function of detecting weak reverse current by increasing the on-resistance of the power MOS tube.
The operating principle of the circuit of fig. 2 is as follows:
VIN is a power supply voltage input end, and VOUT is an output voltage end.
M1 is a larger size power NMOS transistor, M2 is a sense NMOS transistor, and M1 is proportional to M2.
3. The charge pump serves as a driving module of the power NMOS tube, wherein IUP is a current source of the charge pump.
IOUT is power NMOS tube source current, ISE is induction NMOS tube source current.
A1 is voltage comparator, A2 is amplifier.
A2, M3, and current source IB1 make up the current sensing module, and it forces the ratio of ISE to IOUT to be equal to the ratio of the sizes of M2 to M1.
And 7, forming a voltage limiting module by the M6, the M7 and the reference current IDW.
8. When the VOUT is lightly loaded (light load condition), ISE, which is proportional to IOUT, is smaller than the reference current IB1, so M4 has no drain current, which also results in M5 having no drain current, and thus VLOW goes high with the reference current IB 2.
When IDW is higher than IUP, the voltage VG is decreased (VGs1 is also decreased), and it depends on VOUT + VGs1 ═ VIN + VSG7, where VGs1 is the gate-source voltage of the NMOS transistor and VSG7 is the source-gate voltage of M7 (PMOS).
VGS1 drops, naturally resulting in an increase in the on-resistance (Rds _ on) of M1.
11. When VOUT is equal to or greater than VIN (reverse state), the source voltage of M2 is equal to VIN and therefore becomes smaller than ISE in the light load state, so that the descriptions of 8 and 9 are still true and the on-resistance of the power NMOS transistor is still large.
12. According to the above description, the circuit of the invention can detect a weak reverse current (flowing from the terminal VOUT to the terminal VIN) by setting appropriate parameters to obtain a sufficiently large power NMOS on-resistance in the reverse state, without designing a low offset voltage comparator (a1) circuit.
The operating principle of the circuit of fig. 3 is as follows:
VIN is a power supply voltage input end, and VOUT is an output voltage end.
M1 is a larger power PMOS transistor, M2 is a sense PMOS transistor, and M1 is proportional to M2.
3. The current source IDW serves as a driving module of the power PMOS transistor.
IOUT is power PMOS tube source current, ISE is induction PMOS tube source current.
A1 is voltage comparator, A2 is amplifier circuit.
A2, M3, and current source IB1 make up the current sensing module, and it forces the ratio of ISE to IOUT to be equal to the ratio of the sizes of M2 to M1.
And 7, M6, M7 and the reference current IUP form a voltage limiting module.
8. When the VOUT is lightly loaded (light load condition), ISE, which is proportional to IOUT, is smaller than the reference current IB1, so M4 has no drain current, which also results in M5 having no drain current, and thus VLOW goes high with the reference current IB 2.
When the voltage level of VLOW is high, M6(NMOS) is turned on, and when IUP is greater than or equal to IDW, the voltage VG rises (VSG1 falls), and depends on VOUT + VSG1 ═ VIN + VGs7, where VSG1 is the source-gate voltage of the PMOS transistor, and VGs7 is the gate-source voltage of M7 (NMOS).
VSG1 drops, naturally resulting in an increase in the on-resistance (Rds _ on) of M1.
11. When VOUT is equal to or greater than VIN (reverse state), the source voltage of M2 is equal to VIN and therefore becomes smaller than ISE in the light load state, so that the descriptions of 8 and 9 are still true and the on-resistance of the power PMOS transistor is still large.
12. According to the above description, the circuit of the invention can detect a weak reverse current (flowing from the terminal VOUT to the terminal VIN) by setting appropriate parameters to obtain a sufficiently large power PMOS on-resistance in the reverse state, without designing a voltage comparator (a1) circuit with a low offset voltage.
It is pointed out here that the above description is helpful for the person skilled in the art to understand the invention, but does not limit the scope of protection of the invention. Any such equivalents, modifications and/or omissions as may be made without departing from the spirit and scope of the invention may be resorted to.

Claims (2)

1. A reverse current detection circuit is characterized by comprising a first power MOS tube, wherein the grid electrode of the first power MOS tube is respectively connected with a driving module and a voltage limiting module and is connected with a grounding end through a switch, the source electrode and the drain electrode of the first power MOS tube are respectively and correspondingly connected with two input ends of a voltage comparator, the output end of the voltage comparator is connected with the switch control end of the switch, the positive input end of the voltage comparator is connected with a voltage output end, the negative input end of the voltage comparator is connected with a voltage input end, a current sensor is arranged on a line between the voltage output end and the power MOS tube and is connected with a current detection module, and the current detection module is connected with the voltage limiting module;
the first power MOS tube is a power NMOS tube, a source electrode of the power NMOS tube is respectively connected with a positive input end and a voltage output end of the voltage comparator, and a positive input end of the amplifier, a negative input end of the amplifier is respectively connected with a source electrode of the sensing NMOS tube and a source electrode of a third PMOS tube, a grid electrode of the sensing NMOS tube is connected with a grid electrode of the power NMOS tube, a drain electrode of the sensing NMOS tube is connected with the voltage input end, an output end of the amplifier is connected with a grid electrode of the third PMOS tube, and a drain electrode of the third PMOS tube is connected with a grounding end through a first current source;
the drain electrode of the third PMOS tube is respectively connected with the drain electrode and the grid electrode of a fourth NMOS tube, the source electrode of the fourth NMOS tube is grounded, the grid electrode of the fourth NMOS tube is connected with the grid electrode of a fifth NMOS tube, the drain electrode of the fifth NMOS tube is connected with the voltage input end through a second current source, and the source electrode of the fifth NMOS tube is grounded;
the second current source is connected between a grid electrode of a sixth MOS tube and a grid electrode of a seventh MOS tube, the sixth MOS tube is a sixth NMOS tube, the seventh MOS tube is a seventh PMOS tube, a drain electrode of the sixth NMOS tube is mutually connected with a drain electrode of the seventh PMOS tube, a source electrode of the seventh PMOS tube is connected with the grid electrode of the power NMOS tube, and a source electrode of the sixth NMOS tube is grounded through a fourth current source;
the output end of the voltage comparator is connected with the grid electrode of an eighth MOS tube, the eighth MOS tube is an eighth NMOS tube, the source electrode of the eighth NMOS tube is grounded, the drain electrode of the eighth NMOS tube is connected with the grid electrode of the power NMOS tube, the grid electrode of the power NMOS tube is connected with a charge pump, and the charge pump is connected with the voltage input end through a third current source.
2. A reverse current detection circuit is characterized by comprising a first power MOS tube, wherein the grid electrode of the first power MOS tube is respectively connected with a driving module and a voltage limiting module and is connected with a grounding end through a switch, the source electrode and the drain electrode of the first power MOS tube are respectively and correspondingly connected with two input ends of a voltage comparator, the output end of the voltage comparator is connected with the switch control end of the switch, the positive input end of the voltage comparator is connected with a voltage output end, the negative input end of the voltage comparator is connected with a voltage input end, a current sensor is arranged on a line between the voltage output end and the power MOS tube and is connected with a current detection module, and the current detection module is connected with the voltage limiting module;
the first power MOS tube is a power PMOS tube, a drain electrode of the power PMOS tube is respectively connected with a positive input end and a voltage output end of the voltage comparator and a positive input end of the amplifier, a negative input end of the amplifier is respectively connected with a drain electrode of an induction PMOS tube and a source electrode of a third PMOS tube, a grid electrode of the induction PMOS tube is connected with a grid electrode of the power PMOS tube, the source electrode of the induction PMOS tube is connected with the voltage input end, an output end of the amplifier is connected with the grid electrode of the third PMOS tube, and a drain electrode of the third PMOS tube is connected with a grounding end through a first current source;
the drain electrode of the third PMOS tube is respectively connected with the drain electrode and the grid electrode of a fourth NMOS tube, the source electrode of the fourth NMOS tube is grounded, the grid electrode of the fourth NMOS tube is connected with the grid electrode of a fifth NMOS tube, the drain electrode of the fifth NMOS tube is connected with the voltage input end through a second current source, and the source electrode of the fifth NMOS tube is grounded;
the drain electrode of the fifth NMOS tube is connected with the grid electrode of a sixth MOS tube through a second inverting amplifier, the sixth MOS tube is a sixth PMOS tube, the drain electrode of the sixth PMOS tube is connected with the grid electrode of a seventh MOS tube, the seventh MOS tube is a seventh NMOS tube, the drain electrode of the sixth PMOS tube is connected with the drain electrode of the seventh NMOS tube, the source electrode of the seventh NMOS tube is connected with the grid electrode of the power PMOS tube, and the source electrode of the sixth PMOS tube is connected with the voltage input end through a third current source;
the output end of the voltage comparator is connected with the grid electrode of an eighth MOS tube through the first inverting amplifier, the eighth MOS tube is an eighth PMOS tube, the source electrode of the eighth PMOS tube is connected with the voltage input end, the drain electrode of the eighth PMOS tube is divided into two paths, one path is connected with the grid electrode of the power PMOS tube, and the other path is grounded through a fourth current source.
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