CN109075215A - Output driving with power down protection - Google Patents
Output driving with power down protection Download PDFInfo
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- CN109075215A CN109075215A CN201780013156.5A CN201780013156A CN109075215A CN 109075215 A CN109075215 A CN 109075215A CN 201780013156 A CN201780013156 A CN 201780013156A CN 109075215 A CN109075215 A CN 109075215A
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- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims description 9
- 229910044991 metal oxide Inorganic materials 0.000 claims description 8
- 150000004706 metal oxides Chemical class 0.000 claims description 8
- 238000000926 separation method Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims 2
- 230000003071 parasitic effect Effects 0.000 description 40
- 238000002955 isolation Methods 0.000 description 24
- 229910021332 silicide Inorganic materials 0.000 description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000024241 parasitism Effects 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 101001042415 Cratylia mollis Mannose/glucose-specific lectin Cramoll Proteins 0.000 description 3
- 102100029775 Eukaryotic translation initiation factor 1 Human genes 0.000 description 3
- 101001012787 Homo sapiens Eukaryotic translation initiation factor 1 Proteins 0.000 description 3
- 101000643378 Homo sapiens Serine racemase Proteins 0.000 description 3
- AIXMJTYHQHQJLU-UHFFFAOYSA-N chembl210858 Chemical compound O1C(CC(=O)OC)CC(C=2C=CC(O)=CC=2)=N1 AIXMJTYHQHQJLU-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- WABPQHHGFIMREM-AHCXROLUSA-N lead-203 Chemical compound [203Pb] WABPQHHGFIMREM-AHCXROLUSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
- H03K17/08142—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
- H03K17/6874—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor in a symmetrical configuration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0018—Special modifications or use of the back gate voltage of a FET
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
In the described example, interface device (300) includes the NPN structure (Q1) along the horizontal surface of p doped substrate (204).NPN structure (300) is with the 2nd n doped region (244) for being coupled to the first n doped region (242) of output terminal (106), surrounding the first n doped region (242) and being coupled to the p doped region (232,243,245) of output terminal (107) and separated by p doped region (243) with the first n doped region (242).Interface device (300) further includes the positive-negative-positive structure (230) along the vertical depth of p doped substrate (204).Positive-negative-positive structure (230) includes p doped region (243), the n doped layer (234) below p doped region (243) and p doped substrate (204).Advantageously, interface device (300) can bear high voltage swing (both positive and negative), prevent the load current for filling and widening, and avoid entering low resistance mode during power-down operation.
Description
Background technique
Integrated circuit and electronic device include drive circuit, are used to be connected to two or more systems by interface
Between, which operates in different voltage ranges.Drive circuit typically comprises output driver,
To provide high-pressure side (HS) and low-pressure side (LS) operation.For example, output driver may include HS drive circuit and LS driver
Circuit.HS drive circuit is configured to output terminal transmitting HS output (for example, VDD+ voltage), however LS driver is electric
Road is configured in output terminal transmitting LS output (for example, VDD- voltage).During power-down mode, HS drive circuit and LS
Drive circuit is not activated.However, output terminal can receive high voltage slope from load.High voltage slope can be just
Or it is negative, can be bigger than output voltage.If drive circuit is unprotected, high voltage can be to LS drive circuit and negative
Load damages.
Summary of the invention
In the described example, interface device includes the NPN structure along the horizontal surface of p doped substrate.NPN structure
Be coupled to output terminal the first n doped region, around the first n doped region and be coupled to the p doped region of output terminal with
And the 2nd n doped region separated by p doped region with the first n doped region.Interface device further includes the vertical depth along p doped substrate
The positive-negative-positive structure of degree.Positive-negative-positive structure includes p doped region, the n doped layer below p doped region and p doped substrate.Advantageously, it connects
Mouthpart part can bear high voltage swing (both positive and negative), prevent the load current for filling and widening, and avoid falling
Electrically operated period enters low resistance mode.
Detailed description of the invention
Fig. 1 shows the schematic diagram of the interface device of one side according to example embodiment.
Fig. 2A shows the schematic diagram of low-pressure side (LS) drive circuit of one side according to example embodiment.
Fig. 2 B shows the cross-sectional view of the LS drive circuit device of one side according to example embodiment.
Fig. 3 A shows the schematic diagram of the LS drive circuit with power down protection of one side according to example embodiment.
Fig. 3 B shows the cross section of the LS drive circuit with power down protection of one side according to example embodiment
Figure.
Specific embodiment
Similar reference symbol indicates similar element in various figures.Figure is not drawn on scale.
Example embodiment provides a kind of for protecting drive circuit from high voltage slope shadow during power-down mode
Loud solution.In the described example, low side driver circuit has the parasitism with high-breakdown-voltage double
Polar form structure.High-breakdown-voltage inhibits the latch up effect of parasitic silicon controlled rectifier (SCR) (SCR) structure.Advantageously, described
Low side driver can bear high voltage swing (both positive and negative), prevent the load current for filling and widening, and keep away
Exempt to enter low resistance mode during power-down operation.
Fig. 1 shows the schematic diagram of the interface device 100 of one side according to example embodiment.Interface device 100 is through matching
It sets to receive supply voltage from high-pressure side (HS) voltage supply terminal 102 and low-pressure side (LS) voltage supply terminal 104.For example,
In one embodiment, HS voltage supply terminal 102 is configured to range of receiving as the HS voltage VDD+ of 2V to 7V, however LS
It is the LS voltage VDD- that -7V arrives -2V that voltage supply terminal 104, which is configured range of receiving,.Interface device 100 is configured to based on defeated
Enter to generate the output between HS voltage (for example, VDD+) and LS voltage (for example, VDD-).Output is passed to output terminal
106.Load may be coupled to output terminal 106 with the output of receiving interface device 100.Load can be internal load, can
To be a part of the integrated circuit comprising interface device 100.Alternatively, load can be for collecting with interface device 100
At external loading.
Interface device 100 includes HS control circuit 112, LS control circuit 114, HS drive circuit 122 and LS driving
Device circuit 124.Circuit 112,114,122 and 124 can be fabricated onto integrated circuit die.Alternatively, circuit 112,
114,122 and 124 it can be discrete component, for merging on a printed circuit.HS control circuit 112 is coupled to the confession of HS voltage
To terminal 102, however LS control circuit 114 is coupled to LS voltage supply terminal 104.Based on being supplied to the defeated of interface device 100
Enter, HS control circuit 112 controls the operation of HS drive circuit 122, and LS control circuit 114 controls LS drive circuit
124 operation.For example, HS drive circuit 122 is by HS voltage when HS control circuit 112 activates HS drive circuit 122
(for example, VDD+ is in about+5.5V) is transmitted to output terminal 106.Equally, when LS control circuit 114 activates LS drive circuit
LS voltage (for example, VDD- is in about -5.5V) is transmitted to output terminal 106 by 124, LS drive circuits 124.
During power-down mode, HS control circuit 112 and LS control circuit 114 do not drive HS drive circuit 122 or
Person LS drive circuit 124.However, output terminal 106 can be from load-receipt voltage ramp.In some cases, voltage ramp
Size can be more than any one sizableness is big in HS supply voltage or LS supply voltage allowance (margin) (for example,
Greater than 50%).For example, received voltage ramp may range from+12V to -12V at output terminal 106, wherein HS power supply
Voltage is in+5V and LS supply voltage in -5V.In face of high voltage slope, LS drive circuit 124 can enter breakdown mode,
Thus from output terminal 106 and load conducts high current.
Fig. 2A shows the schematic diagram of low-pressure side (LS) drive circuit 200 of one side according to example embodiment.LS drives
Dynamic device circuit 200 can be used for implementing as shown in Figure 1 and described LS drive circuit 124.Generally, LS drive circuit packet
Include LS input terminal 202, the first transistor Q1 and second transistor Q2.The first transistor Q1, which has, is coupled to LS input terminal
202 control grid 212, is coupled to floating connection (floating lead) 203 at the first terminal 214 for being coupled to output terminal 106
Second terminal 216 and the backgate terminal 218 for being coupled to Second terminal 216.The first transistor Q1 can pass through N-channel metal oxygen
Compound semiconductor (NMOS) transistor and/or N-channel drain extended MOS (DENMOS) transistor are implemented.If first crystal
Pipe Q1 is implemented by NMOS transistor, and drain region can be accessed via first terminal 214, and source area can be via Second terminal
216 is accessed and its body area can be accessed via backgate terminal 218.
Similarly, second transistor Q2 has the control grid 222 for being coupled to LS input terminal 202, is coupled to LS voltage
The first terminal 224 of feeding terminal 104, the Second terminal 226 for being coupled to floating connection 203 and it is coupled to Second terminal 226
Backgate terminal 228.Second transistor Q2 is drained by N-channel metal-oxide semiconductor (MOS) (NMOS) transistor and/or N-channel
Diffused mos (DENMOS) transistors is implemented.If second transistor Q2 is implemented by NMOS transistor, drain region can be via
First terminal 224 is accessed, and source area can be accessed via Second terminal 226 and its body area can be via backgate terminal 228
It is accessed.
Via floating connection 203, second transistor is coupled in the gate regions (via Second terminal 216) of the first transistor Q1
The source area of Q2 (via Second terminal 226).And via floating connection 203, the body area of the first transistor Q1 is (via backgate end
218) son is coupled to the body area of second transistor Q2 (via backgate terminal 228).
Each of the first transistor Q1 and second transistor Q2 are with parasitic silicon controlled rectifier (SCR) (SCR) structure (that is, vertical point
The right side of line) it is associated.These parasitic SCR structures can influence the power-down operation of LS drive circuit 200.First parasitism SCR knot
Structure includes that parasitic positive-negative-positive structure 230 and parasitic NPN structure 240, the two are all associated with the first transistor Q1.Parasitic positive-negative-positive structure
230 including the p-type collector for being coupled to backgate terminal 218, the N-shaped base stage floated in the first isolation lead ISO1 and in p
The p type emitter formed in type substrate 204.Parasitic NPN structure 240 include be coupled to output terminal 106 N-shaped emitter, with
Parasitic positive-negative-positive structure 230 p-type collector connection p-type base stage and by first isolation lead ISO1 in float come with PNP
The N-shaped collector of the N-shaped base stage connection of structure 230.
Second parasitic SCR structure includes parasitic positive-negative-positive structure 250 and parasitic NPN structure 260, the two all with the second crystal
Pipe Q2 is associated.Parasitic positive-negative-positive structure 250 includes the p-type collector for being coupled to backgate terminal 228, is coupled to the second isolation lead
The N-shaped base stage of ISO2 and the p type emitter that its N-shaped base stage is formed and be coupled in p-substrate 204.Parasitic NPN structure
260 including being coupled to the N-shaped emitter of LS voltage supply terminal 104, the p connecting with the p-type collector of parasitic positive-negative-positive structure 230
Type base stage and the N-shaped collector connecting with the N-shaped base stage of positive-negative-positive structure 250, the N-shaped base stage of the parasitism positive-negative-positive structure 250 and are posted
The N-shaped collector of raw NPN structure 260 is both coupled to the second isolation lead ISO2.
Fig. 2 B shows the cross-sectional view of LS drive circuit 200, can be better described above with reference to parasitic structure
Between structure relationship.LS drive circuit 200 is formed in p doped substrate 204, which has level
Surface and the vertical depth extended perpendicular to horizontal surface.The first transistor Q1 includes the NPN structure along horizontal surface.NPN knot
Structure includes the first n doped region 242, the first p doped region 243 and the 2nd n doped region 244.The first transistor Q1 further includes the 2nd p
Doped region (p adulterates lateral areas) 245, laterally surrounds the first n doped region 242 and the 2nd n doped region with the first p doped region 243
244.First p doped region 243 can be formed simultaneously using as single p doped region with the 2nd p doped region 245.
In addition, the first transistor Q1 includes the p doping of support and the first p doped region 243 of connection and the 2nd p doped region 245
Layer 232.P doped layer 232 is can be by ion implanting or the p-type buried layer (PBL) by being epitaxially-formed.Meanwhile the first p mix
Miscellaneous area 243, the 2nd p doped region 245 and p doped layer 232 are formed single p doped region (or p trap), the first n doped region 242 and
Two n doped regions 244 are positioned in the single p doped region, and the first n doped region 242 and the 2nd n doped region 244 are by being somebody's turn to do
Single p doped region is separated.
In addition, the first transistor Q1 includes N-shaped isolation structure, the N-shaped isolation structure is by p doped region (for example, the first p mixes
Miscellaneous area 243, the 2nd p doped region 245 and p doped layer 232) it is isolated with second transistor Q2 and substrate 204.N-shaped isolation structure packet
Include n doped layer 234 and n doped sidewalls 246.N doped layer 234 is positioned in 232 lower section of p doped layer.N doped layer 234 is can be by
Ion implanting or the N-shaped buried layer (NBL) being epitaxially-formed.N doped sidewalls 246 are laterally around including the 2nd p doped region
The p doped region of 245 and p doped layer 232.Its underpart and n doped layer 234 are adjacent, and n doped sidewalls 246 form isolation well structure, p
Doped region (such as 243,245 and 232) is positioned in the isolation well structure.
Similarly, second transistor Q2 includes the NPN structure along horizontal surface.The NPN structure of the first transistor Q1 is neighbouring
It the NPN structure of the first transistor Q1 and is opened with the NPN spacing structure of the first transistor Q1.The NPN structure of second transistor Q2
Including the first n doped region 262, the first p doped region 263 and the 2nd n doped region 264.Second transistor Q2 further includes the 2nd p doping
Area's (p adulterates lateral areas) 265, laterally surrounds the first n doped region 262 and the 2nd n doped region 264 with the first p doped region 263.
First p doped region 263 can be formed simultaneously using as single p doped region with the 2nd p doped region 265.
In addition, second transistor Q2 includes the p doping of support and the first p doped region 263 of connection and the 2nd p doped region 265
Layer 252.P doped layer 252 is can be by ion implanting or the p-type buried layer (PBL) by being epitaxially-formed.Meanwhile the first p mix
Miscellaneous area 263, the 2nd p doped region 265 and p doped layer 252 are formed single p doped region (or p trap), the first n doped region 262 and
Two n doped regions 264 are positioned in the single p doped region, and the first n doped region 262 and the 2nd n doped region 264 are by being somebody's turn to do
Single p doped region is separated.
In addition, second transistor Q2 includes N-shaped isolation structure, the N-shaped isolation structure is by p doped region (for example, the first p mixes
Miscellaneous area 263, the 2nd p doped region 265 and p doped layer 252) it is isolated with the first transistor Q1 and with substrate 204.N-shaped isolation junction
Structure includes n doped layer 254 and n doped sidewalls 266, and the two is spaced apart with the N-shaped isolation structure of the first transistor Q1.N doping
Layer 254 is positioned in 252 lower section of p doped layer.N doped layer 254 is can be covered by ion implanting or the N-shaped by being epitaxially-formed
Buried layer (NBL).N doped sidewalls 246 are laterally around the p doped region including the 2nd p doped region 265 and p doped layer 252.Under it
Portion and n doped layer 254 are adjacent, and n doped sidewalls 246 form isolation well structure, and p doped region (such as 263,265 and 252) is positioned
In the isolation well structure.
Referring again to the first transistor Q1, the first n doped region 242 is coupled to output terminal 106 via first terminal 214,
It can be manufactured to n doping silicide contacts.2nd n doped region 244 is coupled to floating connection via Second terminal 216 and (floats
Dynamic lead) 203, n doping silicide contacts can be manufactured to.P doped region (such as the 2nd p doped region 245) is via backgate
Terminal 218 is coupled to floating connection 203, can be manufactured to p doping silicide contacts.Via floating connection 203, the 2nd n
Doped region 244 is coupled to p doped region (for example, 243,245 and 232).N-shaped isolation structure (for example, 246 and 234) can be via
First isolation terminal ISO1 is accessed, can be manufactured such that n adulterates silicide contacts.
In the embodiment that the first transistor Q1 is NMOS transistor, the first n doped region 242 is used as drain region,
2nd n doped region 244 is used as source area, and the first p doped region 243 is as below control grid 212 and in drain region and source
Channel region and the 2nd p doped region 245 between polar region is as the back gate region on 232 side of p doped layer.In the first transistor
Q1 is in the another embodiment of DENMOS transistor, and the first n doped region 242 is used as drain extensions, the 2nd n doped region
244 are used as source area, and the first p doped region 243 is as the ditch below control grid 212 and between drain region and source area
As the back gate region on 232 side of p doped layer, the 2nd p doped region 245 is optionally used for road area and the 2nd p doped region 245
The area surface field (PESURF) is reduced to enhance.
The first transistor Q1 has been embedded into parasitic SCR structure, which includes parasitic positive-negative-positive structure 230 and parasitism
NPN structure 240.Parasitic positive-negative-positive structure 230 is established along the vertical depth of substrate 204.Parasitic positive-negative-positive structure 230 has to be mixed in p
Collector area in miscellaneous area (such as 243 and 232), the base region in N-shaped isolation structure (for example, 234) and p adulterate serve as a contrast
Emitter region in bottom 204.Parasitic NPN structure 240 is established along the vertical depth and/or horizontal surface of substrate 204.It is parasitic
NPN structure 240 include collector area in N-shaped isolation structure (such as 234 and 246), in p-type doping area (for example, 232 Hes
245) base region in and the emitter region in the first n doped region 242.
Referring again to second transistor Q2, the first n doped region 262 is coupled to LS voltage supply side via first terminal 224
Son 104 can be manufactured to n doping silicide contacts.2nd n doped region 264 is coupled to floating via Second terminal 226 and connects
203 are connect, n doping silicide contacts are manufactured to.P doped region (such as the 2nd p doped region 265) is via 228 coupling of backgate terminal
Floating connection 203 is closed, p doping silicide contacts can be manufactured to.Pass through floating connection 203, the 2nd n doped region 264
It is coupled to p doped region (for example, 263,265 and 262).And by floating connection 203, the 2nd n of the first transistor Q1 is adulterated
Area 244 and p doped region 245 are coupled to the 2nd n doped region 264 and p doped region 265 of second transistor Q2.N-shaped isolation structure
(for example, 266 and 254) can be accessed via the second isolation terminal ISO2, can be manufactured such that n adulterates silicide contacts.?
In one embodiment, the second isolation terminal ISO2 may be connected to ground voltage feeding terminal to receive ground voltage (example
Such as, 0V).
In the embodiment that second transistor Q2 is NMOS transistor, the first n doped region 262 is used as drain region,
2nd n doped region 264 is used as source area, and the first p doped region 263 is as below control grid 222 and in drain region and source
Channel region and the 2nd p doped region 265 between polar region is as the back gate region on 252 side of p doped layer.In second transistor
Q2 is in the another embodiment of DENMOS transistor, and the first n doped region 262 is used as drain extensions, the 2nd n doped region
264 are used as source area, and the first p doped region 263 is as the ditch below control grid 222 and between drain region and source area
As the back gate region on 252 side of p doped layer, the 2nd p doped region 265 is optionally used for road area and the 2nd p doped region 265
The area surface field (PESURF) is reduced to enhance.
Second transistor Q2 has been embedded into parasitic SCR structure, which includes parasitic positive-negative-positive structure 250 and parasitism
NPN structure 260.Parasitic positive-negative-positive structure 250 is established along the vertical depth of substrate 204.Parasitic positive-negative-positive structure 250 has to be mixed in p
Collector area in miscellaneous area (such as 263 and 252), the base region in N-shaped isolation structure (for example, 254) and p adulterate serve as a contrast
Emitter region in bottom 204.Parasitic NPN structure 260 is established along the vertical depth and/or horizontal surface of substrate 204.It is parasitic
NPN structure 260 include collector area in N-shaped isolation structure (such as 254 and 266), in p-type doping area (for example, 252 Hes
265) base region in and the emitter region in the first n doped region 262.
During power-down mode, output terminal 106 can receive positive voltage slope or negative voltage slope.LS drive circuit
200 configuration can maintain relatively large positive voltage slope (for example,+10V) at output terminal 106.This is because first crystal
Knot between the first n doped region 242 and p doped region (for example, 243,245 and 232) of pipe Q1 is in reverse bias.And because
P doped region is to float, and junction voltage will be no more than the breakdown voltage of the knot.
However, when output terminal 106 receives relatively large negative voltage slope (for example, -10V), LS drive circuit 200
It can start to conduct electric current.This is because the base region of parasitic positive-negative-positive structure 230 and parasitic NPN structure 240 is all to float.It is posting
In raw NPN structure 240, the base region floating p (for example, 243,245 and 232) can follow the negative electricity from the first n doped region 242
Press slope.For example, the base region p can follow -9V if the first n doped region 242 is in -10V.In parasitic positive-negative-positive structure 230
It is interior, the base region n (for example, 234 and 246) in p doped layer 232 (for example, -9V) and p doped substrate 204 (for example, 0V) it
Between voltage (for example, -1V) at float.Open circuit-base break down voltage (BVCEO) is directed to parasitic positive-negative-positive structure 230 and parasitic NPN
Both structure 240 all relatively low (for example, 5.5V).Correspondingly, about 1 collector-base electric current of parasitic positive-negative-positive structure 230
Gain (HFE) is switched on, and parasitic NPN structure 240 is switched on about 50 HFE.Therefore, parasitic SCR structure positive feedback
It is triggered, this leads to the latch status in LS drive circuit 200.
Latch status during power-down mode in order to prevent, example embodiment provide the LS drive circuit of modification, this is repaired
The LS drive circuit changed can inhibit the positive feedback of parasitic SCR structure.Fig. 3 A shows the drive of the example LS with power down protection
The schematic diagram of dynamic device circuit 300.As LS driver 200, LS drive circuit 300 can be as shown in Figure 1 and be retouched
That states is used to implement LS drive circuit 124.LS drive circuit 300 includes identical with phase with LS drive circuit 200
With the element of digital reference.The difference of LS drive circuit 300 and LS drive circuit 200 is the first transistor Q1 and second
The arrangement of Drain-Source in each of transistor Q2 is opposite.
More particularly with respect to the first transistor Q1, first terminal 214 is re-arranged to access source area, rather than is drained
Area's (or if the first transistor Q1 is extended drain region when being DEMOS transistor), however Second terminal 216 is re-arranged
To access drain region (or if the first transistor Q1 is the drain region of extension when being DEMOS transistor) rather than source area.
For this purpose, backgate terminal 218 is coupled to first terminal 214 rather than Second terminal 216.Because this is rearranged, backgate terminal
218 no longer float with floating connection 203 together.On the contrary, backgate terminal 218 is coupled to output terminal 106.
About second transistor Q2, first terminal 224 is re-arranged to access source area, rather than drain region (or
If the first transistor Q1 is the drain region of extension when being DEMOS transistor), however Second terminal 216 is re-arranged to visit
Ask drain region (or if second transistor Q2 is the drain region of extension when being DEMOS transistor) rather than source area.For this purpose,
Backgate terminal 228 is coupled to first terminal 224 rather than Second terminal 226.Because this is rearranged, backgate terminal 228 is not
It floats together with floating connection 203 again.On the contrary, backgate terminal 228 is coupled to LS voltage supply terminal 104.Again with this
Arrangement, floating connection 203 are connected to the drain region of the first transistor Q1 and the drain region of second transistor Q2.Correspondingly,
The drain region of one transistor Q1 and the drain region of second transistor Q2 are floated during being configured to power-down mode.
Since these connections rearrange, the parasitic structure (for example, 230,240,250 and 260) of LS drive circuit 300
It is shown during power-down mode when compared with its corresponding part (counterpart) from LS drive circuit 200 different
Characteristic.Fig. 3 B shows the cross-sectional view of LS drive circuit 300, can be better described above with reference to parasitic structure
Between structural relation.Although the connection of several doped regions is re-arranged, LS driver 300 has and 200 phase of LS driver
Same cross-sectional layout.
More particularly with respect to the first transistor Q1, the first n doped region 242 is connected to the 2nd p doped region 245.Correspondingly,
Since the first n doped region 242 and the 2nd p doped region 245 are connected to first lead-out terminal 106, the first n doped region 242 with
2nd p doped region 245 shares same potential.In the configuration, the first n doped region 242 is used as source area during power-down mode
Rather than drain region (or if the first transistor Q1 is the drain region of extension when being DENMOS transistor).Backgate terminal 218
With 216 uncoupling of Second terminal.Because this is rearranged, p doped region (such as 243,245 and 232) no longer with floating connection 203
It floats together.On the contrary, p doped region (such as 243,245 and 232) is coupled to output terminal 106.2nd n doped region 244 is no longer
It is coupled to backgate terminal 218.Instead, as drain region, (or if first is brilliant during power-down mode for the 2nd n doped region 244
Body pipe Q1 is the drain region of extension when being DENMOS transistor).
About second transistor Q2, the first n doped region 262 is connected to the 2nd p doped region 265.Accordingly, due to first
N doped region 262 and the 2nd p doped region 265 are connected to LS voltage supply terminal 104, and the first n doped region 262 is mixed with the 2nd p
Share same potential in miscellaneous area 265.In the configuration, the first n doped region 262 as source area rather than leaks during power-down mode
Polar region (or if the first transistor Q1 is the drain region of extension when being DENMOS transistor).Backgate terminal 228 and second end
Sub 226 uncouplings.Because this is rearranged, p doped region (such as 263,265 and 262) no longer with 203 1 floating of floating connection
It is dynamic.On the contrary, p doped region (such as 263,265 and 262) is coupled to LS voltage supply terminal 104.2nd n doped region 264 is no longer
It is coupled to backgate terminal 228.Instead, as drain region, (or if first is brilliant during power-down mode for the 2nd n doped region 264
Body pipe Q1 is the drain region of extension when being DENMOS transistor).For this purpose, floating connection 203 is connected to the first transistor Q1's
The drain region of drain region and second transistor Q2.And the drain region of the first transistor Q1 and the drain region warp of second transistor Q2
Configuration during power-down mode to float.
Referring again to the first transistor Q1, p doped region (for example, 243,245 and 232) no longer floats, but it is total instead
Enjoy potential identical with the first n doped region 242.Therefore, the base region of parasitic NPN structure 240 is no longer open circuit.Because of NPN
The emitter region of structure 240 and base region are coupled, and identical potential is shared in the two areas.Advantageously, NPN structure 240
Breakdown voltage BVCES increase significantly.For example, in one embodiment, closed circuit-base break down voltage BVCES is in
20V is significantly greater than the open circuit in 6V-base break down voltage BVCEO.Even if when output terminal 106 is in the power-down mode phase
Between receive big voltage ramp (for example, when from -12V to+12V), big breakdown voltage BVCES prevent parasitic NPN structure 240 by
Conduct the influence of electric current.Therefore, facilitated to inhibit 240 couples of parasitism SCR of NPN structure by the configuration that LS drive circuit 300 uses
The positive feedback of structure contributes.Advantageously, LS drive circuit 300 can bear high voltage swing (positive and negative two
Person), the load current for filling and widening is prevented, and avoid entering low resistance mode during power-down operation.
The configuration used by LS drive circuit 300 can be by carrying out weight to interconnecting lead as shown in Figure 2 A and 2 B
New route is implemented.Alternatively, the configuration used by LS drive circuit 300 can be by two groups of additional switches come real
It applies.First group of switch includes first switch 272 and second switch 274.First switch 272 is coupled in p doped region 245 (for example,
The back gate region of one transistor Q1) and output terminal 106 between.Second switch 274 is coupled in p doped region 245 (for example, first is brilliant
The back gate region of body pipe Q1) and floating connection (floating lead) 203 between.During powered-on mode, LS driving is enabled in this period
The device circuit 300 and LS drive circuit 300 is configured to drive output terminal 106, first switch 272 is configured to disconnect
And second switch 274 is configured to be closed.Correspondingly, the back gate region (for example, 245) of the first transistor Q1 is coupled to floating lead
203, and with 106 uncoupling of output terminal.During power-down mode, this period LS drive circuit 300 be in tri-state or
Disabled, first switch 272 is configured to closure and second switch 274 is configured to disconnect.Correspondingly, the first transistor Q1
Back gate region (for example, 245) be coupled to output terminal 106 and with 203 uncoupling of floating lead.
Similarly, second group of switch includes first switch 276 and second switch 278.First switch 276 is coupled in p doping
Between area 265 (for example, back gate region of second transistor Q2) and LS voltage supply terminal 104.Second switch 278 is coupled in p and mixes
Between miscellaneous area 265 (for example, back gate region of second transistor Q2) and floating connection (floating lead) 203.During powered-on mode,
LS drive circuit 300 and the LS drive circuit 300, which are enabled, in this period is configured to drive output terminal 106, first
Switch 276 is configured to disconnect and second switch 278 is configured to be closed.Correspondingly, the back gate region (example of second transistor Q2
Such as, 265) be coupled to floating lead 203, and with 104 uncoupling of LS voltage supply terminal.During power-down mode, in the phase
Between LS drive circuit 300 be in tri-state or disabled, first switch 276 is configured to closure and second switch 278 is configured
To disconnect.Correspondingly, the back gate region (for example, 265) of second transistor Q2 be coupled to LS voltage supply terminal 104 and with floating
203 uncoupling of lead.
It is consistent with this description, term " being configured to " describe one or more tangible non-transitory elements structure and
Functional characteristic.For example, term " being configured to " can have be designed or be dedicated to execute certain function specifically configure.Example
Such as, it can be activated, activate or power to execute the tangible non-transitory element of certain function, this device if device includes
Part " being configured to " executes the certain function.However term " being configured to " may include it is configurable, be not limited to this narrow sense
Definition.Therefore when being used for outlines device, term " being configured to " does not require described device at any given time
It is all configurable on point.
Herein can be only about a description special characteristic in several embodiments, but this feature can be as can the phase
Other one or more characteristics as prestige with other embodiments combine, and for any given or specific application
All it is advantageous.
Certain features described in the context of separate embodiments can also group in a single embodiment in this specification
It closes and implements.On the contrary, the various features described in the context of single embodiment can also in various embodiments individually
Or implement in any sub-portfolio appropriate.In addition, although can describe feature as working in certain combinations above,
But in some cases, one or more features from combination can be deleted from the combination, and the combination can be with
For the variation of sub-portfolio or sub-portfolio.
Similarly, it although describing operation by particular order in the accompanying drawings, does not need with shown particular order or sequence
Column sequentially execute this operation, and do not need to execute be described operation, to obtain desired as a result, unless describing
This sequence.In some cases, multitasking and parallel processing may be advantageous.In addition, implementation described above
The separation of various system elements in example is not to require such separation in all embodiments.
Within the scope of the claims, in the embodiments described modification be it is possible, and other embodiments be can
Can.
Claims (20)
1. a kind of device, it includes:
P doped substrate, with horizontal surface and the vertical depth extended perpendicular to the horizontal surface；
Output terminal；
NPN structure, along the horizontal surface, the NPN structure includes: the first n doped region, is coupled to the output end
Son；P doped region around the first n doped region and is coupled to the output terminal；And the 2nd n doped region, pass through
The p doped region is separated with the first n doped region；And
Positive-negative-positive structure, along the vertical depth, the positive-negative-positive structure includes the p doped region, the n below the p doped region
Doped layer and the p doped substrate.
2. device according to claim 1, further includes:
Metal oxide semiconductor transistor includes the drain region in the 2nd n doped region；It is adulterated in the first n
Source area in area；Channel region in the p doped region and between the drain region and the source area；And positioning
Square gate structure on the channel region.
3. device according to claim 1, further includes:
Floating lead is coupled to the 2nd n doped region.
4. device according to claim 3, further includes:
First switch is coupled between the p doped region and the output terminal；And
Second switch is coupled between the p doped region and the floating lead.
5. device according to claim 3, further includes:
Voltage supply terminal；And
2nd NPN structure, along the horizontal surface and the neighbouring NPN structure, the 2nd NPN structure includes: that the 3rd n mixes
The floating lead is coupled in miscellaneous area；2nd p doped region around the 3rd n doped region and is coupled to the voltage
Feeding terminal；And the 4th n doped region, it is separated by the 2nd p doped region with the 3rd n doped region, the described 4th
Doped region is coupled to the voltage supply terminal.
6. device according to claim 5, further includes:
Metal oxide semiconductor transistor includes the drain region in the 3rd n doped region；It is adulterated in the 4th n
Source area in area；Channel region in the 2nd p doped region and between the drain region and the source area；And
The gate structure being located in above the channel region.
7. device according to claim 1, further includes:
Drain-extended metal oxide semi conductor transistor includes the drain region of the extension in the 2nd n doped region；
Source area in the first n doped region；In the p doped region and in the drain region of the extension and the source area
Between channel region；And it is located in the gate structure above the channel region.
8. device according to claim 1, wherein the p doped region includes: to be located in the first n doped region and described
The doped channel regions p between 2nd n doped region；Laterally the p around the first n doped region and the 2nd n doped region mixes
Miscellaneous lateral areas；And support and connect the p doping buried layer of the doped channel regions p and p doping lateral areas.
9. device according to claim 1, further includes:
N doped sidewalls laterally surround the p doped region, the adjacent n doped layer of the n doped sidewalls.
10. a kind of integrated circuit, it includes:
Substrate, with horizontal surface；
Voltage supply terminal；
Output terminal；
The first transistor comprising: the first n doped region is coupled to the output terminal；First p doped region, around described
First n doped region and it is coupled to the output terminal；And the 2nd n doped region, by the first p doped region with it is described
The separation of first n doped region；
Second transistor comprising: the 3rd n doped region；2nd p doped region around the 3rd n doped region and is coupled to
The voltage supply terminal；And the 4th n doped region, it is separated by the 2nd p doped region with the 3rd n doped region,
The 4th n doped region is coupled to the voltage supply terminal；And
Floating lead is coupled between the 2nd n doped region and the 3rd n doped region.
11. integrated circuit according to claim 10, wherein the first transistor includes metal-oxide semiconductor (MOS) crystalline substance
Body pipe includes the drain region in the 2nd n doped region；Source area in the first n doped region；Described
Channel region in one p doped region and between the drain region and the source area；And it is located in above the channel region
Gate structure.
12. integrated circuit according to claim 10, wherein the second transistor includes metal-oxide semiconductor (MOS) crystalline substance
Body pipe includes the drain region in the 3rd n doped region；Source area in the 4th n doped region；Described
Channel region in two p doped regions and between the drain region and the source area；And it is located in above the channel region
Gate structure.
13. integrated circuit according to claim 10, wherein the first transistor includes drain-extended metal oxide
Semiconductor transistor includes the drain region of the extension in the 2nd n doped region；Source in the first n doped region
Polar region；Channel region in the first p doped region and between the drain region of the extension and the source area；And it is fixed
Position square gate structure on the channel region.
14. integrated circuit according to claim 10, wherein the second transistor includes drain-extended metal oxide
Semiconductor transistor includes the drain region of the extension in the 3rd n doped region；Source in the 4th n doped region
Polar region；Channel region in the 2nd p doped region and between the drain region of the extension and the source area；And it is fixed
Position square gate structure on the channel region.
15. integrated circuit according to claim 10, further includes:
First switch is coupled between the first p doped region and the output terminal；And
Second switch is coupled between the first p doped region and the floating lead.
16. integrated circuit according to claim 10, wherein the first p doped region includes: to be located in the first n to mix
The doped channel regions p between miscellaneous area and the 2nd n doped region；Laterally mixed around the first n doped region and the 2nd n
The p in miscellaneous area adulterates lateral areas；And support and connect the p doping buried layer of the doped channel regions p and p doping lateral areas.
17. integrated circuit according to claim 10, further includes:
First n adulterates buried layer, and positioning is over the substrate；
2nd n adulterates buried layer, and positioning is isolated over the substrate and with the first n doping buried layer；
First n doped sidewalls, laterally surround the first p doped region, and the first n doped sidewalls are mixed by the first n
Miscellaneous buried layer support；And
2nd n doped sidewalls, laterally surround the 2nd p doped region, and the 2nd n doped sidewalls are mixed by the 2nd n
Miscellaneous buried layer support.
18. a kind of integrated circuit, it includes:
P doped substrate, with horizontal surface and the vertical depth extended perpendicular to the horizontal surface；
High side voltage feeding terminal, that is, HS voltage supply terminal；
Low-pressure side voltage feeding terminal, that is, LS voltage supply terminal；
Output terminal；
HS drive circuit is coupled between the HS voltage supply terminal and the output terminal；And
LS drive circuit comprising the first transistor, second transistor and floating lead, the first transistor include:
It is coupled to the first n doped region of the output terminal, around the first n doped region and is coupled to the of the output terminal
One p doped region, and the 2nd n doped region separated by the first p doped region with the first n doped region；Described second
Transistor includes: the 3rd n doped region, around the 3rd n doped region and is coupled to the 2nd p of the LS voltage supply terminal
Doped region, and the 4th n doped region separated by the 2nd p doped region with the 3rd n doped region, the 4th n mix
It is coupled to the LS voltage supply terminal in miscellaneous area；The floating lead is coupled in the 2nd n doped region and the 3rd n doping
Between area.
19. integrated circuit according to claim 18, further includes:
First positive-negative-positive structure, along the vertical depth, the first positive-negative-positive structure includes the first p doped region, described
The first n doped layer and the p doped substrate below one p doped region；With
Second positive-negative-positive structure, along the vertical depth, the second positive-negative-positive structure includes the 2nd p doped region, described
Two p doped regions lower sections and the 2nd n doped layer being isolated with the first n doped layer and the p doped substrate.
20. integrated circuit according to claim 18, further includes:
First switch is coupled between the first p doped region and the output terminal；And
Second switch is coupled between the first p doped region and the floating lead.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201662301804P | 2016-03-01 | 2016-03-01 | |
| US62/301,804 | 2016-03-01 | ||
| US15/386,252 US10498326B2 (en) | 2016-03-01 | 2016-12-21 | Output driver with power down protection |
| US15/386,252 | 2016-12-21 | ||
| PCT/US2017/020294 WO2017151827A1 (en) | 2016-03-01 | 2017-03-01 | Output drive with power down protection |
Publications (2)
| Publication Number | Publication Date |
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| CN109075215A true CN109075215A (en) | 2018-12-21 |
| CN109075215B CN109075215B (en) | 2022-04-08 |
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| CN201780013156.5A Active CN109075215B (en) | 2016-03-01 | 2017-03-01 | Output driver with power down protection |
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|---|---|
| US (1) | US10498326B2 (en) |
| JP (1) | JP6916536B2 (en) |
| CN (1) | CN109075215B (en) |
| WO (1) | WO2017151827A1 (en) |
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| US10573639B2 (en) * | 2016-02-29 | 2020-02-25 | Globalfoundries Singapore Pte. Ltd. | Silicon controlled rectifier (SCR) based ESD protection device |
| US10283584B2 (en) * | 2016-09-27 | 2019-05-07 | Globalfoundries Inc. | Capacitive structure in a semiconductor device having reduced capacitance variability |
| US20220223723A1 (en) * | 2021-01-14 | 2022-07-14 | Texas Instruments Incorporated | Scr having selective well contacts |
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| CN101405867A (en) * | 2002-09-29 | 2009-04-08 | 先进模拟科技公司 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology |
| US20100103570A1 (en) * | 2008-10-27 | 2010-04-29 | Ming-Hsiang Song | Circuit and Method for Power Clamp Triggered Dual SCR ESD Protection |
| CN102097441A (en) * | 2010-12-17 | 2011-06-15 | 电子科技大学 | SOI (Silicon On Insulator) device for plasma display panel driving chip |
| CN104969355A (en) * | 2013-01-30 | 2015-10-07 | 密克罗奇普技术公司 | DMOS semiconductor device with ESD self-protection and LIN bus driver comprising the same |
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| US5324982A (en) * | 1985-09-25 | 1994-06-28 | Hitachi, Ltd. | Semiconductor memory device having bipolar transistor and structure to avoid soft error |
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| DE60335180D1 (en) | 2003-07-04 | 2011-01-13 | Dialog Semiconductor Gmbh | High voltage interface and control circuit for it |
| US7166876B2 (en) | 2004-04-28 | 2007-01-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOSFET with electrostatic discharge protection structure and method of fabrication |
| EP2028760B1 (en) * | 2007-08-22 | 2020-06-17 | Semiconductor Components Industries, LLC | A low side driver |
| US8344789B2 (en) * | 2010-01-20 | 2013-01-01 | Intersil Americas Inc. | Analog switch with internal device body control |
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2016
- 2016-12-21 US US15/386,252 patent/US10498326B2/en active Active
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- 2017-03-01 JP JP2018546551A patent/JP6916536B2/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101405867A (en) * | 2002-09-29 | 2009-04-08 | 先进模拟科技公司 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology |
| US20100103570A1 (en) * | 2008-10-27 | 2010-04-29 | Ming-Hsiang Song | Circuit and Method for Power Clamp Triggered Dual SCR ESD Protection |
| CN102097441A (en) * | 2010-12-17 | 2011-06-15 | 电子科技大学 | SOI (Silicon On Insulator) device for plasma display panel driving chip |
| CN104969355A (en) * | 2013-01-30 | 2015-10-07 | 密克罗奇普技术公司 | DMOS semiconductor device with ESD self-protection and LIN bus driver comprising the same |
Also Published As
| Publication number | Publication date |
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| JP6916536B2 (en) | 2021-08-11 |
| US10498326B2 (en) | 2019-12-03 |
| CN109075215B (en) | 2022-04-08 |
| US20170257088A1 (en) | 2017-09-07 |
| WO2017151827A8 (en) | 2018-11-01 |
| JP2019511113A (en) | 2019-04-18 |
| WO2017151827A1 (en) | 2017-09-08 |
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