CN109067388B - CML structure output drive stage circuit - Google Patents

CML structure output drive stage circuit Download PDF

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CN109067388B
CN109067388B CN201811009953.9A CN201811009953A CN109067388B CN 109067388 B CN109067388 B CN 109067388B CN 201811009953 A CN201811009953 A CN 201811009953A CN 109067388 B CN109067388 B CN 109067388B
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pmos
resistor
common mode
terminal
transistor
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CN109067388A (en
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徐希
陶成
陈余
季翔宇
付家喜
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Lontium Semiconductor Corp
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Lontium Semiconductor Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
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  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a CML structure output driving stage circuit, which comprises: the transistor comprises a first resistor R1, a second resistor R2, an output common mode clamping circuit M1, a first PMOS (P-channel metal oxide semiconductor) transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a first NMOS (N-channel metal oxide semiconductor) transistor N1, a second NMOS (N-channel metal oxide semiconductor) transistor N2, a third NMOS transistor N3 and a terminating resistor RA. According to the invention, the output common mode clamping circuit is used for controlling the cross-over resistor to output the common mode voltage, so that both the AC/DC mode and the TX power consumption can be optimized; in the circuit implementation, a 'fixed' bottom tail current source N3 and a top tail current source P3 controlled by an output common mode clamp circuit are used, so that the cross-over resistance of the CML in an AC mode is stabilized at a reasonable working voltage, and a termination voltage is not required to be provided; in addition, automatic regulation of the AC/DC mode, which is itself an adaptive TX, can also be implemented.

Description

CML structure output drive stage circuit
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a CML structure output driving stage circuit.
Background
The power consumption and heating problems of the conventional CML structure output stage driving circuit are more and more prominent for chips with continuously reduced dimensions, so that circuit designers continuously research structures for saving power consumption, but many structures are only limited to AC or DC mode, and the compatibility is not strong; or AC/DC, can be operated, but only one mode can save power.
Disclosure of Invention
The invention aims to provide a CML structure output driving stage circuit which realizes power consumption optimization in an AC working mode and a DC working mode.
In order to achieve the purpose, the invention provides the following technical scheme:
a CML architecture output driver stage circuit comprising: the transistor comprises a first resistor (R1), a second resistor (R2), an output common mode clamp circuit (M1), a first PMOS tube (P1), a second PMOS tube (P2), a third PMOS tube (P3), a first NMOS tube (N1), a second NMOS tube (N2), a third NMOS tube (N3) and a termination Resistor (RA), wherein:
one end of the first resistor (R1) and the first end of the third PMOS tube (P3) are connected with a power supply voltage AVdd; the other end of the first resistor (R1) is connected with one end of the second resistor (R2), and the other end of the second resistor (R2) is grounded;
a common end of the first resistor (R1) and the second resistor (R2) is connected with a first end of the output common mode clamp circuit (M1), a second end of the output common mode clamp circuit (M1) is connected with a control end of the third PMOS tube (P3), and a third end of the output common mode clamp circuit (M1) is connected with a second end of the first PMOS tube (P1) and is connected with Out _ N; the fourth end of the output common mode clamping circuit (M1) is connected with the second end of the second PMOS tube (P2) and is connected with Out _ P;
a second end of the third PMOS tube (P3) is respectively connected with a first end of the first PMOS tube (P1) and a first end of the second PMOS tube (P2), a control end of the first PMOS tube (P1) is connected with In _ P, and a control end of the second PMOS tube (P2) is connected with In _ N;
the second end of the first PMOS tube (P1) is connected with the first end of the first NMOS tube (N1), the second end of the second PMOS tube (P2) is connected with the first end of the second NMOS tube (N2), the control end of the first NMOS tube (N1) is connected with the In _ P, and the control end of the second NMOS tube (N2) is connected with the In _ N;
the second end of the first NMOS transistor (N1) is connected with the second end of the second NMOS transistor (N2), the common end of the first NMOS transistor is connected with the first end of the third NMOS transistor (N3), the second end of the third NMOS transistor (N3) is grounded, and a control end of the third NMOS transistor (N3) inputs a second bias voltage Vbn；
The second end of the first PMOS tube (P1) and the second end of the second PMOS tube (P2) pass through the termination resistor (R)A) Connecting;
a second end of the first PMOS pipe (P1) is connected with the Out _ N, and a second end of the second PMOS pipe (P2) is connected with the Out _ P;
the third NMOS transistor (N3) is used as a bottom tail current source to configure the second bias voltage V according to an AC/DC connection modebn(ii) a Said third PMOS transistor (P3) is biased and controlled by said output common mode clamp as a top tail current source, said output common mode clamp forming a feedback loop by comparing a common mode voltage VcomAnd the actual common mode level of the output voltage to obtain a first bias voltage VbpApplying the first bias voltage VbpFeeding back the actual output common mode level to the third PMOS transistor (P3) to adjust the actual output common mode level to the common mode voltage Vcom。
Further, the output common mode clamp circuit includes: a third resistor (R3), a fourth resistor (R4), a capacitor (C), and a first operational amplifier (OP1), wherein:
the third resistor (R3) and the fourth resistor (R4) are equal in resistance;
the inverting input terminal of the first operational amplifier (OP1) is used as the first terminal of the output common-mode clamp circuit (M1) to input the common-mode voltage Vcom(ii) a The non-inverting input end of the first operational amplifier (OP1) is connected with one end of the capacitor (C), and the other end of the capacitor (C) is grounded;
one end of the capacitor (C) is respectively connected with one end of the third resistor (R3) and one end of a fourth resistor (R4), and the other end of the third resistor (R3) is connected with the Out _ N as the fourth end of the output common mode clamping circuit (M1); the other end of the fourth resistor (R3) is used as the third end of the output common mode clamping circuit (M1) and is connected with the Out _ P;
an output terminal of the first operational amplifier (OP1) as a second terminal of the output common mode clamp circuit (M1) outputs the first bias voltage VbpAnd the control end of the third PMOS tube (P3).
Further, the first end of the first PMOS transistor (P1), the second PMOS transistor (P2), and the third PMOS transistor (P3) is a source, the second end is a drain, and the third end is a gate.
Furthermore, the first end of the first NMOS transistor (N1), the second NMOS transistor (N2), and the third NMOS transistor (N3) is a drain, the second end is a source, and the third end is a gate.
Further, the method also comprises the following steps: a swing controller (M2), the swing controller (M2) comprising: a first end, a second end, and a third end, wherein:
a first terminal of the swing controller (M2) is connected to a second terminal of the output common mode clamp circuit (M1) and receives the first bias voltage VbpA second terminal of the swing controller (M2) receives a target swing voltage VmbfA third terminal of the swing controller (M2) outputs the second bias voltage VbnThe control end of the third NMOS tube (N3) is connected;
the swing controller (M2) is used for adjusting the V according to an AC/DC connection modebn。
Further, the swing controller (M2) comprises: a fourth PMOS transistor (P4), a fifth PMOS transistor (P5), a sixth PMOS transistor (P6), a fourth NMOS transistor (N4), a second operational amplifier (OP2) and a swing resistor (R)B) Wherein:
the first end of the fourth PMOS tube (P4), the first end of the fifth PMOS tube (P5) and the first end of the sixth PMOS tube (P6) are connected with the supply voltage AVdd;
a control end of the fourth PMOS tube (P4) is connected as a first end of the swing controller (M2) and a second end of the output common mode clamping circuit (M1) and receives the first bias voltage Vbp(ii) a The second end of the fourth PMOS tube (P4) is connected with the second end of the fifth PMOS tube (P5), and the common end of the fourth PMOS tube and the fifth PMOS tube is respectively connected with the swing resistor (R)B) Is connected to the inverting input of said second operational amplifier (OP 2);
the swing resistor (R)B) The other end of the second NMOS transistor (N4) is connected with the second end of the fourth NMOS transistor (N4) and is grounded; the first end of the fourth NMOS transistor (N4) is connected with the second end and the control end of the sixth PMOS transistor (P6); the control end of the fifth PMOS tube (P5) is connected with the control end of the sixth PMOS tube (P6);
the control end of the fourth NMOS transistor (N4) is connected with the output end of the second operational amplifier (OP2), and the common end of the fourth NMOS transistor is used as the swingThe third terminal of the controller (M2) outputs the second bias voltage Vbn；
A positive input terminal of the second operational amplifier (OP2) as a second terminal of the swing controller (M2) receives a target swing voltage Vmbf。
Further, the first end of the fourth PMOS transistor (P4), the fifth PMOS transistor (P5), and the sixth PMOS transistor (P6) is a source, the second end is a drain, and the third end is a gate.
Furthermore, the first end of the fourth NMOS transistor (N4) is a drain, the second end is a source, and the third end is a gate.
As can be seen from the above technical solutions, compared with the prior art, the present invention discloses a CML structure output driver stage circuit, including: the circuit comprises a first resistor R1, a second resistor R2, an output common mode clamp circuit M1, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3 and a terminating resistor RAThrough a CML structure driving circuit of an upper current double-tail current source, a lower current double-tail current source, a complete bridging resistor and an output common mode clamping circuit, when an AC/DC mode is switched, a first PMOS tube P1, a second PMOS tube P2 and a third PMOS tube P3 can be automatically closed, and only the bottom tail current needs to be actively configured and increased or reduced by one time. According to the invention, the output common mode clamping circuit is used for controlling the cross-over resistor to output the common mode voltage, so that both the AC/DC mode and the TX power consumption can be optimized; in the circuit implementation, a fixed bottom tail current source N3 and a top tail current source P3 controlled by an output common mode clamp circuit are used, so that the cross-over resistance of the CML in an AC mode is stabilized at a reasonable working voltage, and a termination voltage is not required to be provided; in addition, automatic regulation of the AC/DC mode, which is itself an adaptive TX, can also be implemented.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a block diagram of a transmitting end module of a high-speed multimedia interface chip, which is most common in the prior art;
FIG. 2 is a circuit diagram of a CML-structured output driver stage most commonly used in the prior art;
FIG. 3 is a waveform diagram of an output signal during AC coupling in the prior art;
FIG. 4 is a waveform diagram of an output signal during DC coupling in the prior art;
FIG. 5 is a schematic diagram of the operation principle of a conventional AC mode two-tail current source in the prior art;
FIG. 6 is a waveform diagram of an output signal corresponding to a conventional AC mode two-tailed current source in the prior art;
FIG. 7 is a schematic diagram of a conventional DC mode jumper resistor in the prior art;
FIG. 8 is a circuit diagram of a CML output driver stage according to an embodiment of the present invention;
fig. 9 is a schematic diagram of an output common mode clamp circuit M1 according to an embodiment of the present invention;
FIG. 10 is a circuit diagram of an output driver stage with another CML architecture according to an embodiment of the present invention;
fig. 11 is a schematic diagram of a swing controller M2 according to an embodiment of the present invention.
Detailed Description
As shown in fig. 1, a structure diagram of a sending end module of a high speed multimedia interface chip, which is the most common in the prior art, includes: the parallel-to-serial converter 1, the front driver 2, the driver stage 3, the terminating resistor 4 and the electrostatic protection circuit 5, it should be noted that the capacitors C1 and C2 in fig. 1 may or may not be according to different communication protocols, for example, DP, VB1 protocol is mandatory, HDMI protocol is not limited, and therefore may or may not be present; the driver stage 3 typically uses the CML shown in fig. 2 as an output driver stage circuit, where the capacitors can be operated normally with or without. Fig. 3 is a waveform diagram of an output signal during AC coupling, and fig. 4 is a waveform diagram of an output signal during DC coupling, for example: terminating resistorRtermThe resistance is 50 ohms (basically 40-60 ohms), and when high-speed data is transmitted, the equivalent resistance of the TX resistance and the RX resistance of the output node of the CML differential pair is RtermFor example, a single-ended output swing of 400mV requires 16mA for the tail current I of fig. 2, at 25 ohms/2.
The output driving stage of the conventional CML structure has a simple structure, and different coupling modes have strong universality but large power consumption.
Some designers have improved TX power consumption for AC-coupled mode of operation, but only for AC mode, or, although two modes of operation may be configured, only AC mode is a power-saving module, and DC mode is restored to normal CML structure (for RX DC connection mode using a cross-over resistor, it is considered AC mode in this analysis). The above AC coupling method uses a two-tail current source method, as shown in fig. 5, which is a schematic diagram of the working principle of a conventional AC mode two-tail current source. As shown in FIG. 5, all resistors are RtermWhen the N1 and P2 switches are turned off and the P1 and N2 switches are turned off, I/4 current flows through the cross-over resistor, Vdiff is I + Rterm/2, and the waveform of the output signal corresponding to the conventional AC mode two-tail current source is as shown in fig. 6, comparing fig. 6 with fig. 3, only the common mode position is different, and the differential mode voltage values are the same, so that the purpose of outputting the signal with the same swing by using only half power consumption (AVdd + I/2) is achieved.
Another designer has optimized the DC coupling operation mode, for example, changing the TX termination resistance from single-ended connection to cross-connection is one of the measures, but the cross-connection resistance of the CML structure usually has no termination voltage in the AC mode and cannot normally operate, as shown in fig. 7, which is a schematic diagram of the operation principle of the conventional DC mode cross-connection resistance. Although the current across the resistor is I, it is not reduced, but is drawn from the RX side. In general, TX is a portable device and has a severe requirement for power consumption, and RX is a television or computer monitor and has sufficient power supply capability, so that the purpose of saving the power consumption of the TX end is achieved, and a waveform diagram of an output signal is shown in fig. 3.
Although the above improvement for TX power consumption in AC-coupled mode of operation can be switched in a configurable manner and can use a two-tailed current source in AC mode (and DC mode of RX bridge resistor), it can also work normally in normal DC mode but returns to normal CML architecture without any optimization.
For the most common current switching mode of the single-tail current source in fig. 2, the current efficiency is low, TX power consumption is too large, and it is difficult for some circuits that respectively optimize power consumption in the AC mode and the DC mode to be compatible with both modes. Therefore, the invention aims to design a CML structure output driving stage circuit which can be applied to AC/DC modes and can realize power consumption optimization.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
As shown in fig. 8, an embodiment of the present invention provides a CML structured output driver stage circuit, which specifically includes: the circuit comprises a first resistor R1, a second resistor R2, an output common mode clamp circuit M1, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3 and a terminating resistor RAWherein:
one end of the first resistor R1 and a first end of the third PMOS transistor P3 are connected to a power supply voltage AVdd; the other end of the first resistor R1 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is grounded; a common terminal of the first resistor R1 and the second resistor R2 is connected to a first terminal of the output common mode clamp M1, a second terminal of the output common mode clamp M1 is connected to a control terminal of the third PMOS transistor P3, and a third terminal of the output common mode clamp M1 is connected to a second terminal of the first PMOS transistor P1 and to Out _ N; the fourth terminal of the output common mode clamp M1 is connected to the second terminal of the second PMOS transistor P2 and to Out _ P.
A second end of the third PMOS transistor P3 is connected to a first end of the first PMOS transistor P1 and a first end of the second PMOS transistor P2, respectively, a control end of the first PMOS transistor P1 is connected to In _ P, and a control end of the second PMOS transistor P2 is connected to In _ N; a second end of the first PMOS transistor P1 is connected to a first end of the first NMOS transistor N1, a second end of the second PMOS transistor P2 is connected to a first end of the second NMOS transistor N2, a control end of the first NMOS transistor N1 is connected to the In _ P, and a control end of the second NMOS transistor N2 is connected to the In _ N.
A second terminal of the first NMOS transistor N1 is connected to a second terminal of the second NMOS transistor N2, a common terminal thereof is connected to a first terminal of the third NMOS transistor N3, a second terminal of the third NMOS transistor N3 is grounded, and a control terminal of the third NMOS transistor N3 receives a second bias voltage Vbn(ii) a The second end of the first PMOS transistor P1 and the second end of the second PMOS transistor P2 pass through the termination resistor RAConnecting; a second terminal of the first PMOS transistor P1 is connected to the Out _ N, and a second terminal of the second PMOS transistor P2 is connected to the Out _ P; the third NMOS transistor N3 is used as a bottom tail current source to configure the second bias voltage V according to the AC/DC connection modebn(ii) a The third PMOS transistor P3 is biased and controlled as a top tail current source by the output common mode clamp forming a feedback loop by comparing a common mode voltage VcomAnd the actual common mode level of the output voltage to obtain a first bias voltage VbpApplying the first bias voltage VbpFeeding back the actual output common mode level to the third PMOS transistor P3 to adjust the actual output common mode level to the common mode voltage Vcom。
It should be noted that, since the total current of the whole differential pair is extracted from the top tail current source and finally flows to the bottom tail current source, no other branch provides or extracts current, the top tail current source is automatically adjusted to be equivalent to the bottom current source after the feedback loop is stabilized; in addition, the voltage division of the first resistor R1 and the second resistor R2 can control the common-mode voltage VcomUsually, V iscomBit set at AVdd/2Put (or slightly under), i.e. in the present embodiment, set R1 ═ R2.
As shown in fig. 9, the output common mode clamp circuit includes: third resistance R3, fourth resistance R4, capacitor C and first operational amplifier OP1, wherein:
the third resistor R3 and the fourth resistor R4 have the same resistance; the inverting input terminal of the first operational amplifier OP1 is used as the first terminal of the output common mode clamp M1, and the common mode voltage V is input theretocom(ii) a The non-inverting input terminal of the first operational amplifier OP1 is connected to one terminal of the capacitor C, and the other terminal of the capacitor C is grounded.
One end of the capacitor C is connected to one end of the third resistor R3 and one end of the fourth resistor R4, respectively, and the other end of the third resistor R3 is connected to the Out _ N as the fourth end of the output common mode clamp circuit M1; the other end of the fourth resistor R3 is connected to the Out _ P as the third end of the output common mode clamp M1; an output terminal of the first operational amplifier OP1 is used as a second terminal of the output common mode clamp M1 to output the first bias voltage VbpAnd is connected with the control end of the third PMOS transistor P3.
The first, second, and third PMOS transistors P1, P2, and P3 have a source at a first end, a drain at a second end, and a gate at a third end. The first end of the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3 is a drain, the second end is a source, and the third end is a gate.
In fig. 8, the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, and the second NMOS transistor N2 are switches, and the third PMOS transistor P3 and the third NMOS transistor N3 are current sources, wherein: the third PMOS transistor P3 is a top tail current source; the third NMOS transistor N3 is a bottom tail current source. Terminating resistor RAUsing a full crossover mode, and RA＝2*RtermNo termination voltage is provided.
The third resistor R3 and the fourth resistor R4 are large resistors at least greater than 50k ohms in order to reduce the pair of terminating resistors RAThe parallel effect of (c). When V iscomAt AVdd/2, if the output common-mode voltage is greater than VcomThen V isbpRising, controlling the current of the third PMOS pipe P3 to be reduced, and reducing the output common-mode voltage; and vice versa, namely:
first, when in AC mode, the bottom tail current source N3 is configured as I/2, and the output common mode clamp M1 can substantially form the equivalent two-tail current source operation of FIG. 5 (the TX of FIG. 5 does not require a termination voltage) by stabilizing the output common mode voltage at AVdd/2 through the above negative feedback;
second, in DC mode, the pull-up capability of the RX termination pulls the common mode voltage near AVdd (AVdd-I R)term/2), well above AVdd/2, the output common mode clamp negatively feeds back to reduce the top tail current source P3 until completely turned off. At this time, the first PMOS transistor P1, the second PMOS transistor P2, and the third PMOS transistor P3 fail, and the circuit automatically adjusts to the cross-connected single-tail current source operation mode as shown in fig. 7.
Further, as shown in fig. 10, an output driver stage circuit with a CML structure according to another embodiment of the present invention further includes, on the basis of fig. 8: a swing controller M2, wherein the swing controller M2 comprises: a first end, a second end, and a third end, wherein:
a first terminal of the swing controller M2 is connected to a second terminal of the output common mode clamp M1, and receives the first bias voltage VbpThe second end of the swing controller M2 receives the target swing voltage VmbfThe third terminal of the swing controller M2 outputs the second bias voltage VbnThe control end of the third NMOS transistor N3 is connected;
the swing controller M2 is used for adjusting the V according to the AC/DC connection modebn。
Further, as shown in fig. 11, the swing controller M2 includes: a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a fourth NMOS transistor N4, a second operational amplifier OP2, and a swing resistor RBWherein:
a first terminal of the fourth PMOS transistor P4, a first terminal of the fifth PMOS transistor P5, and a first terminal of the sixth PMOS transistor P6 are connected to the power supply voltage AVdd; the fourth PA control terminal of the MOS transistor P4 is connected to the first terminal of the swing controller M2 and the second terminal of the output common mode clamp M1, and receives the first bias voltage Vbp(ii) a A second terminal of the fourth PMOS transistor P4 and a second terminal of the fifth PMOS transistor P5 are connected, and a common terminal thereof is connected to the swing resistor RBAnd is connected to the inverting input terminal of the second operational amplifier OP 2.
The above-mentioned swing resistor RBThe other end of the second NMOS transistor N4 is connected to the second end of the fourth NMOS transistor N4, and is grounded; a first terminal of the fourth NMOS transistor N4 is connected to a second terminal and a control terminal of the sixth PMOS transistor P6; a control terminal of the fifth PMOS transistor P5 is connected to a control terminal of the sixth PMOS transistor P6; a control terminal of the fourth NMOS transistor N4 is connected to an output terminal of the second operational amplifier OP2, and a common terminal thereof is used as a third terminal of the swing controller M2 to output the second bias voltage Vbn(ii) a A positive input terminal of the second operational amplifier OP2 as a second terminal of the swing controller M2 receives a target swing voltage Vmbf。
The first terminal of the fourth PMOS transistor P4, the fifth PMOS transistor P5, and the sixth PMOS transistor P6 is a source, the second terminal thereof is a drain, and the third terminal thereof is a gate. The first terminal of the fourth NMOS transistor N4 is a drain, the second terminal is a source, and the third terminal is a gate.
Specifically, as shown in fig. 11, the actual output swing is determined by the sum of the current values of the third PMOS transistor P3 and the third NMOS transistor N3. In DC mode, IN3＝I，IP30; in AC mode, IN3＝IP3I/2. The sum of the current values of the two is the same, and the swing is also the same, therefore, only one control circuit is needed to ensure that the sum of the two is always equal to the target current I, so that the system can automatically adjust the bottom tail current source P3 in the AC/DC different modes, and specifically, the implementation of the controller circuit capable of achieving the above functions is many, as shown in fig. 11, which exemplifies an embodiment:
wherein, the fourth PMOS transistor P4 and the fourth NMOS transistor N4 are respectively 1/N times of the width-to-length ratio of the third PMOS transistor P3 and the third NMOS transistor N3 in fig. 10, and the fifth PMOS transistor P5 and the sixth PMOS transistor P6A 1:1 current mirror. A non-inverting input terminal (+) of the operational amplifier inputs a target swing voltage, such as 400mV, and flows through a swing resistor RB＝n*RtermThe current of/2 is 1/n times of the sum of the two tail currents, and the voltage generating the actual swing amplitude is (I)N3+IP3)*RtermAnd 2, inputting the negative phase input end (-) of the operational amplifier for comparison, and outputting the result to control the bottom tail current source N3 to automatically adjust the current value in the AC/DC mode.
In the original basic process, when the AC/DC mode is switched, the first PMOS transistor P1, the second PMOS transistor P2, and the third PMOS transistor P3 may be turned off automatically, and only the active configuration of the bottom tail current needs to be increased or decreased by one time. Otherwise, the swing may be inconsistent in different modes. The benefit of adding a controller for this "only configuration needed" parameter is that the entire system can be made a fully adaptive model. Of course, if this optimization is not used, the basic core circuitry can still operate. But only the parameter configuration according to the DC/AC mode.
The double-tail current source CML provided by the embodiment of the invention simultaneously uses the bridging resistor, and controls the bridging resistor to output the common mode voltage by using the output common mode clamping circuit, so that the TX power consumption can be optimized in both an AC/DC mode; in the circuit implementation, a fixed bottom tail current source N3 and a top tail current source P3 controlled by an output common mode clamp circuit are used, so that the cross-over resistance of the CML in an AC mode is stabilized at a reasonable working voltage, and a termination voltage is not required to be provided; in addition, automatic regulation of the AC/DC mode, which is itself an adaptive TX, can also be implemented.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (7)

1. A CML architecture output driver stage circuit, comprising: the transistor comprises a first resistor (R1), a second resistor (R2), an output common mode clamping circuit (M1), a first PMOS (P1), a second PMOS (P2), a third PMOS (P3), a first NMOS (N1), a second NMOS (N2), a third NMOS (N3) and a terminating resistor (R3525)A) -a swing controller (M2), the swing controller (M2) comprising: a first end, a second end, and a third end, wherein:
one end of the first resistor (R1) and the first end of the third PMOS tube (P3) are connected with a power supply voltage AVdd; the other end of the first resistor (R1) is connected with one end of the second resistor (R2), and the other end of the second resistor (R2) is grounded;
a common end of the first resistor (R1) and the second resistor (R2) is connected with a first end of the output common mode clamp circuit (M1), a second end of the output common mode clamp circuit (M1) is connected with a control end of the third PMOS tube (P3), and a third end of the output common mode clamp circuit (M1) is connected with a second end of the first PMOS tube (P1) and is connected with Out _ N; the fourth end of the output common mode clamping circuit (M1) is connected with the second end of the second PMOS tube (P2) and is connected with Out _ P;
a second end of the third PMOS tube (P3) is respectively connected with a first end of the first PMOS tube (P1) and a first end of the second PMOS tube (P2), a control end of the first PMOS tube (P1) is connected with In _ P, and a control end of the second PMOS tube (P2) is connected with In _ N;
the second end of the first PMOS tube (P1) is connected with the first end of the first NMOS tube (N1), the second end of the second PMOS tube (P2) is connected with the first end of the second NMOS tube (N2), the control end of the first NMOS tube (N1) is connected with the In _ P, and the control end of the second NMOS tube (N2) is connected with the In _ N;
the second end of the first NMOS tube (N1) is connected with the second end of the second NMOS tube (N2), the common end of the first NMOS tube is connected with the first end of the third NMOS tube (N3), the second end of the third NMOS tube (N3) is grounded, and a second bias voltage V is input into the control end of the third NMOS tube (N3)bn；
The second end of the first PMOS tube (P1) and the second end of the second PMOS tube (P2) pass through the terminating resistor (R)A) Connecting;
a second end of the first PMOS pipe (P1) is connected with the Out _ N, and a second end of the second PMOS pipe (P2) is connected with the Out _ P;
the third NMOS transistor (N3) is used as a bottom tail current source to configure the second bias voltage V according to an AC/DC connection modebn(ii) a Said third PMOS transistor (P3) is biased and controlled by said output common mode clamp as a top tail current source, said output common mode clamp forming a feedback loop by comparing a common mode voltage VcomAnd the actual common mode level of the output voltage to obtain a first bias voltage VbpApplying the first bias voltage VbpFeeding back to the third PMOS transistor (P3) to adjust the actual output common mode level to the common mode voltage Vcom；
A first terminal of the swing controller (M2) is connected to a second terminal of the output common mode clamp circuit (M1) and receives the first bias voltage VbpA second terminal of the swing controller (M2) receives a target swing voltage VmbfA third terminal of the swing controller (M2) outputs the second bias voltage VbnThe control end of the third NMOS tube (N3) is connected;
the swing controller (M2) is used for adjusting the V according to an AC/DC connection modebn。
2. The circuit of claim 1, wherein the output common mode clamp circuit comprises: a third resistor (R3), a fourth resistor (R4), a capacitor (C), and a first operational amplifier (OP1), wherein:
the third resistor (R3) and the fourth resistor (R4) are equal in resistance;
an inverting input terminal of the first operational amplifier (OP1) is used as a first terminal of the output common mode clamp circuit (M1) to input the common mode voltage Vcom(ii) a The non-inverting input end of the first operational amplifier (OP1) is connected with one end of the capacitor (C), and the other end of the capacitor (C) is grounded;
one end of the capacitor (C) is respectively connected with one end of the third resistor (R3) and one end of a fourth resistor (R4), and the other end of the third resistor (R3) is connected with the Out _ N as the fourth end of the output common mode clamping circuit (M1); the other end of the fourth resistor (R4) is used as the third end of the output common mode clamping circuit (M1) and is connected with the Out _ P;
an output terminal of the first operational amplifier (OP1) as a second terminal of the output common mode clamp circuit (M1) outputs the first bias voltage VbpAnd the control end of the third PMOS tube (P3).
3. The circuit of claim 1, wherein the first PMOS transistor (P1), the second PMOS transistor (P2), and the third PMOS transistor (P3) have a source at a first terminal, a drain at a second terminal, and a gate at a third terminal.
4. The circuit of claim 1, wherein the first terminal of the first NMOS transistor (N1), the second NMOS transistor (N2), and the third NMOS transistor (N3) is a drain, the second terminal is a source, and the third terminal is a gate.
5. According to claim 1The circuit described above, wherein the swing controller (M2) includes: a fourth PMOS transistor (P4), a fifth PMOS transistor (P5), a sixth PMOS transistor (P6), a fourth NMOS transistor (N4), a second operational amplifier (OP2) and a swing resistor (R)B) Wherein:
the first end of the fourth PMOS tube (P4), the first end of the fifth PMOS tube (P5) and the first end of the sixth PMOS tube (P6) are connected with the supply voltage AVdd;
a control end of the fourth PMOS tube (P4) is connected as a first end of the swing controller (M2) and a second end of the output common mode clamping circuit (M1) and receives the first bias voltage Vbp(ii) a The second end of the fourth PMOS tube (P4) and the second end of the fifth PMOS tube (P5) are connected, and the common ends of the fourth PMOS tube and the fifth PMOS tube are respectively connected with the swing resistor (R)B) Is connected to the inverting input of said second operational amplifier (OP 2);
the swing resistance (R)B) The other end of the second NMOS transistor (N4) is connected with the second end of the fourth NMOS transistor (N4) and is grounded; the first end of the fourth NMOS transistor (N4) is connected with the second end and the control end of the sixth PMOS transistor (P6); the control end of the fifth PMOS tube (P5) is connected with the control end of the sixth PMOS tube (P6);
the control end of the fourth NMOS transistor (N4) is connected with the output end of the second operational amplifier (OP2), and the common end of the fourth NMOS transistor is used as the third end of the swing controller (M2) to output the second bias voltage Vbn；
The positive input end of the second operational amplifier (OP2) is used as the second end of the swing controller (M2) to receive the target swing voltage Vmbf。
6. The circuit of claim 5, wherein the first terminals of the fourth PMOS transistor (P4), the fifth PMOS transistor (P5) and the sixth PMOS transistor (P6) are source electrodes, the second terminals are drain electrodes, and the third terminals are gate electrodes.
7. The circuit as claimed in claim 5, wherein the first terminal of the fourth NMOS transistor (N4) is a drain, the second terminal is a source, and the third terminal is a gate.
CN201811009953.9A 2018-08-31 2018-08-31 CML structure output drive stage circuit Active CN109067388B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6340909B1 (en) * 1998-01-30 2002-01-22 Rambus Inc. Method and apparatus for phase interpolation
CN101171537A (en) * 2005-03-09 2008-04-30 菲尼萨公司 Interconnect mechanism for connecting a laser driver to a laser
EP2590320A2 (en) * 2011-11-01 2013-05-08 NeoEnergy Microelectronic, Inc. Switching system and method for control thereof
CN204481788U (en) * 2015-04-07 2015-07-15 电子科技大学 A kind of LVDS drive circuit suppressing output common mode to fluctuate

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2011033708A1 (en) * 2009-09-18 2013-02-07 パナソニック株式会社 Driver circuit and video system
JP2015128236A (en) * 2013-12-27 2015-07-09 キヤノン株式会社 Differential signal drive circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6340909B1 (en) * 1998-01-30 2002-01-22 Rambus Inc. Method and apparatus for phase interpolation
CN101171537A (en) * 2005-03-09 2008-04-30 菲尼萨公司 Interconnect mechanism for connecting a laser driver to a laser
EP2590320A2 (en) * 2011-11-01 2013-05-08 NeoEnergy Microelectronic, Inc. Switching system and method for control thereof
CN204481788U (en) * 2015-04-07 2015-07-15 电子科技大学 A kind of LVDS drive circuit suppressing output common mode to fluctuate

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