CN109065605A - Schottky diode and preparation method thereof - Google Patents
Schottky diode and preparation method thereof Download PDFInfo
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- CN109065605A CN109065605A CN201810876950.9A CN201810876950A CN109065605A CN 109065605 A CN109065605 A CN 109065605A CN 201810876950 A CN201810876950 A CN 201810876950A CN 109065605 A CN109065605 A CN 109065605A
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- 238000002360 preparation method Methods 0.000 title abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 105
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 105
- 239000010703 silicon Substances 0.000 claims abstract description 105
- 229910052751 metal Inorganic materials 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 41
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 17
- 238000000407 epitaxy Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000010936 titanium Substances 0.000 claims description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- 230000002708 enhancing effect Effects 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims 1
- 238000000034 method Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 125000004494 ethyl ester group Chemical group 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
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Abstract
The embodiment of the present invention provides a kind of Schottky diode and preparation method thereof, the Schottky diode includes: silicon epitaxial wafer, at least one groove is formed in the middle part of the silicon epitaxial wafer, the edge positioned at the middle part opposite sides of the silicon epitaxial wafer is respectively formed with the first notch and the second notch；Oxide layer；Polysilicon layer；Dielectric layer；Anode metal layer, it is set on the dielectric layer and extends in the schottky junctions contact hole of the dielectric layer, the edge of the opposite sides of the anode metal layer is respectively formed with third notch and the 4th notch, and the third notch is in the region projected where being located at first notch with projection of the 4th notch on the silicon epitaxial wafer on the silicon epitaxial wafer and in the region where second notch；Cathode metal layer；Projection of the schottky junctions contact hole on the silicon epitaxial wafer covers at least one described groove.The embodiment of the present invention can be with optimised devices pressure resistance.
Description
Technical field
The present invention relates to technical field of semiconductor device more particularly to a kind of Schottky diodes and a kind of Schottky two
The production method of pole pipe.
Background technique
Schottky diode is usually the more preferably selection of high-frequency electronic application, since they have high switching speed
With low positive (on state) pressure drop, low forward conduction energy loss is very crucial.But up to date, most of applications
Silicon substrate Schottky diode all receives the limitation of the operating voltage lower than 100V.All the time, Schottky diode is reversed
Blocking voltage all receives the limitation of the voltage more much lower than 200V.This is partly due to work as reverse blocking capability close to 200V
When, the forward voltage drop or forward conduction voltage of Schottky diode are allowed to close to the forward voltage drop of PIN diode in the application
Efficiency it is lower.It is, therefore, desirable to provide a kind of Schottky diode and preparation method thereof for capableing of optimised devices pressure resistance.
Summary of the invention
To solve the above problems, the present invention provides a kind of Schottky diode and preparation method thereof, it can be resistance to optimised devices
Pressure.
Specifically, a kind of Schottky diode provided in an embodiment of the present invention, comprising: silicon epitaxial wafer, the silicon epitaxial wafer
Middle part be formed at least one groove, the edge positioned at the middle part opposite sides of the silicon epitaxial wafer is respectively formed with
One notch and the second notch；Oxide layer covers surface and first notch and described second of at least one groove
The surface of notch；Polysilicon layer fills the space in addition to the oxide layer of at least one groove；Dielectric layer, setting
In the upper surface of the silicon epitaxial wafer and the oxide layer；Anode metal layer is set on the dielectric layer and extends to Xiao Te
The bottom of the schottky junctions contact hole is covered in base contact hole, wherein the schottky junctions contact hole through the dielectric layer and
Projection on the silicon epitaxial wafer covers at least one described groove, the edge difference of the opposite sides of the anode metal layer
It is formed with third notch and the 4th notch, projection and fourth notch of the third notch on the silicon epitaxial wafer are in institute
It states in the region in the region where the projection on silicon epitaxial wafer is located at first notch and where second notch；
And cathode metal layer, it is set to the lower surface of the silicon epitaxial wafer.
The present invention in one embodiment, the silicon epitaxial wafer includes silicon substrate and being set on the silicon substrate
Silicon epitaxy layer.
The present invention in one embodiment, at least one described groove, first notch and second notch
It is formed in the silicon epitaxy layer.
The present invention in one embodiment, the bottom minimum point of at least one groove, first notch
The distance of the upper surface of silicon epitaxy layer described in the bottom perigee distance of bottom minimum point and second notch is 1~2.5 micro-
Rice.
The present invention in one embodiment, the number of the groove included by least one described groove is more
It is a.
The present invention in one embodiment, in the multiple groove between two grooves of arbitrary neighborhood between
Away from equal.
The present invention in one embodiment, in the multiple groove between two grooves of arbitrary neighborhood between
Away from being 1~2.75 micron.
The present invention in one embodiment, the material of the oxide layer is silica, the material of the dielectric layer
For plasma enhancing ethyl orthosilicate.
The present invention in one embodiment, the material of the anode metal layer is titanium, the material of the cathode metal layer
Matter is titanium, nickel or silver.
On the other hand, the production method of a kind of Schottky diode provided in an embodiment of the present invention, comprising steps of cleaning silicon
Epitaxial wafer；Growth obtains the first oxide layer on the silicon epitaxial wafer；Etch first oxide layer and the silicon epitaxial wafer with
Form at least one groove, the first notch and the second notch, wherein at least one described groove, first notch and described
Second notch is through first oxide layer and protrudes into inside the silicon epitaxial wafer, at least one described groove is formed in described
The middle part of silicon epitaxial wafer, first notch and second notch be respectively formed in the silicon epitaxial wafer be located at the middle part
The edge of opposite sides；Table on the surface of at least one groove, the surface of first notch and second notch
Length of looking unfamiliar obtains the second oxide layer；Polysilicon layer is formed in first oxide layer and second oxide layer, wherein described
Polysilicon layer fills the space in addition to second oxide layer of at least one groove；Etch the polysilicon layer and institute
The first oxide layer is stated, to remove the portion for protruding from the silicon epitaxial wafer upper surface of the polysilicon layer and first oxide layer
Point；On the silicon epitaxial wafer and the oxide layer formed dielectric layer and make the dielectric layer extend to first notch and
The bottom of first notch and second notch is covered in second notch；The dielectric layer is etched to form Xiao Te
Base contact hole, wherein described in the schottky junctions contact hole is covered through the dielectric layer and in the projection on the silicon epitaxial wafer
At least one groove；Anode metal layer is formed on the dielectric layer and the anode metal layer is made to extend to the Schottky
The bottom of the schottky junctions contact hole is covered in contact hole；The anode metal layer is etched to form third notch and the 4th and lack
Mouthful, wherein the third notch and the 4th notch are respectively formed in the edge of the opposite sides of the anode metal layer, institute
Projection and fourth notch projection on the silicon epitaxial wafer of the third notch on the silicon epitaxial wafer is stated to be located at
In region in region where first notch and where second notch；And in the lower surface of the silicon epitaxial wafer
Cathode metal layer is formed, so that the Schottky diode be made.
The embodiment of the present invention can be realized it is following the utility model has the advantages that Schottky diode provided in an embodiment of the present invention and its
Production method can optimize the pressure resistance of Schottky diode by optimised devices structure.
Detailed description of the invention
Fig. 1 is the partial profile structure of the active region of Schottky diode in one embodiment of the invention.
Fig. 2A is that the obtained device of step 1 of the production method of Schottky diode in one embodiment of the invention is active
The partial profile structure in region.
Fig. 2 B is that the obtained device of step 2 of the production method of Schottky diode in one embodiment of the invention is active
The partial profile structure in region.
Fig. 2 C is that the obtained device of step 3 of the production method of Schottky diode in one embodiment of the invention is active
The partial profile structure in region.
Fig. 2 D is that the obtained device of step 4 of the production method of Schottky diode in one embodiment of the invention is active
The partial profile structure in region.
Fig. 2 E is that the obtained device of step 5 of the production method of Schottky diode in one embodiment of the invention is active
The partial profile structure in region.
Fig. 2 F is that the obtained device of step 6 of the production method of Schottky diode in one embodiment of the invention is active
The partial profile structure in region.
Fig. 2 G is that the obtained device of step 7 of the production method of Schottky diode in one embodiment of the invention is active
The partial profile structure in region.
Fig. 2 H is that the obtained device of step 8 of the production method of Schottky diode in one embodiment of the invention is active
The partial profile structure in region.
Fig. 2 I is that the obtained device of step 9 of the production method of Schottky diode in one embodiment of the invention is active
The partial profile structure in region.
Fig. 2 J is that the obtained device of step 10 of the production method of Schottky diode in one embodiment of the invention has
The partial profile structure of source region.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
As shown in Figure 1, a kind of part of the active region for Schottky diode 100 that one embodiment of the present of invention provides
Structural profile illustration, Schottky diode 100 specifically include that silicon epitaxial wafer 110, oxide layer 120, polysilicon layer 130, medium
Layer 140, anode metal layer 150 and cathode metal layer 160.
Wherein, the middle part of silicon epitaxial wafer 110 for example forms at least one groove 115 (such as 4 ditches as shown in Figure 1
Slot 115), the edge positioned at middle part opposite sides (left and right side of example as shown in figure 1) of silicon epitaxial wafer 110 is respectively formed with
One notch 117 and the second notch 119.Wherein, the opening of each groove 115 is respectively facing the upper surface US of silicon epitaxial wafer 110.
The cross sectional shape of first notch 117 is for example L-shaped (as shown in fig. 1), and the cross sectional shape of the second notch 119 is for example in the inverse time
Needle be rotated by 90 ° after " L " type (as shown in fig. 1).Second notch 119 is for example symmetrical set with the first notch 117
The edge of the middle part opposite sides of silicon epitaxial wafer 110.
Oxide layer 120 for example covers surface and the first notch 117 and the second notch 119 of at least one groove 115
Surface.
Polysilicon layer 130 for example fills the space except the removing oxide layer 120 of at least one groove 115.
Dielectric layer 140 is for example set to the upper surface US of silicon epitaxial wafer 110 and oxide layer 120.
Anode metal layer 150 is for example set on dielectric layer 140 and extends in schottky junctions contact hole CH to cover Xiao Te
The bottom of base contact hole CH, so that the upper surface of anode metal layer 150 and silicon epitaxial wafer 110 forms Schottky contacts.Wherein, Xiao
Special base contact hole CH runs through dielectric layer 140, and in other words, dielectric layer 140 is for example set to the two sides of schottky junctions contact hole CH.Sun
The edge of the opposite sides (left and right side as shown in figure 1) of pole metal layer 150 is for example respectively formed with third notch 151 and the 4th
Notch 153, view field QKZ3 and fourth notch 153 of the third notch 151 on silicon epitaxial wafer 110 are on silicon epitaxial wafer 110
View field QKZ4 be for example located at the region in the region QKZ1 where the first notch 117 and where the second notch 119
In QKZ2.In this way, the region for being located at schottky junctions contact hole CH opposite sides forms a terminal structure.
Cathode metal layer 160 is for example set to the lower surface of silicon epitaxial wafer 110.
Wherein, projection of the schottky junctions contact hole CH on silicon epitaxial wafer 110 for example covers all grooves 115.Specifically,
As shown in Figure 1, all grooves 115 are for example positioned at schottky junctions contact hole CH in the view field CHZ on silicon epitaxial wafer 110.
Further, silicon epitaxial wafer 110 is for example including silicon substrate 111 and the silicon epitaxy layer being set on silicon substrate 111
113.Silicon substrate 111 is, for example, N-type silicon substrate, and silicon epitaxy layer 113 is, for example, N-type silicon epitaxy layer.
All groove 115, the first notch 117 and the second notches 119 are for example respectively formed in silicon epitaxy layer 113.Each
Groove 115 is for example with the curved bottom to lower recess.
The minimum point of the bottom of each groove 115, the first notch 117 bottom minimum point and the second notch 119 bottom
The distance H of the upper surface US of the upper surface namely silicon epitaxial wafer 110 of the perigee distance silicon epitaxy layer 113 in portion is, for example, 1~2.5
Micron.Certainly, the embodiment of the present invention and as limit, H can also be other suitable numerical value.
When the number of groove 115 is multiple, the spacing L between two grooves 115 of arbitrary neighborhood is for example equal.Arbitrarily
Spacing L between two adjacent grooves 115 is, for example, 1~2.75 micron.Certainly, the embodiment of the present invention and as limit, L is also
It can be other suitable numerical value.
The material of oxide layer 120 is, for example, silica, and the material of dielectric layer 140 is, for example, the positive silicic acid of plasma enhancing
Ethyl ester (PETEOS).Certainly, the embodiment of the present invention is not limited thereto, the material of oxide layer 120 and the material of dielectric layer 140
Such as it can also be other suitable materials.
The material of anode metal layer 150 is, for example, the suitable conductive metallic materials such as titanium (Ti), the material of cathode metal layer 160
Matter is, for example, the suitable conductive metallic materials such as titanium (Ti), nickel (Ni) or silver (Ag).
In addition, the embodiment of the present invention also provides the production method of above-mentioned Schottky diode 100.Such as Fig. 2A to 2I and figure
Shown in 1, the partial structurtes for obtained device active region domain in each step of the production method of Schottky diode 100 are cutd open
Face schematic diagram.
Specifically, the production method of Schottky diode 100 specifically includes that
Step 1: as shown in Figure 2 A, cleaning silicon epitaxial wafer.
Step 2: as shown in Figure 2 B, growing to obtain layer of oxide layer OL in the upper surface US of silicon epitaxial wafer 110.Specifically,
The material of oxide layer OL is, for example, silica.Silicon epitaxial wafer 110 is for example including silicon substrate 111 and is set on silicon substrate 111
Silicon epitaxy layer 113.
Step 3: as shown in Figure 2 C, etching oxide layer OL and silicon epitaxial wafer 110 are to form at least one groove 115 (as schemed
Be, for example, multiple grooves 115 shown in 2C), the first notch 117 and the second notch 119, wherein all grooves 115, the first notch
117 and second notch 119 extend through oxide layer OL and protrude into inside silicon epitaxial wafer 110.Specifically, such as first it is aoxidizing
A layer photoresist is smeared in the upper surface of layer OL, is then exposed, develops to it, and dry etching oxide layer OL formation later runs through
At least one aperture OH, notch QK1 and the notch QK2 of oxide layer OL, then in all aperture OL, notch QK1 and the bottom notch QK2
Continue the silicon epitaxy layer 113 of segment thickness in downward wet etching silicon epitaxial wafer 110 to form at least one groove 115, in portion
One notch 117 and the second notch 119, each groove 115 have the curved bottom to lower recess.Wherein, all grooves 115 are for example
It is formed in the middle part of silicon epitaxial wafer 110, what the first notch 117 and the second notch 119 were respectively formed in silicon epitaxial wafer 110 is located at institute
State the edge of middle part opposite sides.
Step 4: as shown in Figure 2 D, in the surface of all grooves 115, the surface of the first notch 117 and the second notch 119
Surface grows layer of oxide layer 120.Specifically, the material of oxide layer 120 is, for example, silica.
Step 5: as shown in Figure 2 E, polysilicon layer 130 is formed on oxide layer OL and oxide layer 120, wherein polysilicon layer
Space except the removing oxide layer 120 of the 130 each grooves 115 of filling.Specifically, such as pass through CVD (Chemical Vapor
Deposition, chemical vapor deposition) method one layer of polysilicon of deposition, to form polysilicon layer 130.
Step 6: as shown in Figure 2 F, polysilicon layer 130 and oxide layer OL are etched, to remove polysilicon layer 130 and oxide layer
The part for protruding from 110 upper surface US of silicon epitaxial wafer of OL.
Step 7: as shown in Figure 2 G, forming dielectric layer 140 in silicon epitaxial wafer 110 and the upper surface US of oxide layer 120 and make
Dielectric layer 140 extends in the first notch 117 and the second notch 119 bottom for covering the first notch 117 and the second notch 119
Portion.Specifically, PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical gas
Mutually deposit) method deposit one layer of plasma enhancing ethyl orthosilicate (PETEOS) to form dielectric layer 140.
Step 8: as illustrated in figure 2h, etching media layer 140 is to form schottky junctions contact hole CH, wherein schottky junctions contact hole
Projection of the CH through dielectric layer 140 and on silicon epitaxial wafer 110 covers each groove 115.Wherein, schottky junctions contact hole CH exists
View field CHZ on silicon epitaxial wafer 110 covers each groove 115.Specifically, one layer is smeared in the upper surface of dielectric layer 140
Then photoresist exposes, develops, etching media layer 140 is later to form schottky junctions contact hole CH.
Step 9: as shown in figure 2i, forming anode metal layer 150 on dielectric layer 140 and extend anode metal layer 150
The bottom of schottky junctions contact hole CH is covered in schottky junctions contact hole CH.Specifically, previous by the way of magnetron sputtering
The surface that step obtains middleware deposits one layer of titanium and is deposited on the bottom schottky junctions contact hole CH to form anode metal layer 150
The anode metal layer 150 and silicon epitaxial wafer 110 in portion constitute Schottky contacts.
Step 10: as shown in fig. 2j, etch anode metal layer 150 to form third notch 151 and the 4th notch 153,
In, third notch 151 and the 4th notch 153 are respectively formed in the edge of the opposite sides of anode metal layer 150, third notch
151 projection and projection of the 4th notch 153 on silicon epitaxial wafer 110 on silicon epitaxial wafer 110 is located at the first notch 117
In region in the region at place and where the second notch 119.Third notch 151 and the 4th notch 153 are for example respectively formed in
The edge positioned at schottky junctions contact hole CH opposite sides of anode metal layer 150.In this way, being located at schottky junctions contact hole CH with respect to two
The region of side forms a terminal structure.
Step 11: as shown in Figure 1, cathode metal layer 160 is formed in the lower surface of silicon epitaxial wafer 110, so that Xiao Te be made
Based diode 100.Specifically, part thickness is removed from the bottom of silicon epitaxial wafer 110 using CMP (chemically mechanical polishing) method first
Then the silicon substrate 111 of degree deposits one layer of titanium, nickel metal or silver metal in silicon epitaxial wafer 110 in such a way that back dries
To form cathode metal layer 160 on the DS of lower surface.
By the above process, the production of achievable Schottky diode 100.It is so without being limited thereto, in other embodiments, also
It changes or increases other steps, to complete Schottky diode 100.
In conclusion the embodiment of the present invention is optimized by the structure to Schottky diode, one kind is obtained in Xiao Te
The Schottky two of a terminal is formed with groove 115, in the opposite sides of schottky junctions contact hole CH in the region base contact hole CH
Pole pipe 100 can optimize the pressure resistance of Schottky diode.
In several embodiments provided herein, it should be understood that disclosed system, device and/or method, it can
To realize by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit/
The division of module, only a kind of logical function partition, there may be another division manner in actual implementation, such as multichannel unit
Or module can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, institute
Display or the mutual coupling, direct-coupling or communication connection discussed can be through some interfaces, device or unit
Indirect coupling or communication connection can be electrical property, mechanical or other forms.
The units/modules as illustrated by the separation member may or may not be physically separated, as
The component that units/modules are shown may or may not be physical unit, it can and it is in one place, or can also be with
It is distributed on multi-channel network unit.Some or all of units/modules therein can be selected to realize according to the actual needs
The purpose of this embodiment scheme.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: it still may be used
To modify the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；
And these are modified or replaceed, technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (10)
1. a kind of Schottky diode characterized by comprising
Silicon epitaxial wafer, at least one groove is formed in the middle part of the silicon epitaxial wafer, and the silicon epitaxial wafer is located at the middle part
The edge of opposite sides is respectively formed with the first notch and the second notch；
Oxide layer covers the surface of at least one groove and the surface of first notch and second notch；
Polysilicon layer fills the space in addition to the oxide layer of at least one groove；
Dielectric layer is set to the upper surface of the silicon epitaxial wafer and the oxide layer；
Anode metal layer is set on the dielectric layer and extends in schottky junctions contact hole to cover the schottky junctions contact hole
Bottom, wherein projection covering of the schottky junctions contact hole through the dielectric layer and on the silicon epitaxial wafer is described extremely
A few groove, the edge of the opposite sides of the anode metal layer are respectively formed with third notch and the 4th notch, and described the
Projection and fourth notch projection on the silicon epitaxial wafer of three notches on the silicon epitaxial wafer are located at described
In region in region where first notch and where second notch；And
Cathode metal layer is set to the lower surface of the silicon epitaxial wafer.
2. Schottky diode as described in claim 1, which is characterized in that the silicon epitaxial wafer includes silicon substrate and is set to
Silicon epitaxy layer on the silicon substrate.
3. Schottky diode as claimed in claim 2, which is characterized in that at least one described groove, first notch
The silicon epitaxy layer is formed in second notch.
4. Schottky diode as claimed in claim 3, which is characterized in that the bottom minimum point of at least one groove,
The upper surface of silicon epitaxy layer described in the bottom perigee distance of the bottom minimum point of first notch and second notch
Distance is 1~2.5 micron.
5. Schottky diode as described in claim 1, which is characterized in that the groove included by least one described groove
Number be it is multiple.
6. Schottky diode as claimed in claim 5, which is characterized in that two institutes of arbitrary neighborhood in the multiple groove
The spacing stated between groove is equal.
7. Schottky diode as claimed in claim 6, which is characterized in that two institutes of arbitrary neighborhood in the multiple groove
Stating the spacing between groove is 1~2.75 micron.
8. Schottky diode as described in claim 1, which is characterized in that the material of the oxide layer is silica, institute
The material for stating dielectric layer is plasma enhancing ethyl orthosilicate.
9. Schottky diode as described in claim 1, which is characterized in that the material of the anode metal layer is titanium, described
The material of cathode metal layer is titanium, nickel or silver.
10. a kind of production method of Schottky diode, which is characterized in that comprising steps of
Clean silicon epitaxial wafer；
Growth obtains the first oxide layer on the silicon epitaxial wafer；
First oxide layer and the silicon epitaxial wafer are etched to form at least one groove, the first notch and the second notch,
In, at least one described groove, first notch and second notch are through first oxide layer and protrude into the silicon
Inside epitaxial wafer, at least one described groove is formed in the middle part of the silicon epitaxial wafer, and first notch and described second lack
Mouth is respectively formed in the edge positioned at the middle part opposite sides of the silicon epitaxial wafer；
It grows to obtain on the surface on the surface of at least one groove, the surface of first notch and second notch
Dioxide layer；
Polysilicon layer is formed in first oxide layer and second oxide layer, wherein described in the polysilicon layer filling
The space in addition to second oxide layer of at least one groove；
The polysilicon layer and first oxide layer are etched, to remove the protrusion of the polysilicon layer and first oxide layer
In the part of the silicon epitaxial wafer upper surface；
On the silicon epitaxial wafer and the oxide layer formed dielectric layer and make the dielectric layer extend to first notch and
The bottom of first notch and second notch is covered in second notch；
The dielectric layer is etched to form schottky junctions contact hole, wherein the schottky junctions contact hole through the dielectric layer and
Projection on the silicon epitaxial wafer covers at least one described groove；
On the dielectric layer formed anode metal layer and make the anode metal layer extend in the schottky junctions contact hole with
Cover the bottom of the schottky junctions contact hole；
The anode metal layer is etched to form third notch and the 4th notch, wherein the third notch and the described 4th lacks
Mouth is respectively formed in the edge of the opposite sides of the anode metal layer, projection of the third notch on the silicon epitaxial wafer
It is located at projection of the 4th notch on the silicon epitaxial wafer in the region where first notch and described the
In region where two notches；And
Cathode metal layer is formed in the lower surface of the silicon epitaxial wafer, so that the Schottky diode be made.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113433579A (en) * | 2021-05-18 | 2021-09-24 | 中国工程物理研究院激光聚变研究中心 | Large-sensitive-surface X-ray spectrum flat response diode detector |
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2018
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113433579A (en) * | 2021-05-18 | 2021-09-24 | 中国工程物理研究院激光聚变研究中心 | Large-sensitive-surface X-ray spectrum flat response diode detector |
| CN113433579B (en) * | 2021-05-18 | 2023-01-20 | 中国工程物理研究院激光聚变研究中心 | Large-sensitive-surface X-ray spectrum flat response diode detector |
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Application publication date: 20181221 |