CN109062684A - A kind of real-time dynamic self-adapting dynamic load balancing method of release of the hardware of multi-core processor - Google Patents
A kind of real-time dynamic self-adapting dynamic load balancing method of release of the hardware of multi-core processor Download PDFInfo
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Abstract
The invention discloses a kind of real-time dynamic self-adapting dynamic load balancing method of release of the hardware of multi-core processor.It is divided into five submodules based on multi-core processor self-adapting high-speed data distribution module, wherein data segmentation module is according to the length information and operating mode of the frame data read out from chained list FIFO.The operating mode information for the correspondence frame for adaptively number sending module being selected to be solved according to control table.SRIO group packet module completes the process of data composition SRIO data packet, and sends data according to busy-idle map information.Configuration packet and doorbell information receiving module are completed to configure the parsing of packet and send configuration packet to finish receiving and verify correct information.Busy-idle map management module creates initial busy-idle map according to the processing number of clusters of reading.The present invention can realize the distribution of data in musec order, 100,000 times faster than traditional approach or more.It is suitble to high-speed digital video camera system, the dynamic realtime load balance of large scale scale heterogeneous multi-core processor system.
Description
Technical field
The present invention relates to multi-core processor load balancing techniques field more particularly to a kind of hardware of multi-core processor are real-time
Dynamic self-adapting dynamic load balancing method of release.
Background technique
In modern digital signal processing system, CPU, FPGA and DSP are always the core devices in Digital Signal Processing,
The system for handling for the multicore isomery being made of them is very universal, the frequency of interaction between chip and chip chamber, plate and plate
It is continuously improved with interactive quantity, the high-speed data communication under heterogeneous platform and load balance will have a direct impact on the performance of system at this time.
The fast development of digital technology and the continuous improvement of processor design complexities, especially at radar signal
There is new requirement in the fields such as reason, video image acquisition and multimedia application to the transmission of high speed real-time data.Meanwhile with
The utilization of superelevation sample rate, broadband ADC/DAC in data collection system, sample rate raising sampling resolution increase,
So that the data volume of signal processing system increases again at geometry, in addition the characteristic of digital information processing system high real-time itself,
This requires higher rate, the real-time balancing dynamic load of higher performance and data distribution systems to meet wanting for data transmission
It asks.
Summary of the invention
In view of the above drawbacks of the prior art, technical problem to be solved by the invention is to provide a kind of multi-core processors
The real-time dynamic self-adapting dynamic load balancing method of release of hardware, the real-time dynamic self-adapting balancing dynamic load module of the hardware can be
The distribution of realization data in musec order, 100,000 times faster than traditional approach or more.It is suitble to high-speed digital video camera system, it is big to advise
The load balance of mould heterogeneous multi-nucleus processor system.
To achieve the above object, the present invention provides a kind of real-time dynamic self-adapting dynamic loads of the hardware of multi-core processor
Balance method, the hardware self-adapting high speed data distribution module based on multi-core processor include data segmentation module, adaptive choosing
Number sending module, SRIO group packet module, configuration packet and doorbell information receiving module and busy-idle map management module, in which:
The data segmentation module, will according to the length information and operating mode of the frame data read out from chained list FIFO
The data with same frame that 4 DDR are read are divided into control table data, 16 circuit-switched datas and monitoring information data；
The operating mode information of the correspondence frame for adaptively number sending module being selected to be solved according to control table, in different operating
Different data is selected to be sent to 4 road HSSI High-Speed Serial Interfaces under mode；
The SRIO group packet module completes the process of data composition SRIO data packet, and sends number according to busy-idle map information
According to first, in accordance with frame head, data, the sequence of doorbell is by data to be sent deposit FIFO, then presses SRIO transport protocol and draw data
It is divided into parcel, is inserted into frame head and doorbell is sent；
The function of the configuration packet and doorbell information receiving module is to complete the parsing of configuration packet and send to Local Bus
Configuration packet finishes receiving and verifies correct information, and the configuration packet that multi-core processor issues is unpacked in the dual port RAM outside deposit piece,
So that subsequent module checks the ID number of idle link, and verify the configuration packet received, after verify successfully output mode select with
And doorbell information；
The busy-idle map management module creates initial busy-idle map according to the processing number of clusters DSP_CLUSTER_NUM of reading, adopts
Whether be spare time, issue if being polled to not busy cluster if successively being inquired with the mode of poll from the 1st cluster to DSP_CLUSTER_NUM cluster
Signal, notice DDR module read a frame data；And corresponding 4 ID numbers sent of the cluster are read from busy-idle map, it is sent to SRIO
Group packet module, when receiving the clear doorbell signal that does that multi-core processor sends over, then corresponding cluster number is set to the spare time.
Further, the data that the data segmentation module completes four DDR are split, each of data segmentation module
The data that data_split submodule completes a piece of DDR are split.
It is further, described that number sending module is adaptively selected to complete frame length selection output and the selection output of SRIO data,
Specifically:
1) frame length selects output: carrying out cross clock domain conversion to the length that DDR is sent first, secondly basis receives
Merging patterns select output data length, and four-in-one then exports four road fiber data total lengths, and four close two output two-way fiber counts
According to overall length, four hairs four export data length all the way；
2) SRIO data selection output: it is different with the length of data according to control table, the DDR data sent are stored in respectively
In control table FIFO and data FIFO, when the FIFO that next stage is sent to SRIO group packet module is non-full, first control table is read, then
It is sequentially read in data portion by optical fiber, is chosen whether the road fiber data being stored in SRIO according to the merging patterns received
In FIFO, the write enable signal of SRIO FIFO and spacing wave are exported, read to enable so that next stage module generates SRIO FIFO
Signal, so that the data in SRIO FIFO be made to be sent to next stage module.
Further, the configuration packet and doorbell information receiving module go out operating mode selection according to configuration Packet analyzing and believe
Breath, optical fiber numbers of beams, processing number of clusters and module parameter.
Further, the busy-idle map management module specifically includes:
1) it reads allocation list module: first reading out the processing number of clusters DSP_CLUSTER_NUM in allocation list, read according to number of clusters
DSP_CLUSTER_NUM ID0, and all ID0 are deposited in register R_id_00~R_id_280, finally read SRIO mesh
First address；
2) busy control module: the module controls data transmission in such a way that busy adds poll, and busy operation includes setting
It busy (BUSY) and sets the spare time (IDLE), with the busy information of 0~28 bit flag, 1~29 cluster of 29 bit register cluster_state,
1 indicates BUSY, and 0 indicates IDLE.
Further, the busy control module busy operation specifically:
Set busy operation are as follows: when starting to send a frame data to a cluster, which is corresponded to the position 1 of cluster_state；
Clear busy operation are as follows: receive the clear doorbell that does that the every cluster ID0 of multi-core processor is sent, and by the ID and R_id_00 of doorbell
~R_id_280 compares, and than going out corresponding cluster number, which is set 0.
The beneficial effects of the present invention are:
The real-time dynamic self-adapting balancing dynamic load module of hardware of the invention can realize point of data in musec order
Match, 100,000 times faster than traditional approach or more.It is suitble to high-speed digital video camera system, large scale scale heterogeneous multi-core processor system
Dynamic realtime load balance.
It is described further below with reference to technical effect of the attached drawing to design of the invention, specific structure and generation, with
It is fully understood from the purpose of the present invention, feature and effect.
Detailed description of the invention
Fig. 1 is adaptive distribution module pinouts of the invention.
Fig. 2 is adaptive distribution module block diagram of the invention.
Fig. 3 is data segmentation module block diagram of the present invention.
Fig. 4 is data selection sending module pinouts of the present invention.
Fig. 5 is data selection sending module block diagram of the present invention.
Fig. 6 is data selection sending module block diagram of the present invention.
Fig. 7 is present invention group packet module status machine schematic diagram.
Fig. 8 is that the present invention sends state transition graph.
Fig. 9 is present invention configuration packet and doorbell information receiving module pinouts.
Figure 10 is present system configuration process.
Figure 11 is busy-idle map management module pinouts of the present invention.
Figure 12 is busy module of meter control block diagram of the present invention.
Figure 13 is busy poll schematic diagram of the present invention.
Specific embodiment
The real-time dynamic self-adapting dynamic load balancing method of release of the hardware of multi-core processor of the invention is handled based on multicore
The hardware self-adapting high speed data distribution module of device includes:
Adaptive distribution module is as shown in Figures 1 and 2: being broadly divided into five submodules, respectively data segmentation module, number
According to selection sending module, SRIO group packet module, configuration packet and doorbell information receiving module and busy-idle map management module.This module
Using the reconstruct of resource to achieve the purpose that each data path load balancing.
Data segmentation module is as shown in Figure 3: this module is believed according to the length of the frame data read out from chained list FIFO
4 DDR data with same frame read are divided into control table data, 16 circuit-switched datas and monitoring information data by breath and operating mode.Number
It is to complete the data fractionation of four DDR according to segmentation functions of modules, the data that each data_split submodule completes a piece of DDR are torn open
Point.Firstly, the DDR data inputted are divided into 3 sections, pass through I_isTable, I_ respectively according to data length information
IsData, I_isInfo this 3 signal identification control tables, data, detection informations.The data in each section enter different FIFO
Carry out data bit width conversion and caching.Wherein, control table and monitoring information data can be directly entered the indexing that 256bit turns 64bit
Wide FIFO.Since operating mode is different before, the difference of merging patterns causes to may not be with optical fiber all the way in 256bit data
Data, therefore data portion then needs further to be split according to the merging mode of current frame data.
Data select sending module as shown in Figures 4 and 5: the operating mode for the correspondence frame that this module is solved according to control table
Information selects different data to be sent to 4 road SRIO under different working modes.The module major function are as follows:
1) frame length selects output: carrying out cross clock domain conversion to the length that DDR is sent first, secondly basis receives
Merging patterns select output data length.Four-in-one then exports four road fiber data total lengths, and four close two output two-way fiber counts
According to overall length, four hairs four export data length all the way.
2) SRIO data selection output: it is different with the length of data according to control table, the DDR data sent are stored in respectively
In control table FIFO and data FIFO.When the FIFO that next stage is sent to SRIO group packet module is non-full, first control table is read, then
It is sequentially read in data portion by optical fiber, is chosen whether the road fiber data being stored in SRIO according to the merging patterns received
In FIFO.The write enable signal of SRIO FIFO and spacing wave are exported, read to enable so that next stage module generates SRIO FIFO
Signal, so that the data in SRIO FIFO be made to be sent to next stage module.
SRIO group packet module is as shown in Figure 6: the module completes the process of data composition SRIO data packet, and according to busy-idle map
Information sends data.Data to be sent are stored in FIFO first, in accordance with frame head, data, the sequence of doorbell.Again by SRIO transmission association
Data are divided into parcel by view, are inserted into frame head and doorbell is sent.
1) packet module is organized
Group packet module according to frame head, data, with frame monitoring information, doorbell sequence deposit transmit_fifo, when receiving this
When frame length, purpose ID, frame head is stored in transmit_fifo；Frame head is read, state transition to data mode (DATA) will
Transmit_fifo is written in data；When every write-in 256Byte data, frame head state (HEADER) is being jumped to, then to give one small
The frame head of packet；When the data volume of write-in reaches the frame data partial-length received, destination address is jumped in configuration packet and is solved
The address with frame monitoring information out, then transmit_fifo will be sent to frame monitoring information；When the total length of data of transmission reaches
When to R_data_len_64b, doorbell is stored in transmit_fifo to doorbell state (DB) by state transition.In order to optimize
The part SRIO timing, data and packet header caching have used two-stage AXI_FIFO.
State conversion is as shown in Figure 7.Group packet module shares 4 tunnels, and every road sends an ID, is sent to pair by 4 road SRIO
Answer the multi-core processor of ID.
2) sending module
It sends state machine and judges transmission types for NW (NWRITE) packet, according to length by transmit_fifo high 2 first
Data are divided into the every parcel of 256Byte and sent by information.It is 256Byte by data volume completion since DDR reads data portion
Integral multiple, therefore the length that receives of the sending module is 32 multiples, state machine will not jump to S_nwlast_header and
S_nwlast_data state, guaranteeing the NW packet sent every time all is whole 256Byte.It is received when data send to count to reach
When length, NW packet is sent.It then proceedes to judge 2 expression doorbells of transmit_fifo high, state transition to S_DB, hair
Send doorbell.Doorbell is sent state and jumps back to the free time again, waits next frame data.Since 2 generation SRIO only support NW length
It is 1,2,4,8,16,32, so a last packet less than 32 will divide five steps to split into parcel transmission, that is, splits into the supported length of NW
Degree combination.
Shown in state transition graph 8.Configuration packet and doorbell information receiving module are as shown in Figure 9: the function of this module is to complete
It configures the parsing of packet and sends configuration packet to Local Bus and finish receiving and verify correct information.Multi-core processor is issued
Configuration packet unpacks in the dual port RAM outside deposit piece, so that subsequent module checks the ID number of idle link.And what verification received matches
Packet is set, output mode selection and doorbell information after verifying successfully.
Go out operating mode selection information, optical fiber numbers of beams, processing number of clusters and module parameter according to configuration Packet analyzing, with configuration
The operating mode of whole system realizes that data difference merging patterns, every road optical fiber press the permutation and combination of wave number sending method, and defeated
Frame data and gating signal under various combination situations out, each internal module of mixing system cooperate, and embody load balancing
With the design of resource multiplex.
After receiving configuration packet from multi-core processor, progress SRIO unpacking first, and unpacked data is stored in FIFO.?
Allocation list reception signal is generated after receiving frame head data, and the data whole deposit bit wide of entire configuration packet (32*64bit)
In the twoport ram of 64bit depth 40, if the verification that solves and equal with practical verification in configuration packet, then it is assumed that verify successfully, school
Sending mode word and wave number are to next module after testing successfully.If verification is unsuccessful, multi-core processor is waited to send one again
Secondary configuration packet.Regardless of check results, primary verification situation signal can be all generated, different verifications is represented with different parameters
As a result.Configuration packet can generate the completion signal of a clock cycle after verifying successfully and give busy-idle map management module, indicate the mould
Block can read the information such as ID number from RAM and receive doorbell information.Concrete configuration process is as shown in Figure 10.
Busy-idle map management module is as shown in FIG. 11 and 12, this module is according to the processing number of clusters DSP_CLUSTER_NUM of reading
Initial busy-idle map is created, the mode of poll is used successively to be inquired from the 1st cluster to DSP_CLUSTER_NUM cluster whether for the spare time, if
It is polled to not busy cluster and then issues signal, notice DDR module reads a frame data；And the corresponding transmission of the cluster is read from busy-idle map
4 ID numbers are sent to SRIO group packet module.It is when receiving the clear busy doorbell signal that multi-core processor sends over, then right therewith
The cluster number answered is set to the spare time.
Function is described in detail:
1) it reads allocation list module: first reading out the processing number of clusters DSP_CLUSTER_NUM in allocation list, read according to number of clusters
DSP_CLUSTER_NUM ID0, and by all ID0 be deposited in register R_id_00~R_id_280 (less than 29 clusters then its
Remaining R_id deposits 16 ' d0).Finally read the first address of SRIO mesh.
2) busy control module: the module controls data transmission in such a way that busy adds poll.Busy operation includes setting
It busy (BUSY) and sets not busy (IDLE).With the busy information of 0~28 bit flag, 1~29 cluster of 29 bit register cluster_state,
1 indicates BUSY, and 0 indicates IDLE.
Set busy operation are as follows: when starting to send a frame data to a cluster, which is corresponded to the position 1 of cluster_state；
Such as shown in Figure 13, this sends the 4th cluster, by the 4th position 1 of cluster_state.
Clear busy operation are as follows: receive the clear doorbell that does that the every cluster ID0 of multi-core processor is sent, and by the ID and R_id_00 of doorbell
~R_id_280 compares, and than going out corresponding cluster number, which is set 0.Such as shown in Figure 13, the doorbell ID and R_id_40 that receive
It is equal, by the 4th position 0 of cluster_state.
Polling mechanism starts after signal is completed in configuration for the first time, starts after starting to send a frame data later.With
Cnt_poll indicates just in the cluster number of poll, if the corresponding cluster_state cluster number of cnt_poll be it is busy, cnt_poll is passed
Increase 1 and continue poll, until being polled to cluster_state cluster number as the spare time, terminates this poll.Such as shown in Figure 13, current shape
State such as schemes cluster_state1, i.e. cluster 2,4,28 is the spare time, other clusters are busy, and this this 4th cluster of transmission；Start to send the 4th cluster
Afterwards, the corresponding cluster_state of the 4th cluster is set busy, state is transformed into cluster_state2；Continue poll, cnt_poll
Add the 1, the 5th cluster be it is busy, non-poll success, cnt_poll adds 1, and so on, until being polled to the 28th cluster as the spare time, poll success,
Send the 28th cluster；Similarly state is transformed into cluster_state3, and cnt_poll is currently that 28, cnt_poll adds 1 time 0, continues
Poll sends the 2nd cluster until being polled to the 2nd cluster as the spare time.
After the completion of poll, corresponding 4 ID of the cluster number being this time polled to are read from allocation list.In end of polling(EOP) and upper one
When frame group end-of-packet, the ID of 4 SRIO mesh of next frame start signal frame_group_start, allocation list RAM reading is issued
And the first address of SRIO mesh.
The preferred embodiment of the present invention has been described in detail above.It should be appreciated that those skilled in the art without
It needs creative work according to the present invention can conceive and makes many modifications and variations.Therefore, all technologies in the art
Personnel are available by logical analysis, reasoning, or a limited experiment on the basis of existing technology under this invention's idea
Technical solution, all should be within the scope of protection determined by the claims.
Claims (6)
1. a kind of real-time dynamic self-adapting dynamic load balancing method of release of the hardware of multi-core processor, it is characterised in that: be based on multicore
The hardware self-adapting high speed data distribution module of processor includes data segmentation module, adaptively selects number sending module, SRIO group
Packet module, configuration packet and doorbell information receiving module and busy-idle map management module, in which:
The data segmentation module is according to the length information and operating mode of the frame data read out from chained list FIFO, by multi-disc
The data with same frame that DDR is read are divided into control table data, 16 circuit-switched datas and monitoring information data；
The operating mode information of the correspondence frame for adaptively number sending module being selected to be solved according to control table, in different working modes
Lower selection different data is sent to multipath high-speed serial line interface；
The SRIO group packet module completes the process of data composition SRIO data packet, and sends data according to busy-idle map information, first
Data to be sent are first stored in FIFO according to frame head, data, the sequence of doorbell, then by SRIO transport protocol are divided into data small
Packet, is inserted into frame head and doorbell is sent；
The function of the configuration packet and doorbell information receiving module is to complete the parsing of configuration packet and send to LocalBus to configure
Packet finishes receiving and verifies correct information, and the configuration packet that multi-core processor issues is unpacked in the dual port RAM outside deposit piece, for
Subsequent module checks the ID number of idle link, and verifies the configuration packet received, output mode selection and door after verifying successfully
Bell information；
The busy-idle map management module creates initial busy-idle map according to the processing number of clusters DSP_CLUSTER_NUM of reading, using wheel
Whether it is the spare time that the mode of inquiry is successively inquired from the 1st cluster to DSP_CLUSTER_NUM cluster, issues letter if being polled to not busy cluster
Number, notice DDR module reads a frame data；And the corresponding multiple corresponding ID numbers sent of the cluster are read from busy-idle map, it sends
SRIO group packet module is given, when receiving the clear busy doorbell signal that multi-core processor sends over, then corresponding cluster number is set to
It is not busy.
2. a kind of real-time dynamic self-adapting dynamic load balancing method of release of the hardware of multi-core processor as described in claim 1,
Be characterized in that: the data that the data segmentation module completes four DDR are split, each data_split of data segmentation module
The data that module completes a piece of DDR are split.
3. a kind of real-time dynamic self-adapting dynamic load balancing method of release of the hardware of multi-core processor as described in claim 1,
It is characterized in that: it is described that number sending module is adaptively selected to complete frame length selection output and the selection output of SRIO data, specifically:
1) frame length selection output: cross clock domain conversion is carried out to the length that DDR is sent first, secondly according to the merging received
Model selection output data length, four-in-one then export four road fiber data total lengths, and four conjunctions, two output two-way fiber datas are total
Long, four hairs four export data length all the way；
2) SRIO data selection output: it is different with the length of data according to control table, the DDR data sent are stored in control respectively
In table FIFO and data FIFO, when the FIFO that next stage is sent to SRIO group packet module is non-full, first control table is read, then in number
It is sequentially read according to part by optical fiber, is chosen whether the road fiber data being stored in SRIO FIFO according to the merging patterns received
In, the write enable signal of SRIO FIFO and spacing wave are exported, read enable signal so that next stage module generates SRIO FIFO,
To make the data in SRIO FIFO be sent to next stage module.
4. a kind of real-time dynamic self-adapting dynamic load balancing method of release of the hardware of multi-core processor as described in claim 1,
Be characterized in that: the configuration packet and doorbell information receiving module go out operating mode according to configuration Packet analyzing and select information, optical fiber wave
Beam number, processing number of clusters and module parameter.
5. a kind of real-time dynamic self-adapting dynamic load balancing method of release of the hardware of multi-core processor as described in claim 1,
Be characterized in that: the busy-idle map management module specifically includes:
1) it reads allocation list module: first reading out the processing number of clusters DSP_CLUSTER_NUM in allocation list, DSP_ is read according to number of clusters
CLUSTER_NUM ID0, and all ID0 are deposited in register R_id_00~R_id_280, finally read the head of SRIO mesh
Address；
2) busy control module: the module controls data transmission in such a way that busy adds poll, and busy operation includes setting to hurry i.e.
BUSY and spare time i.e. IDLE is set, with the busy information of 0~28 bit flag, 1~29 cluster of 29 bit register cluster_state, 1 table
Show BUSY, 0 indicates IDLE.
6. a kind of real-time dynamic self-adapting dynamic load balancing method of release of the hardware of multi-core processor as claimed in claim 5,
It is characterized in that, the busy control module busy operation specifically:
Set busy operation are as follows: when starting to send a frame data to a cluster, which is corresponded to the position 1 of cluster_state；
Clear busy operation are as follows: receive the clear doorbell that does that the every cluster ID0 of multi-core processor is sent, and by the ID of doorbell and R_id_00~R_
Id_280 compares, and than going out corresponding cluster number, which is set 0.
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| CN114268676A (en) * | 2021-11-29 | 2022-04-01 | 北京中科晶上科技股份有限公司 | SRIO-based deframer and satellite communication system |
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