CN109039335B - Device and method for realizing frame clock synchronization of audio analog-to-digital conversion chip array - Google Patents
Device and method for realizing frame clock synchronization of audio analog-to-digital conversion chip array Download PDFInfo
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- CN109039335B CN109039335B CN201810606617.6A CN201810606617A CN109039335B CN 109039335 B CN109039335 B CN 109039335B CN 201810606617 A CN201810606617 A CN 201810606617A CN 109039335 B CN109039335 B CN 109039335B
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- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
- H03M1/1285—Synchronous circular sampling, i.e. using undersampling of periodic input signals
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Abstract
The invention discloses a device and a method for realizing frame clock synchronization of an audio analog-to-digital conversion chip array, which realize the synchronization of internal LRCK signals of each audio ADC chip in the array by multiplexing an audio output signal pin and adding an LRCK synchronous frequency division counting processing unit before the chip works formally on the basis of the conventional audio analog-to-digital conversion chip, thereby finally realizing the synchronization of each sound channel of each audio ADC chip in the audio ADC chip array.
Description
Technical Field
The invention relates to an audio analog-to-digital conversion (ADC) chip array, in particular to a device and a method for realizing frame clock synchronization of the ADC chip array.
Background
With the rapid development of speech recognition technology, audio-to-digital converter (ADC) chips are increasingly widely used in this field. In some demanding speech recognition applications, it is necessary to integrate a plurality of audio ADC chips into an array (often called a microphone array) to improve the speech recognition effect.
The audio ADC chip array has various integration methods, and two types of integration methods are common. The type 1 is that the output audio serial data signal line of each audio ADC chip is integrated on a shared audio data signal line in a tri-state manner, and then each audio ADC chip occupies the shared audio data signal line in a time-sharing manner, as shown in fig. 1 a; the 2 nd type is that each audio ADC chip includes an audio data input signal line and an audio data output signal line, then the audio output signal line of the previous stage audio ADC chip is connected to the audio input signal line of the next stage audio ADC chip, and the audio output signal line of the last stage audio ADC chip is passed through one stage, and finally passed through, as shown in fig. 1 b.
The organization of the audio ADC channel data on the audio data signal line is also various, and two types of organization are common. Type 1 is to put the audio data of each ADC channel in one LRCK (left/right clock) cycle for output, which requires the receiving side of the user to include a data receiving processing circuit supporting this format; the type 2 is that only two sound channels are output in one internal LRCK period, the interface LRCK frequency is a multiple of the internal LRCK frequency, only two sound channels are output in each interface LRCK period, and a plurality of sound channel data of a plurality of audio ADC chips are circularly sent to a user receiving side by taking N external interface LRCK time lengths as periods (the N external interface LRCK time lengths are equal to one internal LRCK period length) according to a certain sequence. The audio ADC chip array of the 2 nd multichannel data organization mode has the advantages that: the user receiving side does not need a special data receiving and processing circuit, but only needs to adopt a common stereo audio receiving and processing circuit.
However, for the audio ADC chip array adopting the type 2 multichannel data organization method, in order to keep the sampling synchronization of each audio ADC chip in the array, the synchronization problem between the channels of each audio ADC chip in the array needs to be solved, and the sampling synchronization of each audio ADC chip depends on its internal LRCK, so the synchronization problem between the internal LRCK of each audio ADC chip in the array needs to be solved.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a device and a method for realizing the frame clock synchronization of an audio analog-to-digital conversion chip array, which can realize the synchronization among all sound channels of all audio ADC chips in the array.
In order to achieve the purpose, the invention provides the following technical scheme: an apparatus for implementing frame clock synchronization of audio analog-to-digital conversion chip array,
preferably, the apparatus includes a plurality of stages of audio analog-to-digital conversion chips connected to each other, and the audio analog-to-digital conversion chip includes:
a configuration interface unit for outputting an LRCK synchronization control signal sync _ sel;
the synchronous switch is connected with the configuration interface unit and is used for controlling whether an output signal of the synchronous switch is used as an internal LRCK synchronous input signal sync _ ip of the LRCK synchronous frequency division counting processing unit or not according to the LRCK synchronous control signal sync _ sel;
the LRCK synchronous frequency division counting processing unit is connected with the synchronous switch, is used for dividing the frequency of an external LRCK signal input by the audio analog-to-digital conversion chip, uses the divided signal as a chip internal LRCK signal i _ LRCK, and is used for outputting an internal LRCK synchronous output signal sync _ op for synchronous use of a next-stage chip according to a received synchronous input signal sync _ ip of the synchronous switch;
and the latter-stage audio analog-digital conversion chip is used as an internal LRCK synchronous input signal sync _ ip of the chip according to the received internal LRCK synchronous output signal sync _ op of the former-stage audio analog-digital conversion chip, and the phase of the frequency-divided internal LRCK signal i _ LRCK of the chip is adjusted according to the internal LRCK synchronous input signal sync _ ip and the counting target value of the chip, so that the phase of the adjusted internal LRCK signal i _ LRCK of the chip is the same as the phase of the internal LRCK signal i _ LRCK of other chips in the array.
Preferably, the audio data output signal lines of the audio analog-to-digital conversion chips are integrated on a shared audio data signal line in a tri-state manner.
Preferably, each of the audio analog-to-digital conversion chips includes an audio data input signal line and an audio data output signal line, and the audio data output signal line of the previous-stage audio analog-to-digital conversion chip is connected to the audio data input signal line of the next-stage audio analog-to-digital conversion chip.
Preferably, the LRCK synchronous frequency division counting processing unit divides the frequency of the external LRCK signal according to an LRCK frequency division coefficient, and the counting target value of the chip itself is the same as the LRCK frequency division coefficient.
Preferably, the audio analog-to-digital conversion chip further includes an ADC data processing unit and an output selector, wherein,
the input end of the ADC data processing unit is connected with both the configuration interface unit and the LRCK synchronous frequency division counting processing unit, and the output end of the ADC data processing unit is connected with the output selector and used for converting an analog input audio signal into a digital output signal o _ adcdat according to the internal LRCK signal i _ LRCK output by the LRCK synchronous frequency division counting processing unit;
the output selector is connected with the LRCK synchronous frequency division counting processing unit, the ADC data processing unit and the configuration interface unit and is used for selecting one of an internal LRCK synchronous output signal sync _ op output by the LRCK synchronous frequency division counting processing unit and a digital output signal o _ adcdat output by the ADC data processing unit as an output signal adcdat according to an output control signal o _ sel output by the configuration interface unit.
Preferably, the input end of the ADC data processing unit further receives a digital serial audio output signal tdmin output by a preceding chip and an analog input signal AIN of the present chip, and the output end of the output selector is connected to a succeeding chip.
Preferably, the input end of the ADC data processing unit further receives an analog input signal AIN of the present stage chip, and the output end of the output selector is connected to the input end of its own synchronous switch and the next stage chip.
Preferably, the audio analog-to-digital conversion chip further comprises a chip state machine and a clock reset unit, wherein,
the chip state machine is connected with the configuration interface unit and is used for controlling the chip to be at least gradually in a reset initial state, an LRCK synchronous processing working state and a normal working state;
the clock reset unit is used for enabling the chip to be in the reset initial state after the chip is powered on and started, and releasing the chip reset after the external master control CPU completes all configuration operations of the chip, so that the chip enters an LRCK synchronous processing working state firstly, and the external master control CPU switches the chip to a normal working state through the configuration interface after the chip completes the LRCK synchronous processing.
The invention discloses a method for realizing the frame clock synchronization of an audio analog-to-digital conversion chip array, which comprises the following steps:
s1, configuring the interface unit to output LRCK synchronous control signal;
s2, the synchronous switch controls whether the output signal of the synchronous switch is used as the internal LRCK synchronous input signal sync _ ip of the LRCK synchronous frequency division counting processing unit or not according to the LRCK synchronous control signal sync _ sel;
s3, the LRCK synchronous frequency division counting processing unit divides the frequency of the external LRCK signal input by the audio frequency analog-to-digital conversion chip, uses the divided frequency signal as the chip internal LRCK signal i _ LRCK, and is used for outputting an internal LRCK synchronous output signal sync _ op for the synchronous use of the next-stage chip according to the received synchronous input signal sync _ ip of the synchronous switch;
s4, the next stage audio analog-to-digital conversion chip takes the internal LRCK synchronous output signal sync _ op of the previous stage audio analog-to-digital conversion chip as the chip internal LRCK synchronous input signal sync _ ip, and adjusts the phase of the chip internal LRCK signal i _ LRCK after frequency division according to the internal LRCK synchronous input signal sync _ ip and the counting target value of the chip, so that the phase of the chip internal LRCK signal i _ LRCK after adjustment is the same as the phase of the chip internal LRCK signal i _ LRCK of other chips in the array.
Preferably, the output signal syn _ ip of the synchronous switch is changed accordingly according to the level of the synchronous control signal sync _ sel.
Preferably, the output selector selects one of the internal LRCK synchronous output signal sync _ op output by the LRCK synchronous frequency division counting processing unit and the digital output signal o _ adcdat output by the ADC data processing unit as its output signal adcdat according to the output control signal o _ sel output by the configuration interface unit
Preferably, when the synchronous input signal sync _ ip received by the LRCK synchronous frequency division counting processing unit is a high level pulse, the next input LRCK clock cycle counter is forced to the initial value of the counting cycle.
The invention has the beneficial effects that: on the basis of the existing audio analog-to-digital conversion (ADC) chip, before the chip works formally, the synchronization among the internal LRCK signals i _ LRCK of each audio ADC chip in the array is realized by multiplexing audio output signal pins and increasing an LRCK synchronous frequency division counting processing unit, and then the synchronization among the sound channels of each audio ADC chip in the array is finally realized when the audio ADC chip array adopts the type 2 output data organization mode.
Drawings
Fig. 1 is an application scenario of an existing audio ADC chip array, where fig. 1a is a schematic diagram of a connection mode structure of a multi-chip time division multiplexing shared array chip, and fig. 1b is a schematic diagram of a connection mode structure of a serial relay array chip;
FIG. 2 is a schematic diagram of the LRCK frequency division synchronization principle of the audio ADC chip of the present invention, wherein FIG. 2a is a schematic diagram of the LRCK frequency division synchronization function of the audio ADC chip under the connection mode of the array chip shown in FIG. 1 a; FIG. 2b is a schematic diagram illustrating LRCK frequency division synchronization function of the audio ADC chip under the connection mode of the array chip shown in FIG. 1 b;
fig. 3 is a schematic diagram of the synchronization principle of the LRCK synchronous frequency division counting processing unit of the present invention, wherein fig. 3a is a schematic diagram of the operation principle of the LRCK synchronous frequency division counting processing unit of the first stage audio ADC chip in the array with the frequency division coefficient set to 4, and fig. 3b is a schematic diagram of the operation principle of the LRCK synchronous frequency division counting processing unit of the audio ADC chips except the first stage in the array with the frequency division coefficient set to 4;
FIG. 4 is a schematic diagram illustrating the LRCK frequency division synchronization principle of the audio ADC chip according to an alternative embodiment of the present invention, wherein FIG. 4a is a schematic diagram illustrating the LRCK frequency division synchronization function of the audio ADC chip under the connection mode of the array chip shown in FIG. 1 a; FIG. 4b is a schematic diagram illustrating LRCK frequency division synchronization function of the audio ADC chip under the connection mode of the array chip shown in FIG. 1 b;
FIG. 5 is a schematic diagram of an audio ADC chip with an array synchronization function according to the present invention;
FIG. 6 is a schematic diagram of a chip state machine according to the present invention.
Detailed Description
The technical solution of the embodiment of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention.
The device for implementing frame clock synchronization of an audio analog-to-digital conversion chip array disclosed by the invention comprises a plurality of connected audio analog-to-digital conversion chips, as introduced in the background art, the connection modes of the plurality of audio analog-to-digital conversion chips are generally two, and are respectively shown in fig. 1a and 1b, which are both suitable for the invention, and specific integrated structures are not repeated herein, and reference can be made to the above description.
In the connection mode of the array chip shown in fig. 1a, a schematic diagram of the LRCK frequency division synchronization structure of the audio ADC chip is shown in fig. 2a, and in the connection mode of the array chip shown in fig. 1b, a schematic diagram of the LRCK frequency division synchronization structure of the audio ADC chip is shown in fig. 2b, and the structure shown in fig. 2b is specifically taken as an example for description.
As shown in fig. 2b, an audio adc chip with an array synchronization function according to an embodiment of the present invention includes: an interface unit, a synchronous switch and an LRCK synchronous frequency division counting processing unit are configured.
The configuration interface unit is configured to receive configuration information required by the ADC chip to operate and output the configuration information, where the configuration information includes an LRCK synchronous control signal sync _ sel, and may also include other configuration information, such as an output control signal o _ sel, a chip state control signal, a clock control signal, a reset control signal, and an operation control signal required by the ADC data processing unit.
The input end of the synchronous switch is connected with the configuration interface unit and receives the digital serial audio output signal tdmin at the same time, the output end of the synchronous switch is connected with the LRCK synchronous frequency division counting processing unit, and the synchronous switch is used for controlling whether the output of the synchronous switch unit is used as a synchronous input signal of the LRCK synchronous frequency division counting processing unit or not through a synchronous control signal sync _ sel output by the configuration interface unit. Specifically, when the synchronous switch is turned on, the output signal sync _ ip of the synchronous switch is used as a synchronous input signal of the LRCK synchronous frequency division counting processing unit; when the switch is closed, the output signal sync _ ip of the synchronous switch unit is ineffective for the LRCK synchronous frequency division counting processing unit. In this embodiment, the output signal syn _ ip of the synchronous switch changes according to the synchronous control signal sync _ sel: when sync control signal sync _ sel is at low level, sync _ ip is always kept at low level, and when sync _ sel is at high level, sync _ ip keeps the same variation timing as tdmin signal.
The input end of the LRCK synchronous frequency division counting processing unit is connected with the synchronous switch, and the input end of the LRCK synchronous frequency division counting processing unit also receives an external LRCK signal (namely the LRCK signal shown in the figure 1a and the figure 1 b) and an LRCK frequency division coefficient which are input to the audio analog-digital conversion chip, and the LRCK signal is used for carrying out frequency division on the external LRCK signal according to the LRCK frequency division coefficient and outputting the frequency-divided signal to be used as an internal LRCK signal i _ LRCK of the chip; and the synchronous output circuit is used for outputting an internal LRCK synchronous output signal sync _ op for synchronous use of a next-stage chip according to a received synchronous input signal sync _ ip output by the synchronous switch, wherein the internal LRCK synchronous output signal sync _ op is equivalent to a digital serial audio output signal tdmin of the next-stage chip when being output to the next-stage chip. The LRCK division factor is generally the same as the number of chips, for example, the number of chips is 4, and the LRCK division factor is 4.
The principle of achieving synchronization between the internal LRCK signals i _ LRCK by an array in which the LRCK division factor is set to 4 is explained in detail below.
Fig. 3a shows the operation process of the LRCK synchronous frequency division counting processing unit of the first stage audio ADC chip in the array with the frequency division factor set to 4. In the figure, LRCK is an input clock (i.e., an external LRCK signal) of the LRCK frequency division count, LRCK _ cnt is a frequency division counter, and i _ LRCK is a frame frequency signal after frequency division. The first stage audio ADC chip, as the initiator of synchronization, has its LRCK synchronization control signal sync _ sel configured to a low level so that its output internal LRCK synchronization input signal sync _ ip remains at a low level at all times, and the LRCK _ cnt counter counts only according to its clock by a set LRCK division factor, and outputs an LRCK synchronization output pulse signal sync _ op of one input LRCK (i.e., external LRCK signal) clock cycle whenever the LRCK _ cnt counter counts to a value of the division factor-1 (i.e., counts to 3).
Fig. 3b shows the operation of the LRCK synchronous division count processing unit of the audio ADC chip of the stage other than the first stage in the array with the division factor set to 4. Similarly, in the figure, LRCK is an input clock of LRCK frequency division count, LRCK _ cnt is a frequency division counter, and i _ LRCK is a frequency-divided frame frequency signal. The non-first stage audio ADC chip receives the sync pulse signal sync _ op output by the previous stage audio ADC chip, and then the sync control signal sync _ sel is configured to be at a high level through the configuration interface unit, so that the LRCK sync input signal sync _ ip is consistent with the sync output signal sync _ op output by the previous stage audio ADC chip, that is, the sync input signal sync _ ip in fig. 3b is consistent with the sync output signal sync _ op output by the previous stage (e.g., the first stage) audio ADC chip.
In addition to counting according to the set frequency division factor according to the clock, when the synchronous input signal sync _ ip received by the LRCK synchronous frequency division count processing unit is a high level pulse, the next input LRCK clock cycle counter is forced to the initial value of the counting cycle, such as 0, but it may also be 1 or other initial values, such as 0 in this embodiment, as shown in fig. 3b, and each time the LRCK _ cnt counter counts the value of the frequency division factor-1, it outputs a synchronous output signal sync _ op of the input LRCK clock cycle.
When the synchronous output signal sync _ op of the previous stage audio ADC chip (i.e. the synchronous input signal sync _ ip of the current stage audio ADC chip) and the synchronous output signal sync _ op of the current stage audio ADC chip keep the same change rule, the i _ LRCK signal output by the LRCK synchronous frequency division counting processing unit of the current stage chip and the i _ LRCK signal output by the LRCK synchronous frequency division counting processing unit of the previous stage chip have the same change rule, and the chip completes the synchronization with the previous stage chip. Thus, the stage is followed by one stage, and the synchronous processing process of all the audio ADC chips in the array is completed.
Further, as shown in fig. 4a and 4b, an audio analog-to-digital conversion chip with an array synchronization function according to an embodiment of the present invention further includes: an ADC data processing unit and an output selector. Fig. 4a and 4b are schematic diagrams corresponding to the LRCK frequency division synchronization structure of the audio ADC chip in the two array chip connection modes of fig. 1a and 1b, respectively.
The ADC data processing unit is mainly used for completing the whole processing process from analog input audio signals to serial audio digital signals, and comprises audio analog front end processing, audio digital filtering, audio output format processing and the like.
Specifically, as shown in fig. 4b, the input end of the ADC data processing unit is connected to both the configuration interface unit and the LRCK synchronous frequency division counting processing unit, and receives the digital serial audio output signal tdmin signal output by the previous chip and the analog input signal AIN of the present chip, and is used for configuring parameters required by the ADC data processing unit through the configuration interface unit according to user requirements, converting the analog input signal AIN of the present chip into the digital serial audio output signal of the present chip, and then combining with the digital serial audio output signal tdmin from the previous chip to output the digital serial audio output signal o _ adcdat. Wherein, i _ LRCK output by the LRCK synchronous frequency division counting processing unit is used as an internal LRCK signal used by the ADC data processing unit.
The ADC data processing unit shown in fig. 4a is similar to the ADC data processing unit shown in fig. 4b in principle, and its input end is also connected to both the configuration interface unit and the LRCK synchronous frequency division counting processing unit, and receives the local chip analog input signal AIN, and is used to configure the parameters required by the ADC data processing unit through the configuration interface unit according to the user's requirements, convert the local chip analog input signal AIN into the local chip digital serial audio output signal, and output it as the digital serial audio output signal o _ ADC dat.
The input end of the output selector is connected to the LRCK synchronous frequency division counting processing unit, the ADC data processing unit and the configuration interface unit, and is respectively configured to receive the internal LRCK synchronous output signal sync _ op, the digital serial audio output signal o _ adcdat and the output control signal o _ sel, the output end is connected to the input end of its own synchronous switch and the subsequent chip, and outputs the digital serial audio output signal o _ adcdat, as shown in fig. 4a, or directly connected to the subsequent chip, and outputs the o _ adcdat signal, as shown in fig. 4 b. It is used for accomplishing the multiplexing function selection of audio output signal pin: when the chip is in an LRCK synchronous processing working state, the chip selects an internal LRCK synchronous output signal sync _ op output by the LRCK synchronous frequency division processing unit as the input of an audio output signal pin; when the chip is in a normal working state, the chip selects the audio output signal of the ADC data processor unit as the input of the audio output signal pin. In this embodiment, when the chip is in the LRCK synchronous processing operation state, the output adcdat signal of the output selector is changed according to the output control signal o _ sel, and when the o _ sel signal is at a low level, the adcdat signal is equal to the o _ adcdat signal in fig. 4a and 4b, and when the o _ sel signal is at a high level, the adcdat signal is equal to the sync _ op signal in fig. 4a and 4 b.
Further, as shown in fig. 5, an audio adc chip with an array synchronization function according to an embodiment of the present invention further includes: a chip state machine and a clock reset unit, wherein, as shown in fig. 6, the chip state machine is connected to the configuration interface unit, and the chip state machine includes a plurality of working states, mainly including three working states: and a reset initial state, wherein the working voltage of the chip gradually reaches the normal working voltage, and the external master control CPU completes the parameter setting of the LRCK frequency division synchronous working state of the chip. And after the LRCK frequency division synchronous working state parameter configuration operation is finished, the main control CPU performs resetting operation on the audio ADC, the working state of the chip jumps to the LRCK frequency division synchronous working state, and LRCK frequency division synchronous processing of the current chip and other chips in the array is finished under the state. And switching the chip from the LRCK frequency division synchronous working state to a normal working state by the external master control CPU until all chips in the array complete the LRCK frequency division synchronous processing.
The clock reset unit is used for enabling the chip to be in a reset initial state after the chip is powered on and started, and releasing the chip reset after the external master control CPU completes all configuration operations of the chip, so that the chip gradually enters other working states, specifically, the chip firstly enters an LRCK synchronous processing working state, and the external master control CPU switches the chip to a normal working state through the configuration interface after the chip completes LRCK synchronous processing.
In this embodiment, when the chip is in the LRCK synchronous frequency division state, both the sync _ sel signal and the o _ sel signal of the two control signals output by the configuration interface unit are at high level, and when the chip is in the normal operation state, both the sync _ sel signal and the o _ sel signal of the two control signals output by the configuration interface unit are at low level.
Based on the device for realizing the frame clock synchronization of the audio analog-to-digital conversion chip array, the invention discloses a method for realizing the frame clock synchronization of the audio analog-to-digital conversion chip array, which comprises the following steps:
s1, configuring the interface unit to output LRCK synchronous control signal;
s2, the synchronous switch controls whether the output signal of the synchronous switch is used as the internal LRCK synchronous input signal sync _ ip of the LRCK synchronous frequency division counting processing unit or not according to the LRCK synchronous control signal sync _ sel;
s3, the LRCK synchronous frequency division counting processing unit divides the frequency of the external LRCK signal input by the audio frequency analog-to-digital conversion chip, uses the divided frequency signal as the chip internal LRCK signal i _ LRCK, and is used for outputting an internal LRCK synchronous output signal sync _ op for the synchronous use of the next-stage chip according to the received synchronous input signal sync _ ip of the synchronous switch;
s4, the next stage audio analog-to-digital conversion chip takes the internal LRCK synchronous output signal sync _ op of the previous stage audio analog-to-digital conversion chip as the chip internal LRCK synchronous input signal sync _ ip, and adjusts the phase of the chip internal LRCK signal i _ LRCK after frequency division according to the internal LRCK synchronous input signal sync _ ip and the counting target value of the chip, so that the phase of the chip internal LRCK signal i _ LRCK after adjustment is the same as the phase of the chip internal LRCK signal i _ LRCK of other chips in the array.
Therefore, the scope of the present invention should not be limited to the disclosure of the embodiments, but includes various alternatives and modifications without departing from the scope of the present invention, which is defined by the claims of the present patent application.
Claims (10)
1. An apparatus for implementing frame clock synchronization of an audio analog-to-digital conversion chip array is characterized in that the apparatus comprises multiple stages of audio analog-to-digital conversion chips connected with each other, and the audio analog-to-digital conversion chips comprise:
a configuration interface unit for outputting an LRCK synchronization control signal sync _ sel;
the synchronous switch is connected with the configuration interface unit and is used for controlling whether an output signal of the synchronous switch is used as an internal LRCK synchronous input signal sync _ ip of the LRCK synchronous frequency division counting processing unit or not according to the LRCK synchronous control signal sync _ sel;
the LRCK synchronous frequency division counting processing unit is connected with the synchronous switch, is used for dividing the frequency of an external LRCK signal input by the audio analog-to-digital conversion chip, uses the divided signal as a chip internal LRCK signal i _ LRCK, and is used for outputting an internal LRCK synchronous output signal sync _ op for synchronous use of a next-stage chip according to a received synchronous input signal sync _ ip of the synchronous switch;
the rear-stage audio analog-digital conversion chip is used as an internal LRCK synchronous input signal sync _ ip of the chip according to a received LRCK synchronous output signal sync _ op of the front-stage audio analog-digital conversion chip, and the phase of a frequency-divided internal LRCK signal i _ LRCK of the chip is adjusted according to the internal LRCK synchronous input signal sync _ ip and a counting target value of the rear-stage audio analog-digital conversion chip, so that the phase of the adjusted internal LRCK signal i _ LRCK of the chip is the same as the phase of the internal LRCK signal i _ LRCK of the front-stage chip.
2. The apparatus of claim 1, wherein the LRCK synchronous frequency division count processing unit divides the frequency of the external LRCK signal according to an LRCK frequency division coefficient, and a count target value of the chip itself is the same as the LRCK frequency division coefficient.
3. The implementation device of claim 1, wherein the audio ADC chip further comprises an ADC data processing unit and an output selector, wherein,
the input end of the ADC data processing unit is connected with both the configuration interface unit and the LRCK synchronous frequency division counting processing unit, and the output end of the ADC data processing unit is connected with the output selector and used for converting an analog input audio signal into a digital output signal o _ adcdat according to the internal LRCK signal i _ LRCK output by the LRCK synchronous frequency division counting processing unit;
the output selector is connected with the LRCK synchronous frequency division counting processing unit, the ADC data processing unit and the configuration interface unit and is used for selecting one of an internal LRCK synchronous output signal sync _ op output by the LRCK synchronous frequency division counting processing unit and a digital output signal o _ adcdat output by the ADC data processing unit as an output signal adcdat according to an output control signal o _ sel output by the configuration interface unit.
4. The device according to claim 3, wherein the input terminal of the ADC data processing unit further receives a digital serial audio output signal tdmin output by a previous chip and an analog input signal AIN of a present chip, and the output terminal of the output selector is connected to a next chip.
5. The device of claim 3, wherein the input terminal of the ADC data processing unit further receives an analog input signal AIN of the chip at this stage, and the output terminal of the output selector is connected to the input terminal of its own synchronous switch and the chip at the next stage.
6. The apparatus of claim 1, wherein the audio ADC chip further comprises a chip state machine and a clock reset unit, wherein,
the chip state machine is connected with the configuration interface unit and is used for controlling the chip to be at least gradually in a reset initial state, an LRCK synchronous processing working state and a normal working state;
the clock reset unit is used for enabling the chip to be in the reset initial state after the chip is powered on and started, and releasing the chip reset after the external master control CPU completes all configuration operations of the chip, so that the chip enters an LRCK synchronous processing working state firstly, and the external master control CPU switches the chip to a normal working state through the configuration interface after the chip completes the LRCK synchronous processing.
7. An implementation method of the apparatus for implementing frame clock synchronization of an audio analog-to-digital conversion chip array according to claim 3, the method comprising:
s1, configuring the interface unit to output LRCK synchronous control signal;
s2, the synchronous switch controls whether the output signal of the synchronous switch is used as the internal LRCK synchronous input signal sync _ ip of the LRCK synchronous frequency division counting processing unit or not according to the LRCK synchronous control signal sync _ sel;
s3, the LRCK synchronous frequency division counting processing unit divides the frequency of the external LRCK signal input by the audio frequency analog-to-digital conversion chip, uses the divided frequency signal as the chip internal LRCK signal i _ LRCK, and is used for outputting an internal LRCK synchronous output signal sync _ op for the synchronous use of the next-stage chip according to the received synchronous input signal sync _ ip of the synchronous switch;
s4, the next stage audio analog-to-digital conversion chip takes the internal LRCK synchronous output signal sync _ op of the previous stage audio analog-to-digital conversion chip as the chip internal LRCK synchronous input signal sync _ ip, and adjusts the phase of the chip internal LRCK signal i _ LRCK after frequency division according to the internal LRCK synchronous input signal sync _ ip and the counting target value of the chip, so that the phase of the chip internal LRCK signal i _ LRCK after adjustment is the same as the phase of the chip internal LRCK signal i _ LRCK of other chips in the array.
8. The method as claimed in claim 7, wherein the output signal syn _ ip of the synchronous switch varies according to the level of the synchronous control signal sync _ sel.
9. The method of claim 7, wherein the output selector selects one of an internal LRCK synchronous output signal sync _ op output by the LRCK synchronous frequency division counting processing unit and a digital output signal o _ adcdat output by the ADC data processing unit as the output signal adcdat according to an output control signal o _ sel output by the configuration interface unit.
10. The method of claim 7 wherein the LRCK synchronous divide-by-count processing unit is further configured to force the next input LRCK clock cycle counter to an initial value of a count cycle when the synchronous input signal sync _ ip received by the LRCK synchronous divide-by-count processing unit is a high pulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810606617.6A CN109039335B (en) | 2018-06-13 | 2018-06-13 | Device and method for realizing frame clock synchronization of audio analog-to-digital conversion chip array |
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| CN112019992B (en) * | 2019-05-29 | 2021-07-09 | 瑞昱半导体股份有限公司 | Audio processing circuit supporting multi-channel input function |
| CN111327321B (en) * | 2020-04-16 | 2023-04-25 | 苏州顺芯半导体有限公司 | Device and method for realizing real-time synchronization of audio analog-digital conversion chip array |
| CN113645540B (en) * | 2020-04-24 | 2022-11-08 | 矽统科技股份有限公司 | Digital audio array circuit |
| TWI747250B (en) | 2020-04-24 | 2021-11-21 | 矽統科技股份有限公司 | Digital audio array circuit |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060045172A (en) * | 2004-11-09 | 2006-05-17 | 주식회사 대우일렉트로닉스 | A orthogonal fequency division multiplexing system multiple using dvb-t and dab |
| CN101448315A (en) * | 2008-12-31 | 2009-06-03 | 华为技术有限公司 | Frame clock synchronization method and frame clock synchronization apparatus |
| CN201623760U (en) * | 2009-12-25 | 2010-11-03 | 大连科迪视频技术有限公司 | 3G-SDI high-definition digital video frame synchronizer |
| CN103684375A (en) * | 2013-11-26 | 2014-03-26 | 深圳市芯海科技有限公司 | Clock frequency division switching circuit and clock chip |
| CN104541473A (en) * | 2012-06-01 | 2015-04-22 | 黑莓有限公司 | Universal synchronization engine based on probabilistic methods for guarantee of lock in multiformat audio systems |
| CN106412763A (en) * | 2016-10-11 | 2017-02-15 | 国光电器股份有限公司 | Audio processing method and apparatus |
| CN206790499U (en) * | 2017-04-07 | 2017-12-22 | 深圳市台电实业有限公司 | A kind of audio synchronization system for session discussing system Redundancy Design |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9326064B2 (en) * | 2011-10-09 | 2016-04-26 | VisiSonics Corporation | Microphone array configuration and method for operating the same |
-
2018
- 2018-06-13 CN CN201810606617.6A patent/CN109039335B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060045172A (en) * | 2004-11-09 | 2006-05-17 | 주식회사 대우일렉트로닉스 | A orthogonal fequency division multiplexing system multiple using dvb-t and dab |
| CN101448315A (en) * | 2008-12-31 | 2009-06-03 | 华为技术有限公司 | Frame clock synchronization method and frame clock synchronization apparatus |
| CN201623760U (en) * | 2009-12-25 | 2010-11-03 | 大连科迪视频技术有限公司 | 3G-SDI high-definition digital video frame synchronizer |
| CN104541473A (en) * | 2012-06-01 | 2015-04-22 | 黑莓有限公司 | Universal synchronization engine based on probabilistic methods for guarantee of lock in multiformat audio systems |
| CN103684375A (en) * | 2013-11-26 | 2014-03-26 | 深圳市芯海科技有限公司 | Clock frequency division switching circuit and clock chip |
| CN106412763A (en) * | 2016-10-11 | 2017-02-15 | 国光电器股份有限公司 | Audio processing method and apparatus |
| CN206790499U (en) * | 2017-04-07 | 2017-12-22 | 深圳市台电实业有限公司 | A kind of audio synchronization system for session discussing system Redundancy Design |
Non-Patent Citations (2)
| Title |
|---|
| A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC;Manuel J等;《IEEE Transactions on Circuits and Systems I》;20161010;全文 * |
| 基于IP的多路音频实时传输技术研究;常永亮;《中国优秀硕士学位论文全文数据库 信息科技辑》;20130715;全文 * |
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