CN109037206A - A kind of power device protection chip and preparation method thereof - Google Patents
A kind of power device protection chip and preparation method thereof Download PDFInfo
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- CN109037206A CN109037206A CN201810817024.4A CN201810817024A CN109037206A CN 109037206 A CN109037206 A CN 109037206A CN 201810817024 A CN201810817024 A CN 201810817024A CN 109037206 A CN109037206 A CN 109037206A
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- 238000002360 preparation method Methods 0.000 title abstract description 6
- 238000002347 injection Methods 0.000 claims abstract description 192
- 239000007924 injection Substances 0.000 claims abstract description 192
- 239000000758 substrate Substances 0.000 claims abstract description 76
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 73
- 229920005591 polysilicon Polymers 0.000 claims abstract description 71
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 230000026267 regulation of growth Effects 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 433
- 238000000034 method Methods 0.000 description 35
- 239000004065 semiconductor Substances 0.000 description 16
- 238000009792 diffusion process Methods 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 230000008569 process Effects 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 150000002500 ions Chemical class 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000000151 deposition Methods 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000000927 vapour-phase epitaxy Methods 0.000 description 7
- 229910052785 arsenic Inorganic materials 0.000 description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 238000005566 electron beam evaporation Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- -1 phosphonium ion Chemical class 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000003796 beauty Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides a kind of power device protection chips and preparation method thereof, comprising: the substrate of the first conduction type；First epitaxial layer of the second conduction type；First buried layer of the first conduction type and the second buried layer of the second conduction type, are formed in first epitaxial layer；Second epitaxial layer of the first conduction type；First injection region of the first conduction type and the second injection region of the second conduction type are formed in second epitaxial layer upper surface, and first injection region is connected with second injection region；Polysilicon layer is connect through second epitaxial layer and with first injection region and first buried layer respectively；Dielectric layer is formed in the upper surface of second epitaxial layer；First electrode, including through the dielectric layer and extending to and the first part of second injection region and being formed in the second part of the dielectric layer surface；Second electrode is formed in the lower surface of the substrate.Device performance, which can be improved, in the present invention reduces device cost.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of power device protection chip and preparation method thereof.
Background technique
Power device protection chip is a kind of for protecting sensitive semiconductor device, destroys it from transient voltage surge
And specially designed solid-state semiconductor device, it has, and clamp coefficient is small, small in size, response is fast, leakage current is small and high reliablity
The advantages that, thus be widely used on voltage transient and carrying out surge protection.Low Capacitance Power device protection chip is applicable in
In the protection device of high-frequency circuit, because it can reduce interference of the parasitic capacitance to circuit, declining for high-frequency circuit signal is reduced
Subtract.
The transient voltage that static discharge and some other voltage surge form occur at random, is typically found in various electronics
In device.As semiconductor devices increasingly tends to miniaturization, high density and multi-functional, electronic device becomes increasingly susceptible to voltage
The influence of surge, even results in fatal harm.Various voltage surges can induce transient current from static discharge to lightning etc.
Peak power device protects impact of the chip commonly used to protection sensitive circuit by surge.Based on different applications, power device
Part protection chip can play the role of circuit protection by changing the clamping voltag of surge discharge path and itself.
Currently used power device protects chip, needs multiple power devices protecting core if bidirectional protective to be carried out
Piece serial or parallel connection together, increases device area and manufacturing cost.
Summary of the invention
The present invention is based on the above problems, proposes a kind of power device protection chip and preparation method thereof, is improving
Power device reduces the manufacturing cost of power device protection chip while protecting chip performance.
In view of this, on the one hand the embodiment of the present invention proposes a kind of power device protection chip, power device protection
Chip includes:
The substrate of first conduction type；
First epitaxial layer of the second conduction type, is grown on the upper surface of substrate；
First buried layer of the first conduction type and the second buried layer of the second conduction type, are formed in first epitaxial layer
It is interior, and at least partly surface exposure of first buried layer and the second buried layer is in first epitaxial layer upper surface, described second
The doping concentration of buried layer is higher than the doping concentration of first epitaxial layer；
Second epitaxial layer of the first conduction type is formed in first epitaxial layer upper surface, and first buried layer
Doping concentration be higher than second epitaxial layer doping concentration；
First injection region of the first conduction type and the second injection region of the second conduction type, are formed in second extension
Layer upper surface, and first injection region is connected with second injection region, the doping concentration of first injection region is higher than
The doping concentration of second epitaxial layer；
Polysilicon layer is connect through second epitaxial layer and with first injection region and first buried layer respectively；
Dielectric layer is formed in the upper surface of second epitaxial layer；
First electrode, including through the dielectric layer and extend to second injection region first part and be formed in institute
State the second part of dielectric layer surface；
Second electrode is formed in the lower surface of the substrate and connect with the substrate.
Further, the doping concentration of first injection region is higher than the doping concentration of first buried layer.
Further, the doping concentration of second buried layer is higher than the doping concentration of second injection region.
Further, second buried layer is oppositely arranged with second injection region.
Further, first buried layer includes the first sub- buried layer and second for being respectively arranged at second buried layer two sides
Sub- buried layer, first injection region include the first sub- injection region and the second son note for being respectively arranged at second injection region two sides
Entering area, the polysilicon layer includes the first polysilicon layer connecting with the described first sub- buried layer and the first sub- injection region, with
And the second polysilicon layer being connect with the described second sub- buried layer and the second sub- injection region.
On the other hand the embodiment of the present invention provides a kind of production method of power device protection chip, this method comprises:
In the first epitaxial layer of two conduction type of upper surface of substrate growth regulation of the first conduction type；
The first buried layer of the first conduction type and the second buried layer of the second conduction type are formed in first epitaxial layer,
And at least partly surface exposure of first buried layer and the second buried layer is in first epitaxial layer upper surface, second buried layer
Doping concentration be higher than first epitaxial layer doping concentration；
The second epitaxial layer of the first conduction type, and first buried layer are formed in first epitaxial layer upper surface
Doping concentration is higher than the doping concentration of second epitaxial layer；
The first groove of first buried layer is formed through second epitaxial layer and extended to, and is formed positioned at described
First groove upside and the second groove with the first groove connection；
Second epitaxial layer upper surface formed the first conduction type the first injection region and the second conduction type the
Two injection regions, and first injection region is connected into first injection region, the doping concentration of first injection region is higher than institute
State the doping concentration of the second epitaxial layer；
The polysilicon layer that first buried layer connects is formed in the first groove and the second groove, and will be described
Polysilicon layer is connected with first injection region；
Dielectric layer is formed in the upper surface of second epitaxial layer；
First electrode is formed, the first electrode includes through the dielectric layer and extending to the of second injection region
A part and the second part for being formed in the dielectric layer surface；
The second electrode connecting with the substrate is formed in the lower surface of the substrate.
Further, the doping concentration of first injection region is higher than the doping concentration of first buried layer.
Further, the doping concentration of second buried layer is higher than the doping concentration of second injection region.
Further, second buried layer and second injection region are oppositely arranged.
Further, first buried layer includes the first sub- buried layer and second for being respectively arranged at second buried layer two sides
Sub- buried layer, first injection region include the first sub- injection region and the second son note for being respectively arranged at second injection region two sides
Entering area, the polysilicon layer includes the first polysilicon layer connecting with the described first sub- buried layer and the first sub- injection region, with
And the second polysilicon layer being connect with the described second sub- buried layer and the second sub- injection region.
The technical solution of the embodiment of the present invention passes through two conduction type of upper surface of substrate growth regulation in the first conduction type
The first epitaxial layer；Formed in first epitaxial layer the first conduction type the first buried layer and the second conduction type second
Buried layer, and at least partly surface exposure of first buried layer and the second buried layer is in first epitaxial layer upper surface, described
The doping concentration of two buried layers is higher than the doping concentration of first epitaxial layer；First is formed in first epitaxial layer upper surface to lead
Second epitaxial layer of electric type, and the doping concentration of first buried layer is higher than the doping concentration of second epitaxial layer；Shape
At through second epitaxial layer and extending to the first groove of first buried layer, and is formed and be located in the first groove
Side and second groove with the first groove connection；The first of the first conduction type is formed in second epitaxial layer upper surface
Second injection region of injection region and the second conduction type, and first injection region is connected into first injection region, described the
The doping concentration of one injection region is higher than the doping concentration of second epitaxial layer；In the first groove and the second groove
The polysilicon layer of the first buried layer connection is formed, and the polysilicon layer is connected with first injection region；Described
The upper surface of second epitaxial layer forms dielectric layer；First electrode is formed, the first electrode includes through the dielectric layer and prolonging
It extends to the first part of second injection region and is formed in the second part of the dielectric layer surface；In the following table of the substrate
Face forms the second electrode connecting with the substrate.Technical solution of the present invention reduces device making technics difficulty, subtracts significantly
Small parasitic capacitance, so that the protection feature and reliability of device are all improved.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below to needed in embodiment description
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the flow diagram of the production method for the power device protection chip that one embodiment of the present of invention provides；
Fig. 2 is the structural schematic diagram for the power device protection chip that one embodiment of the present of invention provides；
Fig. 3 to Figure 10 is the knot of the production method step for the power device protection chip that one embodiment of the present of invention provides
Structure schematic diagram；
Figure 11 is the equivalent circuit diagram for the power device protection chip structure that one embodiment of the present of invention provides；
In figure: 1, substrate；2, the first epitaxial layer；3, the first buried layer；4, the second buried layer；5, the second epitaxial layer；6, the first ditch
Slot；7, the first injection region；8, the second injection region；9, second groove；10, polysilicon layer；11, dielectric layer；12, first electrode；
121, first part；122, second part；13, second electrode；A1, first diode；B1, the second diode；C1, the three or two pole
Pipe；A2, the 4th diode；B2, the 5th diode；C2, the 6th diode.
Specific embodiment
It below will the present invention will be described in more detail refering to attached drawing.In various figures, identical element uses similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use that " A is directly on B herein to describe located immediately at another layer, another region above scenario
The expression method of face " or " A on B and therewith abut ".In this application, " A is in B " indicates that A is located in B, and
And A and B is abutted directly against, rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to entire half formed in each step of manufacturing semiconductor devices
The general designation of conductor structure, including all layers formed or region.
Many specific details of the invention, such as structure, material, the size, processing side of device are described hereinafter
Method and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
Referring next to attached drawing, a kind of production method of power device protection chip is elaborated.
Below in conjunction with Fig. 1 to Figure 10 to a kind of power device protection chip provided in an embodiment of the present invention and preparation method thereof
It is described in detail.
The embodiment of the present invention provides a kind of production method of power device protection chip, as depicted in figs. 1 and 2, the power
Device protection chip production method include:
Step S1: in the first epitaxial layer 2 of 1 upper surface growth regulation of substrate, two conduction type of the first conduction type；
Step S2: first buried layer 3 and the second conduction type of the first conduction type are formed in first epitaxial layer 2
Second buried layer 4, and at least partly surface exposure of first buried layer 3 and the second buried layer 4 is in table on first epitaxial layer 2
Face, the doping concentration of second buried layer 4 are higher than the doping concentration of first epitaxial layer 2；
Step S3: the second epitaxial layer 5 of the first conduction type is formed in 2 upper surface of the first epitaxial layer, and described
The doping concentration of first buried layer 3 is higher than the doping concentration of second epitaxial layer 5；
Step S4: form through second epitaxial layer 5 and extend to the first groove 6 and shape of first buried layer 3
Second groove 9 at 6 upside of first groove is located at and with 6 connection of first groove；
Step S5: conductive in the first injection region 7 and second that 5 upper surface of the second epitaxial layer forms the first conduction type
Second injection region 8 of type, and first injection region 7 is connected into first injection region 7, first injection region 7 is mixed
Miscellaneous concentration is higher than the doping concentration of second epitaxial layer 5；
Step S6: the polysilicon that first buried layer 3 connects is formed in the first groove 6 and the second groove 9
Layer 10, and the polysilicon layer 10 is connected with first injection region 7；
Step S7: dielectric layer 11 is formed in the upper surface of second epitaxial layer 5；
Step S8: forming first electrode 12, and the first electrode 12 includes through the dielectric layer 11 and extending to described
The first part 121 of second injection region 8 and the second part 122 for being formed in 11 surface of dielectric layer；Under the substrate 1
Surface forms the second electrode 13 connecting with the substrate 1.
Specifically, first conduction type is one of p-type doping and n-type doping, and second conduction type is P
Type doping and the another kind in n-type doping.
Special to illustrate herein for convenience of description: first conduction type can be n-type doping, so that described second is conductive
Type is p-type doping；First conduction type can also adulterate for p-type, so that second conduction type is n-type doping.
It is understood that when first conduction type is p-type doping, when second conduction type is n-type doping, the substrate
1, first buried layer 3, second epitaxial layer 5 and first injection region 7 are that p-type is adulterated, first epitaxial layer 2,
Second buried layer 4 and second injection region 8 are N-type epitaxy layer.When first conduction type be n-type doping, it is described
When second conduction type is that p-type is adulterated, the substrate 1, first buried layer 3, second epitaxial layer 5 and first injection
Area 7 is n-type doping, and first epitaxial layer 2, second buried layer 4 and second injection region 8 are p-type epitaxial layer.?
It in next embodiment, is adulterated by p-type of first conduction type, second conduction type is for n-type doping
It is described, but is defined not to this.
Specifically, P type substrate and p-type extension belong to P-type semiconductor, and N-type substrate and N-type extension belong to N-type and partly lead
Body.The P-type semiconductor is the silicon wafer for adulterating triad, such as any group of boron element or phosphide element or aluminium element or three
It closes.The N-type semiconductor is any combination of the silicon wafer for adulterating pentad, such as P elements or arsenic element or both.
Attached drawing 3 is please referred to, step S1 is executed, specifically: it is conductive in the 1 upper surface growth regulation of substrate two of the first conduction type
First epitaxial layer 2 of type.Wherein, in the first extension of 1 upper surface growth regulation of substrate, two conduction type of the first conduction type
The mode of layer 2 is not limited to a kind of fixed mode, can be epitaxially-formed, can also lead in the 1 upper surface use of substrate
The method for crossing ion implanting and/or diffusion forms first epitaxial layer 2 in 1 upper surface of substrate.It is possible to further
The 1 upper surface use of substrate is epitaxially-formed, and can also pass through ion implanting and/or diffusion P elements or arsenic element or two
The method of any combination of person forms first epitaxial layer 2 in 1 upper surface of substrate.Specifically, the extension or diffusion
Method include depositing operation.In some embodiments of the invention, depositing operation can be used in the 1 upper surface shape of substrate
At first epitaxial layer 2, for example, depositing operation can be selected from electron beam evaporation, chemical vapor deposition, atomic layer deposition,
One of sputtering.Preferably, the first epitaxial layer 2, chemical vapor deposition are formed using chemical vapor deposition on the substrate 1
Including process for vapor phase epitaxy.In production, chemical vapor deposition uses process for vapor phase epitaxy mostly, in 1 upper surface of substrate
The first epitaxial layer 2 is formed using process for vapor phase epitaxy, process for vapor phase epitaxy can be improved the perfection of silicon materials, improve device
Integrated level reaches raising minority carrier life time, reduces the leakage current of storage element.Preferably, first epitaxial layer 2 and the substrate
1 is all that silicon materials are made, so that the substrate 1 and first epitaxial layer 2 have the silicon face of same crystal structure, to keep
Control to dopant type and concentration.In addition, first epitaxial layer 2 reduces string while optimizing the breakdown voltage of PN junction
Join resistance, improves device speed under moderate current strength.
It please refers to attached drawing 4, executes step S2, specifically: the of the first conduction type is formed in first epitaxial layer 2
Second buried layer 4 of one buried layer 3 and the second conduction type, and at least partly surface exposure of first buried layer 3 and the second buried layer 4
In 2 upper surface of the first epitaxial layer, the doping concentration of second buried layer 4 is higher than the doping concentration of first epitaxial layer 2.
First buried layer 3 and second buried layer 4 can also pass through ion implanting and/or diffusion by being epitaxially-formed
Method formed.Further, first buried layer 3 can by being epitaxially-formed, can also by ion implanting and/or
The method for spreading any combination of P elements or arsenic element or both is formed.Similarly, second buried layer 4 can be raw by extension
It is long to be formed, ion implanting and/or diffusion boron element or phosphide element or aluminium element or the side of any combination of three can also be passed through
Method is formed.Preferably, the method that ion implanting can be used forms first buried layer 3 and second buried layer 4, passes through ion
Injection forms first buried layer 3 and second buried layer 4 can accurately control impurity accumulated dose, depth distribution and face it is uniform
Property, spreading again for original impurity can be prevented, while can realize self-aligned technology, to reduce capacity effect.Of the invention one
In a little embodiments, at least partly surface exposure of first buried layer 3 and second buried layer 4 is in first epitaxial layer 2
The upper surface of upper surface, i.e., described first buried layer 3 and second buried layer 4 is exposed to first epitaxial layer 2.
Attached drawing 5 is please referred to, step S3 is executed, specifically: the first conduction type is formed in 2 upper surface of the first epitaxial layer
The second epitaxial layer 5, and the doping concentration of first buried layer 3 be higher than second epitaxial layer 5 doping concentration.Wherein,
A kind of fixed side is not limited in the mode that 2 upper surface of the first epitaxial layer forms the second epitaxial layer 5 of the first conduction type
Formula can be used extension, diffusion and/or the method for injection and form second epitaxial layer 5, specifically, the extension or diffusion
Method include depositing operation.It is possible to further use extension, diffusion and/or injection P elements or arsenic element or both
The method of any combination forms second epitaxial layer 5.In some embodiments of the invention, using depositing operation described
One epitaxial layer, 2 upper surface forms the second epitaxial layer 5, for example, depositing operation can be selected from electron beam evaporation, chemical vapor deposition
One of product, atomic layer deposition, sputtering.Wherein, chemical vapor deposition includes process for vapor phase epitaxy, it is preferred that described
One epitaxial layer, 2 upper surface forms the second epitaxial layer 5 using process for vapor phase epitaxy, and the complete of silicon materials can be improved in process for vapor phase epitaxy
Beauty improves the integrated level of device, reaches raising minority carrier life time, reduces the leakage current of storage element.Second epitaxial layer 5 will
The upper surface of first epitaxial layer 2 covers, and is equipped with certain thickness.
Further, the doping concentration of first buried layer 3 is different from the doping concentration of second epitaxial layer 5.It is preferred that
, the doping concentration of first buried layer 3 is higher than the doping concentration of second epitaxial layer 5, and first buried layer 3 is heavily doped
Miscellaneous, so that the resistivity of first buried layer 3 is lower than the resistivity of second epitaxial layer 5, electric current can be low along resistivity
Buried layer forms branch in parallel without being spilt in second epitaxial layer 5 outside to 2 downside of the first epitaxial layer.
Attached drawing 6 and Fig. 8 are please referred to, step S4 is executed, specifically: it is formed through second epitaxial layer 5 and extends to institute
State the first groove 6 of the first buried layer 3, and formed be located at 6 upside of first groove and with 6 connection of first groove the
Two grooves 9.In some embodiments of the invention, mask material, the exposure mask are prepared in the upper surface of second epitaxial layer 5
Material is specially the first photoresist, is formed on first photoresist layer by etching and is extended through second epitaxial layer 5
The extremely first groove 6 of first buried layer 3, then remove first photoresist.Wherein, the method for etching include dry etching and
Wet etching, it is preferred that the method for the etching used is dry etching, and dry etching includes photoablation, gaseous corrosion, plasma
Body corrosion etc., and dry etching easily realizes that automation, treatment process are not introduced into pollution, cleannes height.In some realities of the invention
It applies in example, the bottom surface of the first groove 6 is connected with first buried layer 3, for example, the bottom surface of the first groove 6 can be with
It extends in first buried layer 3, the bottom surface of the first groove 6 can also be connect with the upper surface of first buried layer 3, be protected
The bottom surface for demonstrate,proving the first groove 6 is contacted with first buried layer 3.Further, formation and institute on the upside of the first groove 6
The coaxial second groove 9 of first groove 6 is stated, and the internal diameter of the second groove 9 is greater than the internal diameter of the first groove 6.Institute
It states second groove 9 to be located in second epitaxial layer 5, and the side of the second groove 9 is connected with first injection region 7
It connects.It should be noted that the first groove 6 is interconnected with the second groove 9, for more quickly and effectively described the
Packing material in one groove 6 and the second groove 9.About the shape of the first groove 6 and the second groove 9, ability
Field technique personnel can select groove of different shapes, the first groove 6 and second ditch according to the electric property of device
The shape of slot 9 can be rectangle groove, can also can also be U-shaped groove with square trench, it might even be possible to it is ball cunette slot, etc.
Deng.
Attached drawing 7 is please referred to, step S5 is executed, specifically, forms the first conduction type in 5 upper surface of the second epitaxial layer
The first injection region 7 and the second conduction type the second injection region 8, and by first injection region 7 connect it is described first injection
Area 7, the doping concentration of first injection region 7 are higher than the doping concentration of second epitaxial layer 5.In some implementations of the invention
In example, mask material is prepared in the upper surface of second epitaxial layer 5, the mask material is specially the second photoresist, in institute
State the first note that the method on the second photoresist layer by photoetching forms the first conduction type in second epitaxial layer 5 respectively
Enter the second injection region 8 of area 7 and the second conduction type, wherein first injection region 7 it is adjacent with second injection region 8 and
Part connects.The first conductive-type is formed using ion implanting and/or the method for diffusion in the upper surface of second photoresist layer
First injection region 7 of type and the second injection region 8 of the second conduction type, then get rid of second photoresist layer.Further,
Using ion implanting and/or boron element or phosphide element or aluminium element or three are spread in the upper surface of second photoresist layer
The method of any combination forms the first injection region 7 of the first conduction type；Simultaneously also in the upper surface of second photoresist layer
The of the second conduction type is formed using the method for ion implanting and/or any combination of diffusion P elements or arsenic element or both
Second photoresist layer is finally got rid of in two injection regions 8 again.
Further, second buried layer 4 is oppositely arranged with second injection region 8.Preferably, by second buried layer
4 are set to the underface of first injection region 7, and second injection region 8 is set in first injection region 7
Between, to form electric current successively from second injection region 8, first injection region 7, second epitaxial layer 5 and described
The conductive path of two buried layers 4.The doping concentration of first injection region 7 is different from the doping concentration of second epitaxial layer 5.It is excellent
Choosing, the doping concentration of first injection region 7 is higher than the doping concentration of second epitaxial layer 5, when electric current passes through, adulterates dense
It spends high first injection region 7 to be connected prior to second epitaxial layer 5, be injected to form the electric current by described second
Area 8 and first injection region 7 form PN junction.
Further, the doping concentration of first injection region 7 is different from the doping concentration of first buried layer 3.It is preferred that
, the doping concentration of first injection region 7 is higher than the doping concentration of first buried layer 3, in order to adjust the power device
The breakdown voltage of part protection chip.
Further, the doping concentration of second injection region 8 is different from the doping concentration of second buried layer 4.It is preferred that
, the doping concentration of second buried layer 4 is higher than the doping concentration of second injection region 8, in order to adjust the power device
The breakdown voltage of part protection chip.
Attached drawing 9 is please referred to, executes step S6, specifically: forming institute in the first groove 6 and the second groove 9
The polysilicon layer 10 of the first buried layer 3 connection is stated, and the polysilicon layer 10 is connected with first injection region 7.By institute
First groove 6 and 9 connection of second groove are stated, passes through extension, diffusion in the first groove 6 and the second groove 9
And/or the method for injection forms the polysilicon layer 10, it is preferred that the polysilicon in the polysilicon layer 10 is specially that doping is more
Crystal silicon, DOPOS doped polycrystalline silicon reduce cut-in voltage under high current, can also can reach raising by adjusting polysilicon doping concentration
The effect of breakdown voltage.Polysilicon is filled in the first groove 6 and the second groove 9, so that the polysilicon layer 10
Form the conductive channel being electrically connected respectively with first buried layer 3 and first injection region 7.Further, the polysilicon
Layer 10 is formed by intrinsic polysilicon doping phosphonium ion or boron ion, and those skilled in the art can be according to the structure of device
Different doped polycrystalline silicon-types is selected, the polysilicon in the polysilicon layer 10 can be p-type polysilicon, be also possible to N-type
Polysilicon.Specifically, the extension, diffusion and/or the method for injection include depositing operation.In some embodiments of the present invention
In, depositing operation can be used in 1 upper surface of substrate and form first epitaxial layer 2, for example, depositing operation can be choosing
From one of electron beam evaporation, chemical vapor deposition, atomic layer deposition, sputtering.Preferably, using low on the substrate 1
Pressure chemical vapor deposits described in (abbreviation LPCVD, i.e. Low Pressure Chemical Vapor Deposition) formation
Polysilicon layer 10, the purity is high of the polysilicon layer 10 of formation, uniformity are good.
Attached drawing 9 is please referred to, step S7 is executed, specifically: forming dielectric layer 11 in the upper surface of second epitaxial layer 5.
Dielectric layer 11 is formed in the upper surface of second epitaxial layer 5.The material of the dielectric layer 11 is silicon oxide or silicon nitride or nitrogen
Silica specifically can form the dielectric layer 11 by using sputtering or thermal oxidation method or chemical vapor deposition process.It is preferred that
, the dielectric layer 11 is the silicon oxide layer that thermal oxide is formed, and in subsequent doping step, the silicon oxide layer is as protection
Layer, and by the interlayer insulating film as resulting devices.In addition, the dielectric layer 11 is equipped with certain thickness, so that being given an account of
Matter layer 11 plays the role of that electric current and insulation is isolated.
Further, one end of the polysilicon layer 10 through second epitaxial layer 5 and extends to first buried layer
3, the other end is connect with first injection region 7 and the dielectric layer 11 respectively.It should be noted that the polysilicon layer 10 is first
It is formed, then is formed in the second groove 9, and the upper surface of the polysilicon layer 10 is higher than in the first groove 6
The upper surface of second epitaxial layer 5 so that the polysilicon layer 10 is not only connect with first injection region 7, also with it is described
Dielectric layer 11 connects.
Attached drawing 10 is please referred to, step S8 is executed, specifically: first electrode 12 is formed, the first electrode 12 includes running through
The dielectric layer 11 simultaneously extends to the first part 121 of second injection region 8 and is formed in the of 11 surface of dielectric layer
Two parts 122；The second electrode 13 connecting with the substrate 1 is formed in the lower surface of the substrate 1.Firstly, passing through etching shape
At through the dielectric layer 11 and extending to the first contact hole (not shown) of second injection region 8.Preferably, pass through dry method
Etching forms first contact hole, and dry etching includes photoablation, gaseous corrosion, plasma etching etc., and dry etching
Easily realize that automation, treatment process are not introduced into pollution, cleannes height.Metal material is filled into first contact hole, is formed
First part 121, and metal material is covered in 11 upper surface of dielectric layer, to form the second part 122.Described first
Part 121 and the second part 122 form interconnected the first metal layer, i.e. first electrode 12.The first electrode 12
Be electrically connected by the first part 121 with second injection region 8 so that circuit flow to second injection region 8 with it is described
The access that first injection region 7 is formed, to form PN junction.In addition, 1 lower surface of substrate is metallized, the second gold medal is formed
Belong to layer, to form the second electrode 13 being electrically connected with the substrate 1.The electric current is by the substrate 1 along described second
Electrode 13 flows to external circuit.
Further, first buried layer 3 includes the first sub- buried layer and for being respectively arranged at 4 two sides of the second buried layer
Two sub- buried layers, first injection region 7 include the first sub- injection region and second for being respectively arranged at 8 two sides of the second injection region
Sub- injection region, the polysilicon layer 10 include the first polysilicon connecting with the described first sub- buried layer and the first sub- injection region
Layer 10, and the second polysilicon layer 10 being connect with the described second sub- buried layer and the second sub- injection region, so that entire described
Power device protection chip form symmetrical device architecture, electric current pass sequentially through the first electrode 12, the second injection region 8,
Second epitaxial layer 5, the second buried layer 4, the first epitaxial layer 2, substrate 1 and second electrode 13 are formed by except conductive path, point
It Xing Cheng not the symmetrical branch in the left and right sides.
It is understood that the first groove 6 is deep trench, by the first groove 6 and the second groove 9
It is interior to form the polysilicon layer 10 being electrically connected respectively with first buried layer 3 and first injection region 7, by the polysilicon
Layer 10 forms conductive channel, for conduction, and first injection region 7 is electrically connected with first buried layer 3, forms one simultaneously
The conductive path of connection.In addition, first buried layer 3 and the polysilicon layer 10 are symmetrically distributed setting, it is two-way to form 3 tunnels
Parallel equivalent circuit, due to diode unilateral conduction and have compared with trifle capacitor, efficiently reduce access capacitor, from
And the parasitic capacitance of device can be reduced in high-frequency circuit.
Referring next to attached drawing, a kind of power device protection chip is elaborated.
As shown in Fig. 2, present invention implementation provides a kind of power device protection chip, shown power device protects chip packet
It includes:
The substrate 1 of first conduction type；
First epitaxial layer 2 of the second conduction type is grown on 1 upper surface of substrate；
First buried layer 3 of the first conduction type and the second buried layer 4 of the second conduction type, are formed in first epitaxial layer
In 2, and at least partly surface exposure of first buried layer 3 and the second buried layer 4 is in first epitaxial layer, 2 upper surface, described
The doping concentration of second buried layer 4 is higher than the doping concentration of first epitaxial layer 2；
Second epitaxial layer 5 of the first conduction type is formed in 2 upper surface of the first epitaxial layer, and described first buries
The doping concentration of layer 3 is higher than the doping concentration of second epitaxial layer 5；
First injection region 7 of the first conduction type and the second injection region 8 of the second conduction type, are formed in outside described second
Prolong 5 upper surface of layer, and first injection region 7 is connected with second injection region 8, the doping of first injection region 7 is dense
Degree is higher than the doping concentration of second epitaxial layer 5；
Polysilicon layer 10, through second epitaxial layer 5 and respectively with first injection region 7 and first buried layer 3
Connection；
Dielectric layer 11 is formed in the upper surface of second epitaxial layer 5；
First electrode 12, including through the dielectric layer 11 and extending to 121 He of first part of second injection region 8
It is formed in the second part 122 on 11 surface of dielectric layer；
Second electrode 13 is formed in the lower surface of the substrate 1 and connect with the substrate 1.
Specifically, first conduction type is one of p-type doping and n-type doping, and second conduction type is P
Type doping and the another kind in n-type doping.
Special to illustrate herein for convenience of description: first conduction type can be n-type doping, so that described second is conductive
Type is p-type doping；First conduction type can also adulterate for p-type, so that second conduction type is n-type doping.
It is understood that when first conduction type is p-type doping, when second conduction type is n-type doping, the substrate
1, first buried layer 3, second epitaxial layer 5 and first injection region 7 are that p-type is adulterated, first epitaxial layer 2,
Second buried layer 4 and second injection region 8 are N-type epitaxy layer.When first conduction type be n-type doping, it is described
When second conduction type is that p-type is adulterated, the substrate 1, first buried layer 3, second epitaxial layer 5 and first injection
Area 7 is n-type doping, and first epitaxial layer 2, second buried layer 4 and second injection region 8 are p-type epitaxial layer.?
It in next embodiment, is adulterated by p-type of first conduction type, second conduction type is for n-type doping
It is described, but is defined not to this.
Specifically, P type substrate and p-type extension belong to P-type semiconductor, and N-type substrate and N-type extension belong to N-type and partly lead
Body.The P-type semiconductor is the silicon wafer for adulterating triad, such as any group of boron element or phosphide element or aluminium element or three
It closes.The N-type semiconductor is any combination of the silicon wafer for adulterating pentad, such as P elements or arsenic element or both.
In some embodiments of the invention, as shown in Fig. 2, power device protection chip includes the first conduction type
Substrate 1 and the second conduction type the first epitaxial layer 2, first epitaxial layer 2 is grown on 1 upper surface of substrate.Tool
Body, the substrate 1 is the carrier in integrated circuit, and the substrate 1 plays the role of support, and the substrate 1 also assists in described
The work of integrated circuit.The substrate 1 can be silicon substrate, or Sapphire Substrate can also be silicon carbide substrates, very
It extremely can be silicon Chu substrate, it is preferred that the substrate 1 is silicon substrate, this is because silicon substrate material has low cost, big ruler
Very little, conductive feature, avoids edge effect, can increase substantially yield.First extension of second conduction type
Layer 2 is grown on 1 upper surface of substrate of first conduction type, reacts simultaneously, when electric current passes sequentially through outside described first
When prolonging layer 2 and the substrate 1, PN junction is formed.
In some embodiments of the invention, as shown in Fig. 2, power device protection chip further includes the first conductive-type
First buried layer 3 of type and the second buried layer 4 of the second conduction type, first buried layer 3 and second buried layer 4 are both formed in institute
It states in the first epitaxial layer 2, and at least partly surface exposure of first buried layer 3 and the second buried layer 4 is in first epitaxial layer 2
Upper surface, the doping concentration of second buried layer 4 are higher than the doping concentration of first epitaxial layer 2.Further, described first
Buried layer 3 and second buried layer 4 are adjacent, and first buried layer 3 and second buried layer 4 can be spaced apart from each other, can also be with
It is connected with each other.In addition, first buried layer 3 and second buried layer 4 are heavy doping, to reduce first buried layer 3
With the resistivity of second buried layer 4.Preferably, the doping concentration of second buried layer 4 is higher than mixing for first epitaxial layer 2
Miscellaneous concentration, electric current can be along low second buried layers 4 of resistivity to 2 downside of the first epitaxial layer, to change electric current
Path is equivalent to and reduces series resistance.
In some embodiments of the invention, as shown in Fig. 2, power device protection chip further includes the first conductive-type
Second epitaxial layer 5 of type, second epitaxial layer 5 are formed in 2 upper surface of the first epitaxial layer.First epitaxial layer, 2 He
The thickness of second epitaxial layer 5 depends on the physical size and the device fabrication of the semiconductor devices to be realized
Silicon loss in the process.Second epitaxial layer 5 is grown on 2 upper surface of the first epitaxial layer, plays reduction semiconductor device
The effect of the leakage current of PN junction in part.
In some embodiments of the invention, as shown in Fig. 2, power device protection chip further includes the first conductive-type
First injection region 7 of type and the second injection region 8 of the second conduction type, first injection region 7 and 8 shape of the second injection region
Second epitaxial layer, 5 upper surface described in Cheng Yu, and first injection region 7 is connected with second injection region 8, first note
The doping concentration for entering area 7 is higher than the doping concentration of second epitaxial layer 5.In some embodiments of the invention, described first
Injection region 7 and second injection region 8 are heavy doping, due to the conduction of first injection region 7 and second injection region 8
Type is different, therefore first injection region 7 and second injection region 8 are reacted, to form the PN of high-dopant concentration
Knot.It should be noted that first injection region 7 and second injection region 8 it is adjacent and part connect so that electric current is along institute
It states the PN junction that the first injection region 7 and second injection region 8 are formed and forms branch in parallel.Further, first injection
The doping concentration in area 7 is higher than the doping concentration of first buried layer 3.Further, the doping concentration of second buried layer 4 is higher than
The doping concentration of second injection region 8.Further, second buried layer 4 is oppositely arranged with second injection region 8.
In some embodiments of the invention, as shown in Fig. 2, power device protection chip further includes polysilicon layer
10, the polysilicon layer 10 connects through second epitaxial layer 5 and respectively with first injection region 7 and first buried layer 3
It connects.The power device protection chip even semiconductor devices monocrystalline silicon multi-purpose greatly is made, and the polysilicon layer 10 is electric respectively
First injection region 7 and first buried layer 3 are connected, electric current flows directly into described after through first injection region 7
First buried layer 3, so that discharging efficiency is higher.Specifically, the polysilicon layer 10 has very high compatibility in monocrystalline silicon.
In some embodiments of the invention, as shown in Fig. 2, power device protection chip further includes dielectric layer 11,
The dielectric layer 11 is formed in the upper surface of second epitaxial layer 5.The dielectric layer 11 is for being isolated second epitaxial layer
5。
Further, one end of the polysilicon layer 10 through second epitaxial layer 5 and extends to first buried layer
3, the other end is connect with first injection region 7 and the dielectric layer 11 respectively.One end of the polysilicon layer 10 is through described
Second epitaxial layer 5 simultaneously extends to first buried layer 3, can be one end of the polysilicon layer 10 through second epitaxial layer
It 5 and extends in first buried layer 3, be also possible to one end of the polysilicon layer 10 through second epitaxial layer 5 and prolong
The upper surface for extending to first buried layer 3 guarantees that one end of the polysilicon is contacted with first buried layer 3.More specifically, institute
The other end for stating polysilicon layer 10 extends in the dielectric layer 11 from 5 upper surface of the second epitaxial layer, is formed and is higher than in institute
A protrusion on 5 surface of the second epitaxial layer is stated, in one embodiment of the invention, the protrusion is rectangular or rectangle.It is described convex
It rises and is contacted with the dielectric layer 11, and the side of the protrusion of the polysilicon layer 10 is connect with first injection region 7, due to
The dielectric layer 11 insulate, therefore the other end of the polysilicon layer 10 is electrically connected with first injection region 7.
In some embodiments of the invention, as shown in Fig. 2, power device protection chip further includes first electrode
12, the first electrode 12 includes first part 121 and the shape for running through the dielectric layer 11 and extending to second injection region 8
The second part 122 on 11 surface of dielectric layer described in Cheng Yu；Power device protection chip further includes second electrode 13, and described the
Two electrodes 13 are formed in the lower surface of the substrate 1 and connect with the substrate 1.In some embodiments of the invention, described
First part 121 is through the dielectric layer 11 and extends to second injection region 8, can be the first part 121 and runs through
The dielectric layer 11 simultaneously extends in second injection region 8, is also possible to the first part 121 through the dielectric layer 11
And the upper surface of second injection region 8 is extended to, guarantee that the first part 121 contacts with second injection region 8.It is described
First electrode 12 is specially the first metal layer, and the second electrode 13 is specially second metal layer, the first part 121 and institute
It states and is filled with metal material, the first part 121 and 122 connection of the second part in second part 122 and is collectively formed
The first metal layer.The first metal layer and the second metal layer are equipped with certain thickness.The second metal layer and institute
State the relationship that substrate 1 forms electrical connection.
Further, first buried layer 3 includes the first sub- buried layer and for being respectively arranged at 4 two sides of the second buried layer
Two sub- buried layers, first injection region 7 include the first sub- injection region and second for being respectively arranged at 8 two sides of the second injection region
Sub- injection region, the polysilicon layer 10 include the first polysilicon connecting with the described first sub- buried layer and the first sub- injection region
Layer 10, and the second polysilicon layer 10 being connect with the described second sub- buried layer and the second sub- injection region, the power device
It protects chip overall structure symmetrical and is the first primitive unit cell.
Please refer to the equivalent circuit diagram of the protection chip structure of power device shown in Figure 11.When to 12 He of first electrode
When the second electrode 13 is powered, the electric current flows to the second electrode 13 from the first electrode 12.It should be noted that
The forward and reverse of PN junction formed below is set as p-type with the first conduction type, and second conduction type is set as N-type as this
One embodiment of invention does not limit this to be judged.Electric current passes sequentially through the first electrode 12, described second
Injection region 8, second epitaxial layer 5, second buried layer 4, first epitaxial layer 2, the substrate 1 and the second electrode
13, form a main circuit.Second injection region 8 and second epitaxial layer 5 form reversed PN junction, therefore are formed reversed
First diode a1.Second epitaxial layer 5 and second buried layer 4 form a positive PN junction, therefore form forward direction
Second diode b1.First epitaxial layer 2 and the substrate 1 form a reversed PN junction, therefore form reversed the three or two
Pole pipe c1.The equivalent circuit being made of three diodes is formd in the main circuit.Electric current is passing sequentially through first electricity
When pole 12 and second injection region 8, due to first injection region 7 and the polysilicon layer 10 effect so that electric current according to
It is secondary to be diverted in the polysilicon layer 10 later by second injection region 8, then pass sequentially through first injection region 7, institute
Polysilicon layer 10, first buried layer 3, first epitaxial layer 2, the substrate 1 and the second electrode 13 are stated, forms one
First parallel circuit in parallel.Second injection region 8 and first injection region 7 form reversed PN junction, therefore form anti-
To the 4th diode a2.First buried layer 3 forms positive PN junction with first epitaxial layer 2, therefore forms forward direction
The 5th diode b2.First epitaxial layer 2 forms reversed PN junction with the substrate 1, therefore forms the reversed the 6th
Diode c2.First parallel circuit forms the equivalent circuit being made of three diodes.In addition, due to first buried layer
3 include the described first sub- buried layer and the second sub- buried layer, and first injection region 7 includes the described first sub- injection region and the second son note
Enter area, the polysilicon layer 10 includes first polysilicon layer 10 and the second polysilicon layer 10, therefore the power device is protected
It protects in the structure of chip other than there is a main circuit, also there is symmetrical the first parallel circuit and the second parallel circuit.
In conclusion the claimed power device protection chip of the present invention forms the equivalent circuit of 3 groups of diodes in parallel, due to two
The unilateral conduction of pole pipe and have compared with trifle capacitor, access capacitor is efficiently reduced, so as in high-frequency circuit
Reduce the parasitic capacitance of device.
The technical scheme of the present invention has been explained in detail above with reference to the attached drawings, and improve makes 3 groups according to the technical solution of the present invention
Power device protects integrated chip to together, reduces device area by introducing buried layer technique, reduces technology difficulty, reduce
Device manufacturing cost.Three groups of diodes in parallel, reduce parasitic capacitance, so that the guarantor of improved power device protection chip
Shield characteristic and reliability are all improved.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of power device protects chip characterized by comprising
The substrate of first conduction type；
First epitaxial layer of the second conduction type, is grown on the upper surface of substrate；
First buried layer of the first conduction type and the second buried layer of the second conduction type, are formed in first epitaxial layer, and
At least partly surface exposure of first buried layer and the second buried layer in first epitaxial layer upper surface, second buried layer
Doping concentration is higher than the doping concentration of first epitaxial layer；
Second epitaxial layer of the first conduction type, be formed in first epitaxial layer upper surface, and first buried layer is mixed
Miscellaneous concentration is higher than the doping concentration of second epitaxial layer；
First injection region of the first conduction type and the second injection region of the second conduction type, are formed on second epitaxial layer
Surface, and first injection region is connected with second injection region, the doping concentration of first injection region is higher than described
The doping concentration of second epitaxial layer；
Polysilicon layer is connect through second epitaxial layer and with first injection region and first buried layer respectively；
Dielectric layer is formed in the upper surface of second epitaxial layer；
First electrode is given an account of including running through the dielectric layer and extending to the first part of second injection region and be formed in
The second part of matter layer surface；
Second electrode is formed in the lower surface of the substrate and connect with the substrate.
2. power device according to claim 1 protects chip, which is characterized in that the doping concentration of first injection region
Higher than the doping concentration of first buried layer.
3. power device according to claim 1 protects chip, which is characterized in that the doping concentration of second buried layer is high
Doping concentration in second injection region.
4. power device according to claim 1 protects chip, which is characterized in that second buried layer and second note
Enter area to be oppositely arranged.
5. power device according to claim 1 protects chip, which is characterized in that first buried layer includes being respectively set
The first sub- buried layer and the second sub- buried layer in second buried layer two sides, first injection region include being respectively arranged at described the
The the first sub- injection region and the second sub- injection region of two injection regions two sides, the polysilicon layer include and the described first sub- buried layer and institute
The first polysilicon layer of the first sub- injection region connection is stated, and connect with the described second sub- buried layer and the second sub- injection region
Second polysilicon layer.
6. a kind of production method of power device protection chip comprising:
In the first epitaxial layer of two conduction type of upper surface of substrate growth regulation of the first conduction type；
The first buried layer of the first conduction type and the second buried layer of the second conduction type, and institute are formed in first epitaxial layer
At least partly surface exposure of the first buried layer and the second buried layer is stated in first epitaxial layer upper surface, second buried layer is mixed
Miscellaneous concentration is higher than the doping concentration of first epitaxial layer；
The second epitaxial layer of the first conduction type, and the doping of first buried layer are formed in first epitaxial layer upper surface
Concentration is higher than the doping concentration of second epitaxial layer；
The first groove of first buried layer is formed through second epitaxial layer and extended to, and is formed and is located at described first
Groove upside and the second groove with the first groove connection；
The first injection region of the first conduction type and the second note of the second conduction type are formed in second epitaxial layer upper surface
Enter area, and first injection region is connected into first injection region, the doping concentration of first injection region is higher than described the
The doping concentration of two epitaxial layers；
Form the polysilicon layer that first buried layer connects in the first groove and the second groove, and by the polycrystalline
Silicon layer is connected with first injection region；
Dielectric layer is formed in the upper surface of second epitaxial layer；
First electrode is formed, the first electrode includes running through the dielectric layer and extending to first of second injection region
Divide and be formed in the second part of the dielectric layer surface；
The second electrode connecting with the substrate is formed in the lower surface of the substrate.
7. a kind of production method of power device protection chip according to claim 6, which is characterized in that first note
The doping concentration for entering area is higher than the doping concentration of first buried layer.
8. a kind of production method of power device protection chip according to claim 6, which is characterized in that described second buries
The doping concentration of layer is higher than the doping concentration of second injection region.
9. a kind of production method of power device protection chip according to claim 6, which is characterized in that by described second
Buried layer is oppositely arranged with second injection region.
10. a kind of production method of power device protection chip according to claim 6, which is characterized in that described first
Buried layer includes the first sub- buried layer and the second sub- buried layer for being respectively arranged at second buried layer two sides, and first injection region includes
It is respectively arranged at the first sub- injection region and the second sub- injection region of second injection region two sides, the polysilicon layer includes and institute
State the first polysilicon layer that the first sub- buried layer is connected with the described first sub- injection region, and with the described second sub- buried layer and described
Second polysilicon layer of two sub- injection region connections.
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| CN111584480A (en) * | 2020-04-17 | 2020-08-25 | 深圳方正微电子有限公司 | Semiconductor device and method for manufacturing the same |
| CN111584480B (en) * | 2020-04-17 | 2023-10-31 | 深圳方正微电子有限公司 | Semiconductor device and method for manufacturing the same |
| CN113097305A (en) * | 2021-03-26 | 2021-07-09 | 深圳市金誉半导体股份有限公司 | Field-effect tube and preparation method thereof |
| CN113690231A (en) * | 2021-08-20 | 2021-11-23 | 安芯半导体技术(深圳)有限公司 | Surge protection chip and preparation method thereof |
| CN114023737A (en) * | 2021-11-05 | 2022-02-08 | 深圳市鑫飞宏电子有限公司 | Electrostatic protection chip based on power management and preparation method thereof |
| CN114023737B (en) * | 2021-11-05 | 2023-07-21 | 深圳市鑫飞宏电子有限公司 | Electrostatic protection chip based on power management and preparation method thereof |
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