CN109037072A - Fin field effect pipe and forming method thereof - Google Patents
Fin field effect pipe and forming method thereof Download PDFInfo
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- CN109037072A CN109037072A CN201810802504.3A CN201810802504A CN109037072A CN 109037072 A CN109037072 A CN 109037072A CN 201810802504 A CN201810802504 A CN 201810802504A CN 109037072 A CN109037072 A CN 109037072A
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Abstract
A kind of fin field effect pipe and forming method thereof, wherein the forming method of fin field effect pipe includes: offer substrate；It forms the germanium tin silicon layer of covering substrate and covers the semiconductor layer of germanium tin silicon layer, substrate, germanium tin silicon layer and semiconductor layer include first area, second area and third region；Etch the semiconductor layer of second area and the germanium tin silicon layer of segment thickness, form several discrete fins, fin includes first part and the second part positioned at first part surface, and the orientation between the orientation between adjacent fin and first area, second area and third region is mutually perpendicular to；It is developed across the gate structure of the fin, and the top of gate structure covering fin and side wall；Doped region is formed in the semiconductor layer and germanium tin silicon layer in the first area and third region.The present invention improves fin field effect pipe channel region carrier mobility, optimizes fin field effect pipe electric property.
Description
Technical field
The present invention relates to field of semiconductor fabrication technology, in particular to a kind of fin field effect pipe and forming method thereof.
Background technique
With the continuous development of semiconductor process technique, process node is gradually reduced, and rear grid (gate-last) technique obtains
It is widely applied, to obtain ideal threshold voltage, improves device performance.But when the characteristic size of device further declines
When, even if the structure of conventional metal-oxide-semiconductor field effect transistor also can no longer meet the demand to device performance, fin using rear grid technique
Formula field effect transistor (Fin FET) has obtained extensive concern as a kind of multi-gate device.Fin formula field effect transistor can
It is effectively improved the short-channel effect of transistor, improves the performance of device.
A kind of fin formula field effect transistor of the prior art includes: semiconductor substrate, is formed in the semiconductor substrate
The fin of protrusion, fin is generally by obtaining after semiconductor substrate etching；Dielectric layer covers the semiconductor substrate
A part of the side wall of surface and fin；Gate structure, across on the fin, cover the fin atop part and
Side wall, gate structure include gate dielectric layer and the gate electrode on gate dielectric layer.For fin formula field effect transistor, fin
The part that the side wall of top and two sides is in contact with gate structure all becomes channel region, that is, has multiple grid, be conducive to increase
Driving current improves device performance.
However, the electric property for the fin field effect pipe that the prior art is formed is to be improved.
Summary of the invention
Problems solved by the invention is to provide a kind of fin field effect pipe and forming method thereof, improves fin field effect pipe
Channel region carrier mobility reduces the break-through leakage current of fin field effect pipe, optimizes the electric property of fin field effect pipe.
To solve the above problems, the present invention provides a kind of forming method of fin field effect pipe, comprising: provide substrate；Shape
At the germanium tin silicon layer of covering substrate and the semiconductor layer of covering germanium tin silicon layer, and the lattice constant of semiconductor layer material is greater than
The lattice constant of germanium tin silicon layer material, the substrate, germanium tin silicon layer and semiconductor layer include the first area being arranged successively,
Two regions and third region；The semiconductor layer of the second area and the germanium tin silicon layer of segment thickness are etched, described second
Region forms several discrete fins, and the fin includes first part's fin and positioned at the second of first part's fin portion surface
Part fin, first part's fin material is identical as germanium tin silicon layer material, second part fin material and semiconductor layer material phase
Together, and the orientation between the orientation between adjacent fin and first area, second area and third region is mutually hung down
Directly；It is developed across the gate structure of the fin, and the top of gate structure covering fin and side wall；In firstth area
Doped region is formed in the semiconductor layer and germanium tin silicon layer in domain and third region.
Optionally, the material of the substrate is silicon；The material of the semiconductor layer is germanium or tin germanium.Optionally, formation
When fin field effect pipe is NMOS device, the material of the semiconductor layer is germanium；The fin field effect pipe of formation is PMOS device
When, the material of the semiconductor layer is tin germanium.Optionally, before the germanium tin silicon layer for forming covering substrate, in the substrate table
Face forms buffering germanium layer；Buffering germanium layer, germanium tin silicon layer and semiconductor layer are formed using epitaxy technique.Optionally, the germanium tin
In silicon layer, the atomic percent of germanium is 50% to 70%, and the atomic percent of tin is 5% to 10%；The material of the semiconductor layer
When material is tin germanium, the atomic percent of tin is 2% to 10% in semiconductor layer.Optionally, several discrete fins are formed
Processing step include: to form several discrete mask layers in the semiconductor layer surface of the second area；With secondth area
The mask layer in domain is exposure mask, etches the germanium tin silicon layer of the semiconductor layer and segment thickness to form several discrete fins.
Optionally, several discrete mask layers are also located at the semiconductor layer surface of first area and third region；Described second
The semiconductor layer surface and exposure mask layer surface in region form pseudo- grid；Semiconductor layer table in the first area and third region
Face and exposure mask layer surface form dielectric layer, flush at the top of the dielectric layer with pseudo- grid top；The pseudo- grid are removed, expose the
The semiconductor layer surface and exposure mask layer surface in two regions.Optionally, the material of the pseudo- grid is amorphous carbon or siliceous anti-
Reflecting material；After forming the pseudo- grid, further comprises the steps of: and form the first side wall in the pseudo- grid sidewall surfaces；It is being formed
After the fin, further comprises the steps of: semiconductor layer sidewall surfaces after etching and germanium tin silicon layer sidewall surfaces form the
Two side walls.
Correspondingly, the present invention provides a kind of fin field effect pipe, comprising: substrate, the substrate include be arranged successively
One region, second area and third region；Germanium tin silicon layer, Yi Jiwei positioned at the first area and third substrate areas surface
In the semiconductor layer of germanium tin silicon surface, and the lattice constant of semiconductor layer material is greater than the lattice constant of germanium tin silicon layer material；
Positioned at the germanium tin silicon layer of the second area substrate surface, and the thickness of the germanium tin silicon layer of second area is less than first area and the
The thickness of the germanium tin silicon layer in three regions；Positioned at several discrete fins of the second area germanium tin silicon surface, the fin
Including first part and positioned at the second part fin of first part's fin portion surface, first part's fin material and germanium tin silicon layer
Material is identical, and second part fin material is identical as semiconductor layer material；Across the gate structure of the fin, and the grid
Structure covers top and the side wall of fin；Doping in the semiconductor layer and germanium tin silicon layer in first area and third region
Area.
Optionally, there is buffering germanium layer between the substrate and germanium tin silicon layer；The material of the semiconductor layer is germanium or tin
Germanium.Optionally, in the germanium tin silicon layer, the atomic percent of germanium is 50% to 70%, the atomic percent of tin be 5% to
10%；When the material of the semiconductor layer is tin germanium, the atomic percent of tin is 2% to 10% in semiconductor layer.Optionally, also
It include: the dielectric layer positioned at the semiconductor layer surface of first area and third region, the dielectric layer top and gate structure top
Portion flushes.
The present invention also provides a kind of forming methods of fin field effect pipe, comprising: provides substrate, the substrate includes successively
First area, second area and the third region of arrangement；The substrate for etching the segment thickness of the second area, described second
Region forms several discrete fins, and the orientation between adjacent fin and first area, second area and third region
Between orientation be mutually perpendicular to；It is formed and is covered in fin partial sidewall surface and second area substrate surface
First grid, the carrier in the first grid capture portion fin；It is developed across the second grid of the fin, described
Two grids are located at first grid surface and cover top and the side wall of fin；Substrate in the first area and third region
Interior formation doped region.
Optionally, the material of the first grid is the polysilicon or metal material of polysilicon, p-type doping, wherein metal
The work function of material is 4.9ev to 5.9ev；It is described before forming the first grid, further comprise the steps of: to be formed and be covered in fin
The gate dielectric layer at portion top and side wall；Cap rock is formed on the gate dielectric layer surface.Optionally, the material of the cap rock is TiN
Or TaN；The first grid with a thickness of 10 nanometers to 50 nanometers；The material of the second grid be Cu, Al, W, Pt, Ag or
Au.Optionally, the processing step for forming the first grid includes: to form the first grid film for being covered in the gate dielectric layer；
It is etched back to the first grid film, etching removes the first grid film being located at the top of fin and in residual substrate
The first grid film of segment thickness, forms first grid, and the first grid top surface is lower than fin top surface.It is optional
, the processing step of formation several discrete fins includes: the substrate in the first area, second area and third region
Surface forms several discrete mask layers；It after forming the mask layer, is formed before fin, is further comprised the steps of: described
The substrate and exposure mask layer surface of second area form pseudo- grid；The first area and third region substrate surface and cover
Film surface forms dielectric layer, flushes at the top of the dielectric layer with pseudo- grid top；The pseudo- grid are removed, second area is exposed
Substrate and exposure mask layer surface；Using the mask layer of the second area as exposure mask, the substrate of etched portions thickness is several to be formed
Discrete fin.
Correspondingly, the present invention also provides a kind of fin field effect pipes, comprising: substrate, the substrate include being arranged successively
First area, second area and third region, and the base top in first area and third region is higher than the substrate of second area
Top；Positioned at several discrete fins of the substrate surface of the second area, and the orientation between adjacent fin and the
Orientation between one region, second area and third region is mutually perpendicular to；Positioned at the fin partial sidewall surface, with
And the first grid of second area substrate surface, the carrier in the first grid capture portion fin；Across the fin
Second grid, the second grid be located at first grid surface and cover fin top and side wall；Positioned at first area and
The intrabasement doped region in third region.
Optionally, the material of the first grid is the polysilicon or metal material of polysilicon, p-type doping, wherein metal
The work function of material is 4.9ev to 5.9ev；The top of the fin and sidewall surfaces have gate dielectric layer；The gate dielectric layer
Surface has cap rock.Optionally, the first grid with a thickness of 10 nanometers to 50 nanometers.
Compared with prior art, technical solution of the present invention has the advantage that
The present invention provides a kind of forming method of fin field effect pipe, forms the germanium tin silicon layer and covering germanium of covering substrate
The semiconductor layer of tin silicon layer, and the lattice constant of semiconductor layer material is greater than the lattice constant of germanium tin silicon layer material, therefore in institute
The semiconductor layer for stating the formation of germanium tin silicon surface has compression；When the semiconductor layer and segment thickness for etching second area
After germanium tin silicon layer is to form fin, the fin includes first part's fin and positioned at second of first part's fin portion surface
Divide fin, the compression inside the second part fin is enhanced, therefore when the fin field effect pipe formed is PMOS device
When part, the channel region carrier mobility of the fin field effect pipe increases, and optimizes the electric property of fin field effect pipe.Together
When, since the band gap of germanium tin silicon layer material is relatively large, for NMOS device and PMOS device, advantageously reduce fin
The parasitic leakage current of field-effect tube.Also, since the semiconductor layer of first area and third region does not undergo etching technics, so that
Doped region has good surface topography, is conducive to form the conductive plunger of high quality on doped region surface.
Further, when the fin field effect pipe of formation is NMOS device, the material of semiconductor layer is germanium, and electronics is in germanium material
In have biggish mobility；When the fin field effect pipe of formation is PMOS device, the material of semiconductor layer is tin germanium, and hole exists
There is biggish mobility in tin germanium material.Therefore the electric property of NMOS device and PMOS device can effectively be improved.
Further, before forming germanium tin silicon layer, buffering germanium layer is formed in substrate surface, the buffering germanium layer material
Lattice constant is located between silicon and the lattice constant of germanium tin silicon, avoids bad shadow caused by lattice constant mutation between layers
It rings.
The present invention also provides a kind of superior fin field effect pipes of structural behaviour, if second area germanium tin silicon surface has
Do discrete fin, the fin includes first part's fin and the second part fin positioned at first part's fin portion surface,
First part's fin material is identical as germanium tin silicon layer material, and second part fin material is identical as semiconductor layer material, and partly leads
The lattice constant of body layer material is greater than the lattice constant of germanium tin silicon layer material, therefore has biggish pressure inside second part fin
Stress, to be conducive to improve the channel region carrier mobility of fin field effect pipe.Simultaneously as second area germanium tin silicon layer has
There is relatively large band gap, is conducive to inhibit the parasitic leakage current in fin field effect pipe.
The present invention also provides a kind of forming method of fin field effect pipe, the substrate for etching second area segment thickness is formed
After several discrete fins, the first grid for being covered in fin partial sidewall surface and second area substrate surface is formed,
It is developed across the second grid of fin, the second grid is located at first grid surface and covers top and the side wall of fin.Institute
The carrier in first grid capture portion fin is stated, the excess carriers in the fin of substrate can be discharged, effectively
Inhibit the break-through electrical leakage problems of fin field effect pipe, improves the electric property of fin field effect pipe.Simultaneously as first area and
The substrate in third region does not undergo etching technics, so that doped region has good surface topography.
Further, first grid with a thickness of 10 nanometers to 50 nanometers.If the thickness of first grid is excessively thin, it is higher than first
Excess carriers in the fin of grid are still difficult to be released, if the thickness of first grid is blocked up, the thickness of second grid will
It is excessively thin, it is easy to cause the gate structure of fin field effect pipe excessively weak to the control ability of channel region.
The present invention also provides a kind of superior fin field effect pipes of structural behaviour, comprising: is located at second area substrate surface
Several discrete fins；Positioned at fin partial sidewall surface and the first grid of second area substrate surface；Across fin
Second grid, the second grid be located at first grid surface and cover fin top and side wall.The first grid energy
Enough excess carriers discharged in the fin of substrate, improve the break-through electrical leakage problems of fin field effect pipe.
Detailed description of the invention
Fig. 1 to Figure 11 is the structural schematic diagram for the fin field effect pipe forming process that one embodiment of the invention provides；
Figure 12 to Figure 18 be another embodiment of the present invention provides fin field effect pipe forming process structural schematic diagram.
Specific embodiment
It can be seen from background technology that the electric property for the fin field effect pipe that the prior art is formed is to be improved.
For this purpose, the present invention provides a kind of fin field effect pipe and forming method thereof, optimize the electrical property of fin field effect pipe
Energy.To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to of the invention specific
Embodiment is described in detail.
Fig. 1 to Figure 11 is the structural schematic diagram for the fin field effect pipe forming process that one embodiment of the invention provides.
Fig. 1 and Fig. 2 is please referred to, Fig. 1 is top view, and Fig. 2 is the schematic diagram of the section structure of the Fig. 1 along the direction AA1: providing substrate
100；It forms the germanium tin silicon layer 102 of covering substrate 100 and covers the semiconductor layer 103 of germanium tin silicon layer 102, and semiconductor layer
The lattice constant of 103 materials is greater than the lattice constant of 102 material of germanium tin silicon layer, the substrate 100, germanium tin silicon layer 102 and half
Conductor layer 103 includes first area I, the second area II and third region III being arranged successively；The half of the second area II
103 surface of conductor layer forms several discrete mask layers 104.
In the present embodiment, the material of the substrate 100 is silicon.Using chemical vapor deposition, physical vapour deposition (PVD) or atom
Layer depositing operation forms the germanium tin silicon layer 102.The forbidden bandwidth (bandgap) of 102 material of germanium tin silicon layer is wider than the forbidden band of germanium
The forbidden bandwidth of degree and silicon is big, forms germanium tin silicon layer 102 on 100 surface of substrate, advantageously reduces the parasitism in substrate 100
Leakage current.
The germanium tin silicon layer 102 is formed using epitaxy technique in the present embodiment, in the germanium tin silicon layer 102, the atom of germanium
Percentage is 50% to 70%, and the atomic percent of tin is 5% to 10%.Since the lattice constant of silicon and the lattice of germanium tin silicon are normal
Difference is larger between number, if directly forming germanium tin silicon layer 102, substrate 100 and 102 interface of germanium tin silicon layer on 100 surface of substrate
Place causes the adhesiveness between germanium tin silicon layer 102 and substrate 100 very poor, and in substrate 100 for more dislocation defects
Surface formed germanium tin silicon layer 102 it is second-rate.The present embodiment forms germanium tin silicon layer 102 on 100 surface of substrate thus
Before, buffering germanium layer 101 is formed on 100 surface of substrate, since the lattice constant of germanium is located at the lattice constant and germanium tin silicon of silicon
Between lattice constant, lattice between layers is prevented to be mutated serious adherency between raising substrate 100 and germanium tin silicon layer 102
Property, while improving the quality of the germanium tin silicon layer 102 of formation.The buffering germanium layer 101 is formed using epitaxy technique.
Since the band gap of germanium tin silicon layer 102 is larger, for example, atomic percent silicon is 32%, tin atom in germanium tin silicon layer 102
When percentage is 8%, the band gap of germanium tin silicon layer 102 is 0.87ev, is conducive to the parasitic leakage current for reducing fin field effect pipe.
The material of the semiconductor layer 103 is germanium or tin germanium；The semiconductor layer 103 of subsequent etching second area II is to form
The fin of fin field effect pipe；It is subsequent to be doped in the semiconductor layer 103 of first area I and third region I to be formed and be mixed
Miscellaneous area, the doped region are source doping region or drain doping region.
When the fin field effect pipe of formation is NMOS device, the material of the semiconductor layer 103 is germanium, is advantageous in that:
For NMOS device, the carrier of channel region is electronics, and electronics has biggish mobility in germanium, is conducive to improve
The carrier mobility of NMOS device.When the fin field effect pipe of formation is PMOS device, the material of the semiconductor layer 103 is
Tin germanium, is advantageous in that: for PMOS device, the carrier of channel region is hole, and hole has biggish in tin germanium
Mobility is conducive to the carrier mobility for improving PMOS device.
The present embodiment makees example as cmos device using the fin field effect pipe formed, and the substrate 100 includes NMOS area
IV and PMOS area V, and the orientation between NMOS area IV and PMOS area V and first area I, second area II and the
Orientation between three region III is mutually perpendicular to, and wherein the material of the semiconductor layer 103a of NMOS area IV is germanium, the area PMOS
The material of the semiconductor layer 103b of domain V is tin germanium.
The semiconductor layer 103b of PMOS area V is located at 102 surface of germanium tin silicon layer, since the material of semiconductor layer 103b is tin
Germanium, the lattice constant of semiconductor layer 103b material is greater than the lattice constant of 102 material of germanium tin silicon layer, so that in germanium tin silicon layer 102
There is compression (compressive strain) in the semiconductor layer 103b that surface is formed, it is subsequent in etching semiconductor layer 103b
There is compression after forming the fin of PMOS device, in the fin and compression enhances, to improve the sky of PMOS device
Cave mobility.
If the atomic percent of tin is too low in the material of semiconductor layer 103b, subsequent PMOS area V-arrangement at channel region
Interior hole mobility is still lower；If tin atom percentage is excessively high in the material of semiconductor layer 103b, semiconductor layer 103b's
It is second-rate, can to subsequent PMOS area V-arrangement at channel region in hole mobility cause adverse effect.For this purpose, the present embodiment
Semiconductor layer 103b in, tin account for tin germanium atomic percent be 2% to 10%.
The semiconductor layer 103 is formed using epitaxy technique in the present embodiment, specifically, in the germanium tin silicon of NMOS area IV
102 surface of layer form semiconductor layer 103a, form semiconductor layer 103b on 102 surface of germanium tin silicon layer of PMOS area V.
The mask layer 104 is used to define the positions and dimensions for the fin being subsequently formed, the row between the mask layer 104
The orientation of column direction and first area I, second area II and third region III is mutually perpendicular to.In order to reduce mask layer 104
Formation process difficulty, mask layer 104 described in the present embodiment remove positioned at second area II 103 surface of part of semiconductor layer
Outside, 103 surface of part of semiconductor layer of first area I and third region III are also located at.The material of the mask layer 104 is oxygen
SiClx, silicon nitride or Other substrate materials；Subsequent with the mask layer 104 is exposure mask, etching semiconductor layer 103 and segment thickness
Germanium tin silicon layer 102, therefore it is required that between the mask layer 104 and semiconductor layer 103 and the material of germanium tin silicon layer 102 have it is good
Good Etch selectivity.The mask layer 104 is single layer structure or laminated construction, and the present embodiment is single with the mask layer 104
Do exemplary illustrated for layer structure, the material of the mask layer 104 is silicon nitride.
Please continue to refer to Fig. 1 and Fig. 2, on 104 surface of 103 surface of semiconductor layer and mask layer of the second area II
Form pseudo- grid 105.
The puppet grid 105 define the position for the gate structure being subsequently formed.Semiconductor of the extended meeting in pseudo- 105 two sides of grid afterwards
103 surface of layer and 104 surface of mask layer form dielectric layer, and then the etching removal pseudo- grid 105 are to expose second area
104 surface of 103 surface of semiconductor layer and mask layer of II；It is required that the technique that the etching removes pseudo- grid 105 will not be to medium
Layer causes etching injury, therefore has good Etch selectivity between pseudo- grid 105 and the material of dielectric layer.Common dielectric layer
Material be silica, silicon nitride or silicon oxynitride, thus the material of puppet grid described in the present embodiment 105 be amorphous carbon
(Amorphous Carbon).The material of pseudo- grid 105 can also be siliceous antireflection material.
The processing step that the pseudo- grid 105 are formed in a specific embodiment includes: using spin coating process, and formation is covered
It is placed on the pseudo- grid film on 104 surface of semiconductor layer 103 and mask layer；Patterned photoresist is formed in the pseudo- grid film surface
Layer, the patterned photoresist layer expose the pseudo- grid film positioned at first area I and third region III；With described graphical
Photoresist layer be exposure mask, etching removal first area I and third region III pseudo- grid film, in the semiconductor of second area II
103 surface of layer and 104 surface of mask layer form pseudo- grid 105.
After forming the pseudo- grid 105, further comprises the steps of: and form the first side wall in pseudo- 105 sidewall surfaces of grid
106.103 surface of semiconductor layer, the top surface on 104 surface of mask layer and pseudo- grid 105 and side are covered in specifically, being formed
The side wall film of wall surface；Using non-mask etching technique, it is etched back to the side wall film, formation is covered in pseudo- 105 sidewall surfaces of grid
The first side wall 106.
The material of first side wall 106 described in the present embodiment is silicon nitride.Before forming first side wall 106, also
Can semiconductor layer 103 to first area I and third region III and germanium tin silicon layer 102 carry out lightly doped district, in first area
Lightly doped district is formed in the semiconductor layer 103 and germanium tin silicon layer 102 of I and third region III.Forming first side wall 106
Before, it further comprises the steps of: and weight is carried out to the semiconductor layer 103 and germanium tin silicon layer 102 of the first area I and third region III
Doping, forms heavily doped region in the semiconductor layer 103 and germanium tin silicon layer 102 of the first area I and third region III.
Specifically, in NMOS area IV first area I and third region III carry out N-doped zone, the N-type mixes
Miscellaneous Doped ions are P, As or Sb, with the semiconductor layer 103a of first area I and third region III in NMOS area and
N-doped zone is formed in germanium tin silicon layer 102；To in PMOS area V first area I and third region III carry out p-type doping,
The Doped ions of p-type doping are B, Ga or In, in PMOS area first area I and third region III partly lead
P-doped zone is formed in body layer 103b and germanium tin silicon layer 102.
Doped region described in the present embodiment includes lightly doped district and heavily doped region.In other embodiments, can also only exist
Heavily doped region is formed in the semiconductor layer and germanium tin silicon layer in first area and third region.
Referring to FIG. 3, Fig. 3 and Fig. 2 is the schematic diagram of the section structure in the same direction, in the first area I and third
103 surface of semiconductor layer of region III and 104 surface of mask layer form dielectric layer 107,107 top of dielectric layer and puppet
It is flushed at the top of grid 105.
The material of the dielectric layer 107 is silica, silicon nitride or silicon oxynitride, and dielectric layer 107 and mask layer 104
There is Etch selectivity between material.In the present embodiment, the material of the mask layer 104 is silicon nitride, the material of dielectric layer 107
For silica or silicon oxynitride.When the material of mask layer is silica in other embodiments, the material of dielectric layer can be nitrogen
SiClx or silicon oxynitride.
The dielectric layer 107 is located at the doped region surface of first area I and third area III, prevents subsequent etching technics
Etching injury is caused to the doped region surface, so that doped region surface has good pattern；Also, it is subsequent to be removed in etching
After pseudo- grid 105,103 surface of semiconductor layer and 104 surface of mask layer of the second area II between adjacent dielectric 107 is sudden and violent
Expose, to carry out being subsequently formed the processing step of fin and gate structure.
It in other embodiments, can also be after forming dielectric layer, to the semiconductor layer of first area and third region
It is doped with germanium tin silicon layer, to form doped region.
Referring to FIG. 4, Fig. 4 and Fig. 3 is the schematic diagram of the section structure in the same direction, 105 (such as Fig. 3 of the pseudo- grid is removed
It is shown), expose 104 surface of 103 surface of semiconductor layer and mask layer of second area II.
The pseudo- grid 105 are removed, are prepared to form fin；And the semiconductor layer of first area I and third region III
103 are covered by dielectric layer 107, to prevent from causing etching injury to doped region in subsequent etching technics.In the present embodiment,
The material of the puppet grid 105 is amorphous carbon, using one or both of cineration technics or wet-etching technology, described in removal
Pseudo- grid 105.
Fig. 5 to Fig. 7 is please referred to, Fig. 5 is top view, and Fig. 6 is the schematic diagram of the section structure of the Fig. 5 along the direction AA1, Fig. 7 Fig. 5
For the schematic diagram of the section structure in the direction BB1, the direction AA1 is parallel to each other with the direction BB1, with the mask layer of the second area II
104 be exposure mask, the semiconductor layer 103 of the second area II and the germanium tin silicon layer 102 of segment thickness is etched, described second
Several discrete fins are formed in region II substrate 100.
The fin is formed using dry etch process, and the bottom of fin is located at the germanium tin silicon layer 102 of second area II
It is interior.The fin includes first part's fin 118 and the second part fin 128 positioned at 118 surface of first part's fin,
In, first part's fin 118 is identical as germanium tin 102 materials of silicon layer, second part fin 128 and 103 material of semiconductor layer
It is identical, specifically, the material positioned at the second part fin 128 of PMOS area V is identical as semiconductor layer 103b material, it is located at
The material of the second part fin 128 of NMOS area IV is identical as semiconductor layer 103a material.
Arrangement side between orientation between adjacent fin and first area I, second area II and third region III
To being mutually perpendicular to.Angle between 100 surface of side wall and substrate of the fin is 75 ° to 90 °, i.e., the top dimension of fin with
Less than or equal to the bottom size of fin.
For PMOS area V, fin is shape after the germanium tin silicon layer 102 of etching semiconductor layer 103b and segment thickness
At, before etching forms fin, there is compression inside semiconductor layer 103b, after forming the fin, due to
The germanium tin silicon layer 102 of the segment thickness of PMOS area V is etched removal, therefore the compression having inside fin is enhanced,
To be conducive to further increase the hole mobility of PMOS device.For NMOS area IV, second part fin 128
Material is germanium, and the part channel region material of NMOS device is germanium thus, and the electron mobility in the channel region of NMOS device is larger.
Due to being limited by etching technics, so that the fin sidewall surfaces formed have certain line width roughness
(LWR, Line Width Roughness), the present embodiment further comprises the steps of: after forming fin to the fin side thus
Wall surface carries out reparation etching processing, to reduce the line width roughness of fin sidewall surfaces.
Referring to FIG. 8, Fig. 8 and Fig. 7 is the schematic diagram of the section structure in the same direction, semiconductor layer 103 after etching
And 102 sidewall surfaces of germanium tin silicon layer form the second side wall 109.
The side wall of second side wall 109 and the first side wall 106 as the gate structure sidewall surface being subsequently formed.It is described
The material of second side wall 109 is silica, silicon nitride, silicon oxynitride or carbon dope silicon nitride, and second side wall 109 is single layer knot
Structure or laminated construction.The present embodiment does exemplary illustrated so that the material of second side wall 109 is silicon nitride as an example.The present embodiment
In, in order to guarantee that fin has biggish contact area, after forming the second side wall 109, fin with the gate structure being subsequently formed
The sidewall surfaces in portion are not covered by the second side wall 109, i.e., the sidewall surfaces of the described fin are exposed.
Second side wall 109 described in the present embodiment is only located at 103 side wall of germanium tin silicon layer 102 and semiconductor layer after etching
Surface, the second side wall can also be covered in part the first side wall sidewall surfaces in other embodiments.
After forming second side wall 109, etching removes the mask layer 104 (as shown in Figures 5 and 6).This reality
It applies example and the mask layer 104 is removed using wet-etching technology etching, the material of the mask layer 104 is silicon nitride, and wet process is carved
The etch liquids of etching technique are phosphoric acid solution.
Fig. 9 and Figure 11 is please referred to, Fig. 9 is top view, and Figure 10 is the schematic diagram of the section structure of the Fig. 9 along the direction AA1, Tu11Wei
Fig. 9 is developed across the gate structure of the fin along the schematic diagram of the section structure in the direction BB1, and the gate structure covers fin
The top in portion and side wall.
The present embodiment by taking the fin field effect pipe that is formed is cmos device as an example, the gate structure of formation include: across
The second grid structure of the first grid structure 111 of the fin of NMOS area IV and the fin 108 across PMOS area V
112,111 top surface of first grid structure is flushed with 107 top surface of dielectric layer, and the second grid structure 112 is pushed up
Portion surface is flushed with 107 top surface of dielectric layer.
The first grid structure 111 include: cover NMOS area IV fin at the top of and side wall the first gate dielectric layer,
And positioned at first grid dielectric layer surface and the first grid of the full NMOS area IV groove of filling.The material of first gate dielectric layer
Material is silica, silicon nitride or high K medium material；The material of the first grid be polysilicon, Al, W, Cu, Ni, Ag, Au,
One of TiN, TaN, Ti or Ta or combination.The first function can also be formed between first gate dielectric layer and first grid
Function layer, first work-function layer are N-type workfunction layer, and the material of first work-function layer includes TixAl1-x(0<x<
1), one of Ti, Al, TaAl or a variety of.
The second grid structure 112 include: cover the 5th region V fin at the top of and side wall the second gate dielectric layer,
And positioned at second gate dielectric layer surface and the second grid of the full 5th region V groove of filling.The material of second gate dielectric layer
Material is silica, silicon nitride or high K medium material；The material of the second grid be polysilicon, Al, W, Cu, Ni, Ag, Au,
One of TiN, TaN, Ti or Ta or combination.The second function can also be formed between second gate dielectric layer and second grid
Function layer, second work-function layer are P-type workfunction layer, and the material of second work-function layer includes TixN1-x(0<x<1)、
One of TaC, MoN, TaN or a variety of.
The high K medium material include LaO, AlO, BaZrO, HfZrO, HfZrON, HfLaO, HfSiO, HfSiON,
LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr) TiO3(abbreviation BST), Al2O3、Si3N4, one of SiON or a variety of.
The dielectric layer 107 that etching is located at first area I and third region III is further comprised the steps of:, exposes doping to be formed
The conductive through hole on area surface；The conductive plunger for filling the full conductive through hole is formed, the conductive plunger is electrically connected with doped region.
Etching technics is not undergone by the semiconductor layer 103 of first area I in this present embodiment and third region III, so that
103 surface of semiconductor layer of first area I and third region III has good pattern, i.e. doped region surface has good pattern,
So that the etching stopping position for forming conductive through hole is easy to control, and avoid reporting to the leadship after accomplishing a task as doped region surface topography and caused by
Doped region is etched, and improves the quality of the conductive plunger of formation, to further increase the electric property of fin field effect pipe.
Correspondingly, the present embodiment also provides a kind of fin field effect pipe, as shown in Figures 9 to 11, Fig. 9 is top view, figure
10 be Fig. 9 along the schematic diagram of the section structure in the direction AA1, and Figure 11 is the schematic diagram of the section structure of the Fig. 9 along the direction BB1, fin field effect
Should pipe include:
Substrate 100, the substrate 100 include first area I, the second area II and third region III being arranged successively；Position
In the germanium tin silicon layer 102 on 100 surface the first area I and third region III substrate and positioned at 102 surface of germanium tin silicon layer
Semiconductor layer, and the lattice constant of 103 material of semiconductor layer be greater than 102 material of germanium tin silicon layer lattice constant；Positioned at described
The germanium tin silicon layer 102 on 200 surface of second area II substrate, and the thickness of the germanium tin silicon layer 102 of second area II is less than the firstth area
The thickness of the germanium tin silicon layer 102 of domain I and third region III；Positioned at the several discrete of 102 surface of second area germanium tin silicon layer
Fin, the fin includes first part's fin 118 and the second part fin positioned at 118 surface of first part's fin
128,118 material of first part's fin is identical as germanium tin 102 materials of silicon layer, 128 material of second part fin and semiconductor
103 material of layer are identical；Across the gate structure of the fin, and the gate structure covers top and the side wall of fin；It is located at
Doped region in first area I and the semiconductor layer in third region 103 and germanium tin silicon layer 102.
There is buffering germanium layer 101 between the substrate 100 and germanium tin silicon layer 102；The material of the semiconductor layer be germanium or
Tin germanium.
For the present embodiment by taking fin field effect pipe is cmos device as an example, substrate 100 includes PMOS area V and NMOS area
The material of the semiconductor layer 103b of IV, PMOS area V are tin germanium, and the material of the semiconductor layer of NMOS area IV is germanium.The area PMOS
The material of first part's fin 118 of domain V is identical as the material of germanium tin silicon layer 102, the material of second part fin 128 with partly lead
Body layer 103b material is identical；118 material of first part's fin of NMOS area IV is identical as germanium tin 102 materials of silicon layer, and second
Divide 128 material of fin identical as NMOS area IV semiconductor layer material.
In the germanium tin silicon layer 102, the atomic percent of germanium is 50% to 70%, the atomic percent of tin be 5% to
10%；When the material of the semiconductor layer is tin germanium, the atomic percent of tin is 2% to 10% in semiconductor layer.
The gate structure includes: across the first grid structure 111 of the fin of NMOS area IV and across the area PMOS
The second grid structure 112 of the fin 108 of domain V.
Further include: positioned at the dielectric layer 107 of the semiconductor layer surface of first area I and third region III, the dielectric layer
107 top with flushed at the top of first grid structure 111 and second grid structure 112；Positioned at first area I and third region III
Conductive through hole in dielectric layer 107；The conductive plunger of the full conductive through hole is filled, the conductive plunger is electrically connected with doped region
It connects.
Fin field effect pipe provided in this embodiment, had not only improved the carrier mobility in channel region, but also to adulterate
Area surface has good pattern, so that the fin field effect pipe structural behaviour provided is superior.
Further embodiment of this invention also provides a kind of forming method of fin field effect pipe, Figure 12 to Figure 18 be the present invention again
The structural schematic diagram for the fin field effect pipe forming process that one embodiment provides.
Figure 12 is please referred to, Figure 12 is top view, provides substrate 200, and the substrate 200 includes the first area being arranged successively
10, second area 20 and third region 30；Several discrete mask layers are formed on 200 surface of substrate of the second area 20
201。
The material of the substrate 200 is silicon, germanium, SiGe, arsenic SiClx or gallium indium, and the substrate 200 can also be exhausted
Silicon on edge body；The material of substrate 200 described in the present embodiment is silicon.The subsequent substrate in first area 10 and third region 30
Doped region is formed in 200, etches the substrate 200 of second area 20 to form several discrete fins.It is described to cover in the present embodiment
Film layer 201 is also located at 200 surface of part of substrate in first area 10 and third region 30.The material of the mask layer 201 is oxygen
SiClx, silicon nitride or Other substrate materials, the material of mask layer 201 described in the present embodiment are silicon nitride.
Fin field effect pipe to be formed is PMOS device, NMOS device or cmos device, and the present embodiment is with to be formed
Fin field effect pipe is that PMOS device makees example.
Figure 13 is please referred to, Figure 13 is the schematic diagram of the section structure on the basis of Figure 12 is along the direction CC1, in the second area
20 substrate 200 and 201 surface of mask layer form pseudo- grid 202；Substrate 200 in the first area 10 and third region 30
Surface and 201 surface of mask layer form dielectric layer 203, flush at the top of 203 top of dielectric layer and pseudo- grid 202.
The puppet grid 202 define the position of the first grid and second grid that are subsequently formed, the formation of the puppet grid 202
Method can refer to the forming method of the pseudo- grid 105 (as shown in Figure 2) of previous embodiment offer, and details are not described herein.The present embodiment
In, the material of the puppet grid 202 is amorphous carbon；After forming the pseudo- grid 202, in the sidewall surfaces of the pseudo- grid 202
Form the first side wall 204.
Before forming first side wall 204, can also the substrate 200 to first area 10 and third region 30 carry out
Lightly doped district forms lightly doped district in the substrate 200 in first area 10 and third region 30.Forming first side wall
After 204, can also substrate 200 to first area 10 and third region 30 carry out heavy doping, in first area 10 and third
Heavily doped region is formed in the substrate 200 in region 30.
Doped region described in the present embodiment includes that lightly doped district and heavily doped region in other embodiments can also be only
Heavily doped region is formed in the substrate in first area and third region.
The material of the dielectric layer 203 is silica, silicon nitride or silicon oxynitride.The material of mask layer 201 in the present embodiment
Material is silicon nitride, and the material of dielectric layer 203 is silica or silicon oxynitride.The dielectric layer 203 is located at first area 10 and
The doped region surface in three regions 30, prevents subsequent etching technics from causing etching injury to doped region surface.In other embodiments
In, the substrate of first area and third region can also be doped to form doped region after forming dielectric layer.
Figure 14 to Figure 16 is please referred to, Figure 14 is top view, and Figure 15 is the schematic diagram of the section structure of the Figure 14 along the direction DD1, DD1
Direction is parallel to each other with the direction CC1, and Figure 16 is the schematic diagram of the section structure of the Figure 14 along the direction EE1, and the direction EE1 and the direction CC1
It is mutually perpendicular to, removes the pseudo- grid 202 (such as Figure 13), expose 201 surface of substrate 200 and mask layer of second area 20；
Mask layer 201 with the second area 20 is exposure mask, and the substrate 200 of etched portions thickness is to form several discrete fins
205。
Using one or both of cineration technics or wet-etching technology, the pseudo- grid 202 are removed；Then dry method is used
Etching technics, the mask layer 201 with second area 20 are exposure mask, and the substrate 200 of etched portions thickness is several discrete to be formed
Fin 205.Orientation and first area 10, second area 20 between adjacent fin 205 and the row between third region 30
Column direction is mutually perpendicular to.
Please referring to Figure 17 and Figure 18, Figure 17 and Figure 15 is the schematic diagram of the section structure in the same direction, and Figure 18 is with Figure 16
The schematic diagram of the section structure in the same direction, formation are covered in 205 partial sidewall surface of fin and the remaining base of second area 20
The first grid 206 on 200 surface of bottom；It is developed across the second grid 207 of the fin 205, the second grid 207 is located at the
One grid, 206 surface and top and the side wall for covering fin 205.
After forming the fin 205, the mask layer 201 of the second area 20 is removed, exposes 205 top of fin
Surface.
Due to that when fin field effect pipe is in running order, will have carrier inside fin, particularly, close to substrate
Fin region in since positive charge is assembled will lead to the fin region with excess carriers, cause break-through to leak electricity
(punch through leakage current) problem is significant.For this purpose, by close to residual substrate 200 in the present embodiment
205 sidewall surfaces of fin and 200 surface of residual substrate formed first grid 206,206 capture portion of first grid
Carrier in fin discharges the excess carriers by the first grid 206, improves the fin close to residual substrate 200
205 region of portion is to the control ability of electric field, so that the electron density in the fin 205 of residual substrate 200 is reduced, to change
The break-through electrical leakage problems of kind fin field effect pipe.
In one embodiment, the material of the first grid 206 is polysilicon.In another embodiment, described first
The material of grid 206 is the polysilicon of p-type doping, and the Doped ions of p-type doping are B, Ga or In, the p-type doping
Doping concentration is 1E15atom/cm3To 5E20atom/cm3。
In other embodiments, the material of the first grid 206 can also be metal material, and the metal material plays
Effect play the role of with the polysilicon that p-type is adulterated suitable, the workfunction range of the metal material is 4.9ev to 5.9ev,
Such as 4.9ev, 5.1ev, 5.29ev, 5.5ev, 5.75ev or 5.9ev.Also, since depletion of polysilicon is not present in metal material
(poly-silicon depletion) problem, therefore can preferably inhibit in 205 region of fin of residual substrate 200
The aggregation of excess carriers reduces channel region carriers content, thus preferably inhibit the leakage current of fin field effect pipe
Problem.The metal material is W, WN, Ru, Mo or MoN.
It has been investigated that in the range of being higher than 200 top surface 10nm of residual substrate, all having in fin 205
The carrier of amount, for this purpose, the thickness of first grid 206 is greater than or equal to 10 nanometers in the present embodiment, to discharge the fin 205
Interior excess carriers inhibit the current leakage of fin field effect pipe；And the thickness of first grid 206 be also not easy it is blocked up, it is no
Then the thickness of second grid 207 will be relatively small, causes gate structure weaker to the control ability of channel region.For this purpose, this implementation
Example in first grid 206 with a thickness of 10 nanometers to 50 nanometers.
Before forming the first grid 206, the gate medium to be formed and be covered at the top of fin with side wall is further comprised the steps of:
Layer 208, the material of the gate dielectric layer 208 are silica, silicon nitride or high K medium material.Form the first grid 206
Processing step includes: to form the first grid film for being covered in the gate dielectric layer 208；It is etched back to the first grid film, is etched
Removal is located at the first grid of the first grid film on 205 top of fin and the segment thickness in residual substrate 200
Film, forms first grid 206, and 206 top surface of first grid is lower than 205 top surface of fin.
In embodiments of the present invention, injury-free for protection gate dielectric layer 208, after forming the gate dielectric layer 208
It is formed before first grid 205, cap rock 209 can also be formed on 208 surface of gate dielectric layer, the material of the cap rock 209 is TiN
Or TaN.The material of the second grid 207 is metal material, for example, Cu, Al, W, Ag, Au or Pt.The present embodiment is forming institute
Before stating first grid 206 and second grid 207,200 sidewall surfaces of substrate after etching form the second side wall 210.
The present embodiment discharges the excess carriers inside channel region by first grid 206, improves close close to fin 205
200 region of substrate is to the control ability of electric field, so that the electron density in the fin 205 of residual substrate 200 is reduced, thus
Improve the break-through current leakage of fin field effect pipe.
Correspondingly, the present embodiment also provides a kind of fin field effect pipe, as shown in FIG. 17 and 18, Figure 17 and Figure 18 are fin
The schematic diagram of the section structure of formula field-effect tube, and the profile direction of Figure 17 and Figure 18 is mutually perpendicular to, the fin field effect pipe packet
It includes:
Substrate 200, the substrate 200 include first area 10, second area 20 and the third region 30 being arranged successively,
And higher than 200 top of the substrate of second area 20 at the top of the substrate 200 in first area 10 and third region 30；Positioned at described second
Several discrete fins 205 on 200 surface of substrate in region 20, and orientation and first area between adjacent fin 205
10, the orientation between second area 20 and third region 30 is mutually perpendicular to；Positioned at the partial sidewall table of the fin 205
The first grid 206 on 200 surface of face and 20 substrate of second area；Across the second grid 207 of the fin 205, described
Two grids 207 are located at 206 surface of first grid and cover top and the side wall of fin 205；Positioned at first area 10 and third area
Doped region in the substrate 200 in domain 30.
Specifically, the material of the substrate 200 is silicon, germanium, SiGe, GaAs or gallium indium, the material of the substrate 200
Material can also be the silicon on insulator.In one embodiment, in the substrate 200 in first area 10 and third region 30
Doped region is N-doped zone, Doped ions P, As or Sb；In another embodiment, it is located at first area 10 and third region
Doped region in 30 substrate 200 is P-doped zone, Doped ions B, Ga or In.Positioned at first area 10 and third region
30 300 surface of substrate has dielectric layer 203.
Carrier in the 206 capture portion fin 205 of first grid discharges fin 205 close to the region of substrate 200
Interior excess carriers improve the control ability close to 205 region of fin of substrate 200 to electric field, to reduce close to substrate
Electron density in 200 fin 205, so as to improve the break-through leakage current of fin field effect pipe.
The material of the first grid 206 is the polysilicon or metal material of polysilicon, p-type doping.In one embodiment
In, the material of the first grid 206 is the polysilicon of p-type doping, and the Doped ions of the p-type doping are B, Ga or In, institute
The doping concentration for stating p-type doping is 1E15atom/cm3 to 5E20atom/cm3.In other embodiments, the first grid
206 material is metal material, and the workfunction range of the metal material is 4.9ev to 5.9ev, such as 4.9ev, 5.1ev,
5.29ev, 5.5ev, 5.75ev or 5.9ev.The metal material is W, WN, Ru, Mo or MoN.
The first grid 206 with a thickness of 10 nanometers to 50 nanometers.If the thickness of first grid 206 is excessively thin, it is higher than
Excess carriers in 205 region of fin of first grid 206 are difficult to be released, and still will cause biggish current leakage；If
The thickness of first grid 206 is blocked up, then the thickness of corresponding second grid 207 is excessively thin, causes control of the gate structure to fin 205
Ability is weaker.For this purpose, in the present embodiment first grid 206 with a thickness of 10 nanometers to 50 nanometers.
The sidewall surfaces of the substrate 200 have the second side wall 210, avoid between first grid 206 and doped region directly
Contact.The material of the second grid 207 is metal material, for example, Cu, Al, W, Ag, Au or Pt；The second grid 207
It is flushed at the top of top and dielectric layer 203；There is the first side wall 204 between the second grid 207 and dielectric layer 203.This implementation
In example, the top of the fin 205 and sidewall surfaces have gate dielectric layer 208；208 surface of gate dielectric layer has cap rock
209.Wherein, the material of gate dielectric layer 208 is silica, silicon nitride or high K medium material；The material of cap rock 209 be TiN or
TaN。
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (12)
1. a kind of forming method of fin field effect pipe characterized by comprising
Substrate is provided；
It forms the germanium tin silicon layer of covering substrate and covers the semiconductor layer of germanium tin silicon layer, and the lattice of semiconductor layer material is normal
Number is greater than the lattice constant of germanium tin silicon layer material, and the substrate, germanium tin silicon layer and semiconductor layer include first be arranged successively
Region, second area and third region；
The semiconductor layer of the second area and the germanium tin silicon layer of segment thickness are etched, forms several points in the second area
Vertical fin, the fin include first part's fin and the second part fin positioned at first part's fin portion surface, and first
Part fin material is identical as germanium tin silicon layer material, and second part fin material is identical as semiconductor layer material, and adjacent fin
Between orientation and first area, second area and third region between orientation be mutually perpendicular to；
It is developed across the gate structure of the fin, and the top of gate structure covering fin and side wall；
Doped region is formed in the semiconductor layer and germanium tin silicon layer in the first area and third region.
2. the forming method of fin field effect pipe as described in claim 1, which is characterized in that the material of the substrate is silicon；Institute
The material for stating semiconductor layer is germanium or tin germanium.
3. the forming method of fin field effect pipe as claimed in claim 2, which is characterized in that the fin field effect pipe of formation is
When NMOS device, the material of the semiconductor layer is germanium；When the fin field effect pipe of formation is PMOS device, the semiconductor layer
Material be tin germanium.
4. the forming method of fin field effect pipe as claimed in claim 2, which is characterized in that in the germanium tin silicon for forming covering substrate
Before layer, buffering germanium layer is formed in the substrate surface；Buffering germanium layer, germanium tin silicon layer and semiconductor are formed using epitaxy technique
Layer.
5. the forming method of fin field effect pipe as claimed in claim 2, which is characterized in that in the germanium tin silicon layer, the original of germanium
Sub- percentage is 50% to 70%, and the atomic percent of tin is 5% to 10%；When the material of the semiconductor layer is tin germanium, half
The atomic percent of tin is 2% to 10% in conductor layer.
6. the forming method of fin field effect pipe as described in claim 1, which is characterized in that form several discrete fins
Processing step include: to form several discrete mask layers in the semiconductor layer surface of the second area；With secondth area
The mask layer in domain is exposure mask, etches the germanium tin silicon layer of the semiconductor layer and segment thickness to form several discrete fins.
7. the forming method of fin field effect pipe as claimed in claim 6, which is characterized in that several discrete mask layers are also
Semiconductor layer surface positioned at first area and third region；In the semiconductor layer surface and mask layer table of the second area
Face forms pseudo- grid；Dielectric layer, institute are formed in the semiconductor layer surface and exposure mask layer surface in the first area and third region
It states and is flushed at the top of dielectric layer at the top of pseudo- grid；The pseudo- grid are removed, the semiconductor layer surface and exposure mask of second area are exposed
Layer surface.
8. the forming method of fin field effect pipe as claimed in claim 7, which is characterized in that the material of the puppet grid is amorphous
Carbon or siliceous antireflection material；After forming the pseudo- grid, further comprises the steps of: and form first in the pseudo- grid sidewall surfaces
Side wall；After forming the fin, semiconductor layer sidewall surfaces after etching and germanium tin silicon layer side wall are further comprised the steps of:
Surface forms the second side wall.
9. a kind of fin field effect pipe characterized by comprising
Substrate, the substrate include the first area being arranged successively, second area and third region；
Positioned at the germanium tin silicon layer on the first area and third substrate areas surface and positioned at the semiconductor of germanium tin silicon surface
Layer, and the lattice constant of semiconductor layer material is greater than the lattice constant of germanium tin silicon layer material；
Positioned at the germanium tin silicon layer of the second area substrate surface, and the thickness of the germanium tin silicon layer of second area is less than first area
With the thickness of the germanium tin silicon layer in third region；
Positioned at several discrete fins of the second area germanium tin silicon surface, the fin includes first part and is located at
The second part fin of first part's fin portion surface, first part's fin material is identical as germanium tin silicon layer material, second part fin
Portion's material is identical as semiconductor layer material；
Across the gate structure of the fin, and the gate structure covers top and the side wall of fin；
Doped region in the semiconductor layer and germanium tin silicon layer in first area and third region.
10. fin field effect pipe as claimed in claim 9, which is characterized in that have buffering between the substrate and germanium tin silicon layer
Germanium layer；The material of the semiconductor layer is germanium or tin germanium.
11. fin field effect pipe as claimed in claim 10, which is characterized in that in the germanium tin silicon layer, the atomic percent of germanium
It is 50% to 70%, the atomic percent of tin is 5% to 10%；When the material of the semiconductor layer is tin germanium, in semiconductor layer
The atomic percent of tin is 2% to 10%.
12. fin field effect pipe as claimed in claim 9, which is characterized in that further include: positioned at first area and third region
The dielectric layer of semiconductor layer surface, the dielectric layer top and gate structure top flush.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102820230A (en) * | 2011-06-10 | 2012-12-12 | 国际商业机器公司 | Fin-last replacement metal gate FinFET |
| US20130341639A1 (en) * | 2012-06-26 | 2013-12-26 | Globalfoundries Singapore Pte. Ltd. | Deep depleted channel mosfet with minimized dopant fluctuation and diffusion levels |
| CN103515420A (en) * | 2012-06-26 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and formation method thereof |
| CN103762242A (en) * | 2014-02-19 | 2014-04-30 | 重庆大学 | Compressive strain GeSn p-channel MOSFET |
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| US7960234B2 (en) * | 2007-03-22 | 2011-06-14 | Texas Instruments Incorporated | Multiple-gate MOSFET device and associated manufacturing methods |
| US8367528B2 (en) * | 2009-11-17 | 2013-02-05 | Asm America, Inc. | Cyclical epitaxial deposition and etch |
| US20130183814A1 (en) * | 2012-01-13 | 2013-07-18 | Applied Materials, Inc. | Method of depositing a silicon germanium tin layer on a substrate |
| CN103311302B (en) * | 2013-05-09 | 2016-01-20 | 清华大学 | A kind of hybrid three-dimensional transistor and forming method thereof |
| CN103839829A (en) * | 2014-02-25 | 2014-06-04 | 清华大学 | Fin type field effect transistor with SiGeSn channel and forming method thereof |
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|---|---|---|---|---|
| CN102820230A (en) * | 2011-06-10 | 2012-12-12 | 国际商业机器公司 | Fin-last replacement metal gate FinFET |
| US20130341639A1 (en) * | 2012-06-26 | 2013-12-26 | Globalfoundries Singapore Pte. Ltd. | Deep depleted channel mosfet with minimized dopant fluctuation and diffusion levels |
| CN103515420A (en) * | 2012-06-26 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and formation method thereof |
| CN103762242A (en) * | 2014-02-19 | 2014-04-30 | 重庆大学 | Compressive strain GeSn p-channel MOSFET |
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