CN109004823B - Self-adaptive fixed on-time generation circuit based on CMOS (complementary metal oxide semiconductor) process - Google Patents
Self-adaptive fixed on-time generation circuit based on CMOS (complementary metal oxide semiconductor) process Download PDFInfo
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- CN109004823B CN109004823B CN201810937820.1A CN201810937820A CN109004823B CN 109004823 B CN109004823 B CN 109004823B CN 201810937820 A CN201810937820 A CN 201810937820A CN 109004823 B CN109004823 B CN 109004823B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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Abstract
A self-adaptive fixed on-time generating circuit based on a CMOS (complementary metal oxide semiconductor) process belongs to the technical field of power electronics. The input end of the input voltage acquisition unit is used as the first input end of the self-adaptive fixed conduction time generation circuit, and the output end of the input voltage acquisition unit outputs a charging current which is in direct proportion to a signal of the first input end of the input voltage acquisition unit and is connected to the input end of the charging timing unit; the control end of the charging timing unit is connected with the control signal, and the output end of the charging timing unit outputs a charging voltage which is controlled by the control signal and is generated according to the charging current; the positive input end of the comparator is connected with the charging voltage, the negative input end of the comparator is used as the second input end of the self-adaptive fixed conduction time generation circuit, and the output end of the comparator is used as the output end of the self-adaptive fixed conduction time generation circuit. The on-time generated by the invention can be adaptively adjusted along with the input and output voltage of the applied circuit, and the invention can be suitable for some special environments or processes because no BJT device is used.
Description
Technical Field
The invention belongs to the technical field of power electronics, and relates to a self-adaptive fixed conduction time generation circuit based on a CMOS (complementary metal oxide semiconductor) process, which is mainly applied to the field of DC-DC (direct current-direct current) switch converters.
Background
Among four basic circuits of the DC-DC switching converter, the Buck converter has the characteristics that the output voltage is less than the input voltage and the direct current is not isolated, and is also called as a Buck converter, so that the Buck converter is widely applied to mobile portable equipment and has a huge application market. The fixed On Time (COT) Buck converter is widely used due to higher efficiency and better load step characteristics under light load, but due to the fixed On Time, some disadvantages are brought, such as unfixed frequency and further improved load step characteristics. Therefore, an adaptive fixed-on-time Buck converter is introduced, and the adaptive on-time generating circuit becomes the core and key point of design.
The traditional self-adaptive on-time generating circuit realizes the multiplication and division relation of current by depending on the addition and subtraction relation of the base electrode-emitter BE junction voltage of a BJT, thereby realizing the relation that the on-time is in direct proportion to the output voltage of a Buck converter and in inverse proportion to the input voltage of the Buck converter. However, the conventional adaptive on-time generation circuit cannot be applied to some special application environments or some special processes due to the use of BJT devices.
Disclosure of Invention
Aiming at the problem that the traditional self-adaptive conduction time generating circuit cannot be applied to some special application environments due to the fact that BJT devices are used, the invention provides the self-adaptive conduction time generating circuit, and the input voltage of the application circuit is collected by using an operational amplifier clamping method, so that the conduction time T generated by the self-adaptive conduction time generating circuit is enabled to beONThe invention is in direct proportion to the output voltage of the applied circuit and in inverse proportion to the input voltage of the applied circuit, and can be used in some special environments because the invention can use pure CMOS technology.
The technical scheme of the invention is as follows:
a self-adaptive fixed on-time generation circuit based on a CMOS (complementary metal oxide semiconductor) process comprises an input voltage acquisition unit, a charging timing unit and a comparator, wherein the input end of the input voltage acquisition unit is used as the first input end of the self-adaptive fixed on-time generation circuit, and the output end of the input voltage acquisition unit outputs a charging current IINThe input end of the charging timing unit is connected; the control end of the charging timing unit is connected with a control signal CON, and the output end of the charging timing unit is controlled by the control signal CON and is based on the charging current IINGenerated charging voltage VCAP(ii) a The positive phase input end of the comparator is connected with the charging voltage VCAPThe inverting input end of the adaptive fixed on-time generating circuit is used as the second input end of the adaptive fixed on-time generating circuit, and the output end of the adaptive fixed on-time generating circuit is used as the output end of the adaptive fixed on-time generating circuit;
the input voltage acquisition unit comprises an operational amplifier, a first resistor R1, a first capacitor C1, a fifth NMOS transistor N5, a sixth PMOS transistor P6 and a seventh PMOS transistor P7,
the first input end of the operational amplifier is used as the input end of the input voltage acquisition unit, the second input end of the operational amplifier is connected with the source electrode of the fifth NMOS tube N5 and is grounded GND after passing through the first resistor R1, and the output end of the operational amplifier is connected with the grid electrode of the fifth NMOS tube N5 and is grounded GND after passing through the first capacitor C1;
the gate of the seventh PMOS transistor P7 is connected to the gate and the drain of the sixth PMOS transistor P6 and the drain of the fifth NMOS transistor N5, the source thereof is connected to the source of the sixth PMOS transistor P6 and to the supply voltage VDD, and the drain thereof outputs the charging current IIN。
Specifically, the operational amplifier in the input voltage collecting unit comprises a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4 and a fifth PMOS transistor P5,
the grid electrode of the fifth PMOS pipe P5 is used as the first input end of the operational amplifier, the source electrode of the fifth PMOS pipe P5 is connected with the source electrode of the fourth PMOS pipe P4 and the drain electrode of the second PMOS pipe P2, and the drain electrode of the fifth PMOS pipe P5 is connected with the grid electrode and the drain electrode of the third NMOS pipe N3 and the grid electrode of the fourth NMOS pipe N4;
the grid electrode of the fourth PMOS pipe P4 is used as the second input end of the operational amplifier, and the drain electrode of the fourth PMOS pipe P4 is connected with the grid electrode of the first NMOS pipe N1 and the grid electrode and the drain electrode of the second NMOS pipe N2;
the grid electrode of the second PMOS pipe P2 is connected with a bias voltage VB1The sources of the PMOS transistors are connected with the sources of the first PMOS transistor P1 and the third PMOS transistor P3 and connected with the power supply voltage VDD;
the grid electrode of the third PMOS pipe P3 is connected with the grid electrode and the drain electrode of the first PMOS pipe P1 and the drain electrode of the first NMOS pipe N1, and the drain electrode of the third PMOS pipe P3 is connected with the drain electrode of the fourth NMOS pipe N4 and serves as the output end of the operational amplifier;
the sources of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3 and the fourth NMOS transistor N4 are grounded GND.
Specifically, the charging timing unit includes a second capacitor C2, a sixth NMOS transistor N6, an eighth PMOS transistor P8, and a first inverter INV1,
a source electrode of the eighth PMOS transistor P8 is used as an input end of the charging timing unit, a gate electrode thereof is connected to the gate electrode of the sixth NMOS transistor N6 and the output end of the first inverter INV1, and a drain electrode thereof is connected to the drain electrode of the sixth NMOS transistor N6 and is used as the output end of the charging timing unit; the second capacitor C2 is connected between the output end of the charging timing unit and the ground GND; an input end of the first inverter INV1 is used as a control end of the charging timing unit; the source of the sixth NMOS transistor N6 is grounded.
Specifically, when the adaptive fixed on-time generating circuit is used in a DC-DC switching converter, the input voltage of the DC-DC switching converter is connected to the first input terminal of the adaptive fixed on-time generating circuit, and the output voltage of the DC-DC switching converter is connected to the second input terminal of the adaptive fixed on-time generating circuit.
The working process of the invention is as follows:
the input voltage acquisition unit regulates and controls a fifth NMOS transistor N5 through an operational amplifier therein, so that the voltage on the first resistor R1 is clamped, and a charging current I which is in direct proportion to a signal of a first input end of the self-adaptive fixed on-time generation circuit is obtainedIN(ii) a The charging timing unit utilizes the charging current I generated by the input voltage acquisition unit under the control of the control signal CONINCharging the second capacitor C2 to obtain a charging voltage VCAP(ii) a Control signal CON controls charging voltage VCAPClearing when each period comes; the comparator compares the charging voltage V generated by the charging timing unitCAPComparing with the signal of the second input terminal of the adaptive fixed on-time generation circuit when the charging voltage V isCAPWhen the voltage value of the signal of the second input end of the self-adaptive fixed on-time generation circuit rises, the output signal of the comparator is the generated on-time TONIs reversed to produce a conduction time T proportional to the signal at the second input of the adaptive fixed conduction time generation circuit and inversely proportional to the signal at the first input of the adaptive fixed conduction time generation circuitON。
Wherein when the invention is used for a DC-DC switching converter, the charging current I generated by the input voltage acquisition unitINProportional to DC-DC switchInput voltage V of turn-off converterINUsing the charging current IINThe resulting charging voltage VCAPWith the output voltage V of the DC-DC switching converterOUTComparing, when the charging voltage V isCAPUp to the output voltage V of the DC-DC switching converterOUTTime, output signal TONAnd (6) turning over.
The invention has the beneficial effects that: the invention can be applied to a DC-DC switch converter circuit, is used for generating the self-adaptive conduction time which is adjusted along with the input voltage and the output voltage of an application circuit of the DC-DC switch converter circuit, quickens the transient response of the application circuit of the DC-DC switch converter circuit and provides a frequency coarse adjustment for the application circuit of the DC-DC switch converter circuit, and can be applied to certain special environments or processes because no BJT device is used.
Drawings
Fig. 1 is a schematic diagram of an overall structure of a self-adaptive fixed on-time generation circuit based on a CMOS process according to the present invention.
Fig. 2 is a schematic diagram of a circuit implementation structure of the input voltage acquisition unit of the present invention.
Fig. 3 is a schematic diagram of a circuit implementation structure of the charging timing unit according to the present invention.
Fig. 4 is a waveform diagram illustrating an operation of an adaptive fixed on-time generating circuit according to the present invention.
Detailed Description
The present invention will be described in detail below with reference to examples and the accompanying drawings.
Fig. 1 is a schematic diagram of a structure of a self-adaptive fixed on-time generation circuit based on a CMOS process according to the present invention, which includes an input voltage acquisition unit, a charging timing unit and a comparator, wherein an input terminal of the input voltage acquisition unit is used as a first input terminal of the self-adaptive fixed on-time generation circuit, and an output terminal thereof outputs a charging current IINThe input end of the charging timing unit is connected; the control end of the charging timing unit is connected with a control signal CON, and the output end of the charging timing unit is controlled by the control signal CON and is based on the charging current IINGenerated charging voltage VCAP(ii) a The positive input end of the comparator is connected with the chargeVoltage VCAPAnd the negative input end of the self-adaptive fixed on-time generating circuit is used as the second input end of the self-adaptive fixed on-time generating circuit, and the output end of the self-adaptive fixed on-time generating circuit is used as the output end of the self-adaptive fixed on-time generating circuit.
As shown in fig. 2, the input voltage collecting unit includes an operational amplifier, a first resistor R1, a first capacitor C1, a fifth NMOS transistor N5, a sixth PMOS transistor P6, and a seventh PMOS transistor P7, a first input terminal of the operational amplifier is used as an input terminal of the input voltage collecting unit, a second input terminal of the operational amplifier is connected to a source of the fifth NMOS transistor N5 and grounded to GND through the first resistor R1, and an output terminal of the operational amplifier is connected to a gate of the fifth NMOS transistor N5 and grounded to GND through the first capacitor C1; the gate of the seventh PMOS transistor P7 is connected to the gate and the drain of the sixth PMOS transistor P6 and the drain of the fifth NMOS transistor N5, the source thereof is connected to the source of the sixth PMOS transistor P6 and to the supply voltage VDD, and the drain thereof outputs the charging current IIN。
As shown in fig. 2, a circuit implementation form of an operational amplifier in an input voltage acquisition unit is further provided, and includes a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, and a fifth PMOS transistor P5, where a gate of the fifth PMOS transistor P5 is used as a first input terminal of the operational amplifier, a source of the fifth PMOS transistor P5 is connected to a source of the fourth PMOS transistor P4 and a drain of the second PMOS transistor P2, and a drain of the fifth PMOS transistor P5 is connected to a gate and a drain of the third NMOS transistor N3 and a gate of the fourth NMOS transistor N4; the grid electrode of the fourth PMOS pipe P4 is used as the second input end of the operational amplifier, and the drain electrode thereof is connected with the grid electrode of the first NMOS pipe N1 and the grid electrode and the drain electrode of the second NMOS pipe N2; the grid electrode of the second PMOS pipe P2 is connected with a bias voltage VB1The sources of the PMOS transistors are connected with the sources of the first PMOS transistor P1 and the third PMOS transistor P3 and connected with the power supply voltage VDD; the grid electrode of the third PMOS pipe P3 is connected with the grid electrode and the drain electrode of the first PMOS pipe P1 and the drain electrode of the first NMOS pipe N1, and the drain electrode of the third PMOS pipe P3 is connected with the drain electrode of the fourth NMOS pipe N4 and is used as the output end of the operational amplifier; the sources of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3 and the fourth NMOS transistor N4 are grounded GND.
A circuit implementation form of the charging timing unit is shown in fig. 3, which includes a second capacitor C2, a sixth NMOS transistor N6, an eighth PMOS transistor P8 and a first inverter INV1, wherein the source of the eighth PMOS transistor P8 is used as the input terminal of the charging timing unit, the gate thereof is connected to the gate of the sixth NMOS transistor N6 and the output terminal of the first inverter INV1, and the drain thereof is connected to the drain of the sixth NMOS transistor N6 and is used as the output terminal of the charging timing unit; the second capacitor C2 is connected between the output terminal of the charging timing unit and the ground GND; an input end of the first inverter INV1 is used as a control end of the charging timing unit; the source of the sixth NMOS transistor N6 is grounded.
When the adaptive fixed on-time generation circuit provided by the invention is used for the DC-DC switching converter, the input voltage V of the DC-DC switching converterINConnecting the first input terminal of the adaptive fixed on-time generating circuit to the output voltage V of the DC-DC switching converterOUTAnd the second input end of the self-adaptive fixed on-time generation circuit is connected. The working process of the embodiment is as follows: the input voltage acquisition unit acquires the input voltage V of the DC-DC switch converter through the clamping of the operational amplifierINThe fifth NMOS transistor N5 is regulated by the operational amplifier to clamp the voltage on the first resistor R1, so as to generate a voltage proportional to the input voltage V of the DC-DC switching converterINCharging current I ofIN. The charging timing unit utilizes the charging current IINCharging the second capacitor C2 to obtain a charging voltage VCAPInput voltage V of DC-DC switching converterINThe larger the charging current IINThe larger the charging voltage VCAPThe faster the rise, the smaller the charging time, and thus the resulting on-time TONInput voltage V to DC-DC switching converterINIn inverse proportion; controlling a charging voltage V by a control signal CONCAPThe control signal CON controls the charging voltage V at each arrival of the periodCAPAnd (6) clearing. The comparator will charge voltage VCAPWith the output voltage V of the DC-DC switching converterOUTComparing, when the charging voltage V isCAPUp to the output voltage V of the DC-DC switching converterOUTThe on-time T of the output signalONInverting to obtain the waveform shown in FIG. 4, due to the output voltage V of the DC-DC switching converterOUTThe greater the conduction time TONThe later the flip, the resulting on-timeTONWith the output voltage V of the DC-DC switching converterOUTIs in direct proportion.
In summary, compared with the traditional adaptive conduction time generation circuit, the multiplication and division relation of the current is realized by depending on the addition and subtraction relation of the BE junction voltage of the BJT; the invention utilizes the operational amplifier clamp to acquire the signal of the first input end of the operational amplifier clamp to obtain the charging current which is in direct proportion to the signal of the first input end of the operational amplifier clamp, and utilizes the charging voltage generated by the charging current to compare with the signal of the second input end of the operational amplifier clamp to realize the generated conduction time TONThe signal of the first input end of the invention is inversely proportional to the signal of the second input end of the invention, so that the on-time generated by the invention can be adaptively adjusted according to the signals of the first input end and the second input end of the invention, the transient response of the application circuit of the invention is accelerated, and the application circuit of the invention does not provide a coarse frequency adjustment; the invention can be applied in some special application environments or special processes because BJTs are not used.
Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (3)
1. A self-adaptive fixed on-time generating circuit based on a CMOS (complementary metal oxide semiconductor) process comprises an input voltage acquisition unit, a charging timing unit and a comparator, wherein the input end of the input voltage acquisition unit is used as the first input end of the self-adaptive fixed on-time generating circuit, and the output end of the input voltage acquisition unit outputs charging current (I)IN) An input terminal connected to the charging timing unit; the control end of the charging timing unit is connected with a control signal (CON), and the output end of the charging timing unit is controlled by the control signal (CON) and is based on the charging current (I)IN) Generated charging voltage (V)CAP) (ii) a The positive input end of the comparator is connected with the charging voltage (V)CAP) The inverting input end of the adaptive fixed on-time generating circuit is used as the second input end of the adaptive fixed on-time generating circuit, and the output end of the adaptive fixed on-time generating circuit is used as the output end of the adaptive fixed on-time generating circuit;
the input voltage acquisition unit comprises an operational amplifier, a first resistor (R1), a first capacitor (C1), a fifth NMOS transistor (N5), a sixth PMOS transistor (P6) and a seventh PMOS transistor (P7),
the first input end of the operational amplifier is used as the input end of the input voltage acquisition unit, the second input end of the operational amplifier is connected with the source electrode of the fifth NMOS tube (N5) and is Grounded (GND) after passing through the first resistor (R1), and the output end of the operational amplifier is connected with the grid electrode of the fifth NMOS tube (N5) and is Grounded (GND) after passing through the first capacitor (C1);
the grid electrode of the seventh PMOS tube (P7) is connected with the grid electrode and the drain electrode of the sixth PMOS tube (P6) and the drain electrode of the fifth NMOS tube (N5), the source electrode of the seventh PMOS tube is connected with the source electrode of the sixth PMOS tube (P6) and the power Voltage (VDD), and the drain electrode of the seventh PMOS tube outputs the charging current (I3578)IN)；
The charging timing unit comprises a second capacitor (C2), a sixth NMOS transistor (N6), an eighth PMOS transistor (P8) and a first inverter (INV1),
the source electrode of the eighth PMOS tube (P8) is used as the input end of the charging timing unit, the grid electrode of the eighth PMOS tube (P8) is connected with the grid electrode of the sixth NMOS tube (N6) and the output end of the first inverter (INV1), and the drain electrode of the eighth PMOS tube (P8) is connected with the drain electrode of the sixth NMOS tube (N6) and is used as the output end of the charging timing unit; a second capacitor (C2) is connected between the output end of the charging timing unit and the Ground (GND); an input end of the first inverter (INV1) is used as a control end of the charging timing unit; the source of the sixth NMOS transistor (N6) is grounded.
2. The adaptive fixed on-time generation circuit based on CMOS process of claim 1, wherein the operational amplifier in the input voltage collection unit comprises a first NMOS transistor (N1), a second NMOS transistor (N2), a third NMOS transistor (N3), a fourth NMOS transistor (N4), a first PMOS transistor (P1), a second PMOS transistor (P2), a third PMOS transistor (P3), a fourth PMOS transistor (P4) and a fifth PMOS transistor (P5),
the grid electrode of a fifth PMOS pipe (P5) is used as a first input end of the operational amplifier, the source electrode of the fifth PMOS pipe (P5) is connected with the source electrode of a fourth PMOS pipe (P4) and the drain electrode of a second PMOS pipe (P2), and the drain electrode of the fifth PMOS pipe (P5) is connected with the grid electrode and the drain electrode of a third NMOS pipe (N3) and the grid electrode of a fourth NMOS pipe (N4);
the grid electrode of a fourth PMOS pipe (P4) is used as a second input end of the operational amplifier, and the drain electrode of the fourth PMOS pipe is connected with the grid electrode of a first NMOS pipe (N1) and the grid electrode and the drain electrode of a second NMOS pipe (N2);
the grid electrode of the second PMOS tube (P2) is connected with a bias voltage (V)B1) The sources of the PMOS transistors are connected with the sources of the first PMOS transistor (P1) and the third PMOS transistor (P3) and connected with the power supply Voltage (VDD);
the grid electrode of the third PMOS tube (P3) is connected with the grid electrode and the drain electrode of the first PMOS tube (P1) and the drain electrode of the first NMOS tube (N1), and the drain electrode of the third PMOS tube is connected with the drain electrode of the fourth NMOS tube (N4) and serves as the output end of the operational amplifier;
the source electrodes of the first NMOS transistor (N1), the second NMOS transistor (N2), the third NMOS transistor (N3) and the fourth NMOS transistor (N4) are Grounded (GND).
3. The adaptive fixed on-time generation circuit based on a CMOS process according to claim 1, wherein when the adaptive fixed on-time generation circuit is used in a DC-DC switching converter, an input voltage of the DC-DC switching converter is connected to a first input terminal of the adaptive fixed on-time generation circuit, and an output voltage of the DC-DC switching converter is connected to a second input terminal of the adaptive fixed on-time generation circuit.
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