CN109003909B - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN109003909B CN109003909B CN201810556837.2A CN201810556837A CN109003909B CN 109003909 B CN109003909 B CN 109003909B CN 201810556837 A CN201810556837 A CN 201810556837A CN 109003909 B CN109003909 B CN 109003909B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/63—Connectors not provided for in any of the groups H01L24/10 - H01L24/50 and subgroups; Manufacturing methods related thereto
- H01L24/64—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Wire Bonding (AREA)
Abstract
The flow of the solder is stopped almost without being affected by the atmospheric temperature. The method for manufacturing a semiconductor device includes the steps of: a step of bonding the wire (W1) to the main surface (4 a) of the substrate (4) by ultrasonic bonding in a state in which the wire (W1) surrounds a region (Rg 1) to be supplied with solder (3 n) on the main surface (4 a); and a step of supplying solder (3 n) for bonding the electrode terminal (E1) and the substrate (4) to the region (Rg 1).
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor device for solder bonding of electrode terminals.
Background
In a power semiconductor device, it is required to normally drive the device even in a high-temperature environment. Therefore, in the semiconductor device, it is required to firmly bond the electrode terminal and the substrate using solder. In order to satisfy this requirement, it is conceivable to increase the amount of solder to be used in the joining of the electrode terminals. Further, if the amount of solder is simply increased, the solder is likely to flow to an unintended place. Therefore, a structure for stopping the flow of the solder is required.
Patent document 1: japanese laid-open patent publication No. 2010-251556 (FIG. 1, paragraph 0036)
The protective film of the related structure a is made of, for example, resin. Therefore, the protective film may be peeled off from the metal layer in a high-temperature environment. Therefore, the related structure a has a problem that the flow of the solder may not be stopped depending on the state of the atmospheric temperature. Therefore, a structure capable of stopping the flow of the solder almost without being affected by the air temperature is desired.
Disclosure of Invention
The present invention has been made to solve the above-described problems, and an object thereof is to provide a method for manufacturing a semiconductor device, which can stop the flow of solder with little influence of atmospheric temperature.
In order to achieve the above object, a method for manufacturing a semiconductor device according to one aspect of the present invention bonds an electrode terminal to a substrate using solder paste. The method for manufacturing a semiconductor device includes the steps of: a step of bonding a lead wire to a main surface of the substrate by ultrasonic bonding while the lead wire surrounds a region to be supplied with the solder in the main surface; and supplying the solder for bonding the electrode terminal and the substrate to the region.
ADVANTAGEOUS EFFECTS OF INVENTION
According to the present invention, the lead wire is bonded to the main surface of the substrate by ultrasonic bonding in a state in which the lead wire surrounds a region to be a supply target of the solder. Supplying the solder for bonding the electrode terminal and the substrate to the region.
The wire is less likely to be deformed depending on the temperature than resin. Therefore, the flow of the solder can be stopped by the wire with little influence of the atmospheric temperature.
Drawings
Fig. 1 is a cross-sectional view of a semiconductor device according to embodiment 1 of the present invention.
Fig. 2 is a diagram showing a characteristic configuration of embodiment 1 of the present invention.
Fig. 3 is a flowchart of a semiconductor manufacturing method according to embodiment 1 of the present invention.
Fig. 4 is a diagram showing a configuration according to modification 1 of embodiment 1 of the present invention.
Fig. 5 is a diagram showing a configuration according to modification 2 of embodiment 1 of the present invention.
Description of the reference symbols
3. 3n solder, 4A, 4B substrate, 100 semiconductor device, E1 electrode terminal, S1 semiconductor chip, W1a, W1B wire.
Detailed Description
Embodiments of the present invention will be described below with reference to the drawings. In the following drawings, the same components are denoted by the same reference numerals. The names and functions of the components denoted by the same reference numerals are the same. Therefore, detailed description of a part of each component denoted by the same reference numeral may be omitted.
The dimensions, materials, shapes, relative arrangements of the respective constituent elements, and the like of the constituent elements exemplified in the embodiments may be appropriately changed according to the structure of the apparatus to which the present invention is applied, various conditions, and the like.
< embodiment 1>
Fig. 1 is a cross-sectional view of a semiconductor device 100 according to embodiment 1 of the present invention. The semiconductor device 100 is a power module used in industrial equipment, automobiles, electric trains, and the like.
In fig. 1, the X direction, the Y direction, and the Z direction are orthogonal to each other. The X direction, Y direction, and Z direction shown in the following figures are also orthogonal to each other. Hereinafter, a direction including the X direction and a direction opposite to the X direction (the (-X direction)) is also referred to as an "X axis direction". Hereinafter, a direction including the Y direction and a direction opposite to the Y direction (the (-Y direction)) is also referred to as a "Y axis direction". Hereinafter, a direction including the Z direction and a direction opposite to the Z direction (the (-Z direction)) is also referred to as a "Z axis direction".
Hereinafter, a plane including the X-axis direction and the Y-axis direction is also referred to as an "XY plane". Hereinafter, a plane including the X-axis direction and the Z-axis direction is also referred to as an "XZ plane". Hereinafter, a plane including the Y-axis direction and the Z-axis direction is also referred to as a "YZ plane".
Referring to fig. 1, a semiconductor device 100 includes: semiconductor chip S1, substrate 4A, substrate 4B, base plate 5, heat dissipation plate 6, electrode terminal E1, case 8, and resin 9.
The heat sink 6 is bonded to the substrate 4B with solder 3 interposed therebetween. The substrate 4B is an insulating substrate. The substrate 4B is provided with an electric circuit (not shown). The base plate 4B is joined to the base plate 5. The susceptor plate 5 is made of AlN (aluminum nitride), for example.
A substrate 4 and a substrate 4A are bonded to the base plate 5. The substrate 4A is an insulating substrate. The substrate 4A is provided with an electric circuit (not shown). Further, a semiconductor chip S1 is bonded to the substrate 4A via a solder 3.
The Semiconductor chip S1 is, for example, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or the like. The semiconductor chip S1 is connected to an electric circuit (not shown) of the substrate 4 via a wire Wn.
The substrate 4 is an insulating substrate. The substrate 4 is provided with an electric circuit (not shown). Further, the electrode terminal E1 is joined to the substrate 4 via the solder 3.
A cylindrical case 8 is connected to the heat sink 6. The case 8 is connected to the peripheral edge of the heat sink 6 so that the case 8 surrounds the substrates 4, 4A, 4B, the semiconductor chip S1, the base plate 5, and the like. That is, the substrates 4, 4A, 4B, the semiconductor chip S1, the base plate 5, and the like are accommodated by the case 8 and the heat dissipation plate 6. Further, a part of the electrode terminal E1 is fixed to the case 8. The inside of the case 8 is filled with a resin 9. The resin 9 is, for example, silicone gel. Further, a cover 10 is provided on the upper portion of the housing 8.
(characteristic Structure)
Next, a characteristic structure of the present invention (hereinafter, also referred to as "structure Ct 1") will be described. The structure Ct1 is a structure for bonding the electrode terminal to the substrate by solder.
Fig. 2 is a diagram showing a characteristic structure Ct1 of embodiment 1 of the present invention. Fig. 2 shows the electrode terminal E1 and the configuration of the periphery of the electrode terminal E1. That is, fig. 2 shows a part of the semiconductor device 100 of fig. 1. Fig. 2 (a) is a top view of a part of the semiconductor device 100. Fig. 2 (b) is a cross-sectional view of a portion of the semiconductor device 100 taken along line A1-A2 of fig. 2 (a).
Hereinafter, the solder having viscosity is also referred to as "solder 3n". The solder 3n is, for example, a solder paste. The solder paste is a paste-like solder. In addition, the solder paste is also called a paste solder. The solder 3n is melted by heating the solder 3n, and then the solder 3n is solidified to obtain the solder 3.
Referring to fig. 2 (a), the substrate 4 has a main surface 4a. Hereinafter, a region to be supplied with the solder 3n on the main surface 4a of the substrate 4 is also referred to as a "region Rg1".
The lead W1 is bonded to the main surface 4a of the substrate 4. The shape of the wire W1 is a closed loop shape in a plan view (XY plane). The lead W1 is bonded to the main surface 4a of the substrate 4 such that the lead W1 surrounds the region Rg1 in a plan view (XY plane). In the region Rg1, the electrode terminal E1 is bonded to the substrate 4 via the solder 3.
The wire W1 of the present embodiment is made of Al (aluminum). Hereinafter, the wire W1 made of Al is also referred to as "wire W1a".
Hereinafter, the step of bonding the electrode terminal E1 and the substrate 4 with the solder 3n is also referred to as a "semiconductor manufacturing method Pr". The semiconductor manufacturing method Pr is performed in a state where the wire W1 is not present on the main surface 4a of the substrate 4.
Hereinafter, a device having a function of ultrasonic bonding is also referred to as a "bonding device". Ultrasonic bonding is a process of applying ultrasonic vibration to a bonding object in a state where the bonding object is pressurized. The object to be bonded is, for example, a wire W1. Hereinafter, a device having a function of supplying the solder 3n is also referred to as a "solder supplying device".
Next, a semiconductor manufacturing method Pr in this embodiment will be described. The semiconductor manufacturing method Pr is a process included in a manufacturing method for manufacturing the semiconductor device 100.
Fig. 3 is a flowchart of a semiconductor manufacturing method Pr according to embodiment 1 of the present invention. In the semiconductor manufacturing method Pr, first, the process of step S110 is performed.
In step S110, a wire bonding process is performed. Referring to fig. 2 (a), in the wire bonding step, the wire W1 is placed on the main surface 4a of the substrate 4 so that the wire W1 surrounds the region Rg1 in a plan view (XY plane).
Then, the bonding device bonds the wire W1 to the principal surface 4a by ultrasonic bonding in a state where the wire W1 surrounds the region Rg1 of the principal surface 4a. Specifically, the bonding apparatus applies ultrasonic vibration to the wire W1 in a state where the wire W1 is pressurized by the bonding apparatus, thereby bonding the wire W1 to the main surface 4a. Then, the process of step S120 is performed.
In step S120, a solder supplying step is performed. In the solder supplying process, the solder supplying device supplies the solder 3n to the area Rg1 surrounded by the wire W1. The solder 3n supplied to the region Rg1 is a member for bonding the electrode terminal E1 with the substrate 4. Then, the process of step S130 is performed.
In step S130, a terminal bonding process is performed. In the terminal bonding step, the end of the electrode terminal E1 is fixed in the solder 3n present in the region Rg1. Then, the solder 3n is heated. Thereby, after the solder 3n is melted, the solder 3n is solidified to become the solder 3. Thereby, the electrode terminal E1 is joined to the substrate 4 via the solder 3. In this way, the semiconductor manufacturing method Pr ends.
As described above, the semiconductor manufacturing method Pr of the present embodiment includes: a step of bonding the wire W1 to the main surface 4a by ultrasonic bonding in a state where the wire W1 surrounds a region Rg1 to be a supply target of the solder 3n in the main surface 4a of the substrate 4; and a step of supplying solder 3n for bonding the electrode terminal E1 and the substrate 4 to the region Rg1.
The wire is less likely to be deformed depending on the temperature than resin. Therefore, the flow of the solder 3n can be stopped by the wire W1 with little influence of the atmospheric temperature.
The lead wire W1 of the present embodiment is a lead wire W1a made of Al. Therefore, even if the wire W1 made of Al is used, the above-described effect is obtained.
In the present embodiment, the closed loop-shaped wire W1 is bonded to the substrate 4 by ultrasonic bonding. Then, solder 3n having viscosity is supplied to the region Rg1 surrounded by the wire W1. Thus, the wire W1 functions as a wall preventing the flow of the solder 3n.
Therefore, the solder 3n can be prevented from adhering to the lead Wn, the base plate 5, and the like. In addition, in order to prevent the flow of the solder 3n, the amount of the solder 3n to be supplied can be increased in the region Rg1 in the wire W1. Further, by heating the increased amount of solder 3n, the solder 3n is melted, and then the solder 3n is solidified to form the solder 3. Therefore, the amount of solder 3 for joining the electrode terminal E1 and the substrate 4 can be increased. This can improve the strength of the bonding of the electrode terminal E1 to the substrate 4. Therefore, a semiconductor device (power module) with high reliability can be obtained as compared with the related art.
In addition, the power module during driving generates heat. When the temperature of the heat is extremely high, the case 8, the heat sink 6, the substrate 4, and the like may be deformed. Further, a part of the electrode terminal E1 is fixed to the case 8. Therefore, if the case 8 is deformed, stress is applied to the solder 3 joining the electrode terminal E1 and the substrate 4. Such as tensile stress, compressive stress, etc. Therefore, if the strength of the joint of the electrode terminal E1 and the substrate 4 by the solder 3 is small, there is a problem that the electrode terminal E1 is peeled off from the substrate 4.
Further, in order to improve the strength of the above-described joining, it is conceivable to increase the amount of solder paste for joining the electrode terminal E1 and the substrate 4. However, in the case where the amount of the solder paste is increased, there is a problem that the solder paste is likely to adhere to components (the base plate, the insulating member, and the like) present in the periphery of the electrode terminal.
The solder paste is obtained by adding flux to solder powder. The solder paste has an appropriate viscosity. Further, when the solder paste is heated to melt it, the viscosity of the solder paste decreases. In this case, there is a problem that the solder powder contained in the solder paste adheres to components (the base plate, the insulating portion, and the like) present in the periphery of the electrode terminal before the solder paste is melted.
Therefore, the semiconductor manufacturing method Pr of the present embodiment is performed in the above manner. Therefore, the semiconductor manufacturing method Pr of the present embodiment can solve the above-described various problems.
< modification 1 of embodiment 1>
Hereinafter, the structure of this modification is also referred to as "structure Ctm1". In the structure Ctm1, the wire W1 is made of Cu (copper).
Fig. 4 is a diagram showing a structure Ctm1 according to modification 1 of embodiment 1 of the present invention. Fig. 4 (a) is a plan view of a part of the semiconductor device 100 according to modification 1. Fig. 4 (b) is a cross-sectional view of a part of semiconductor device 100 according to modification 1 taken along line A1-A2 of fig. 4 (a).
Structure Ctm1 is different from structure Ct1 of fig. 2 only in that wire W1 is made of Cu instead of Al. The other structure of the structure Ctm1 is the same as that of the structure Ct1, and therefore, detailed description thereof is omitted. Hereinafter, the wire W1 made of Cu is also referred to as "wire W1b". The shape of the wire Wb in the structure Ctm1 is the same as that of the wire W1 in the structure Ct 1.
In the structure Ctm1, the semiconductor manufacturing method Pr described above is also performed as in embodiment 1.
According to this modification, even if the lead wire W1 is made of Cu, the same effect as that of embodiment 1 is obtained.
< modification 2 of embodiment 1>
Hereinafter, the structure of this modification is also referred to as "structure Ctm2". In the structure Ctm2, the wire W1 is made of Au (gold).
Fig. 5 is a diagram showing a structure Ctm2 according to modification 2 of embodiment 1 of the present invention. Fig. 5 (a) is a plan view of a part of the semiconductor device 100 according to modification 2. Fig. 5 (b) is a cross-sectional view of a part of semiconductor device 100 according to modification 2 taken along line A1-A2 of fig. 5 (a).
The structure Ctm2 is different from the structure Ct1 of fig. 2 only in that the wire W1 is made of Au instead of Al. The other structure of the structure Ctm2 is the same as that of the structure Ct1, and therefore, detailed description thereof is omitted. Hereinafter, the wire W1 made of Au is also referred to as "wire W1c". The shape of the wire W1c in the structure Ctm2 is the same as that of the wire W1 in the structure Ct 1.
In the structure Ctm2, the semiconductor manufacturing method Pr described above is also performed as in embodiment 1.
According to this modification, even if the wire W1 is made of Au, the same effect as that of embodiment 1 is obtained.
In addition, the present invention can freely combine the embodiments and the modifications thereof, or can suitably modify and omit the embodiments and the modifications thereof within the scope of the present invention.
Claims (4)
1. A method for manufacturing a semiconductor device, which uses a paste-like solder to bond an electrode terminal to a substrate,
the method for manufacturing a semiconductor device includes the steps of:
a step (S1) of bonding a wire to a main surface of the substrate by ultrasonic bonding while the wire surrounds a region to be supplied with the solder in the main surface; and
a step (S2) of supplying the solder for bonding the electrode terminal and the substrate to the region,
the shape of the wire in a plan view is a closed loop,
the shape of the cross section of the wire is circular,
in the step (S1), the wire is bonded to the main surface over the entire circumference of the wire by applying ultrasonic vibration to the wire.
2. The method for manufacturing a semiconductor device according to claim 1,
the wire is composed of Al.
3. The method for manufacturing a semiconductor device according to claim 1,
the wire is composed of Cu.
4. The method for manufacturing a semiconductor device according to claim 1,
the wire is made of Au.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017-112239 | 2017-06-07 | ||
| JP2017112239A JP6952503B2 (en) | 2017-06-07 | 2017-06-07 | Manufacturing method of semiconductor devices |
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| CN109003909A CN109003909A (en) | 2018-12-14 |
| CN109003909B true CN109003909B (en) | 2023-01-06 |
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| JPH08236575A (en) * | 1995-02-22 | 1996-09-13 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
| JPH10199923A (en) * | 1997-01-13 | 1998-07-31 | Hitachi Ltd | Power semiconductor module |
| JP2002270629A (en) * | 2001-03-07 | 2002-09-20 | Matsushita Electric Ind Co Ltd | Electronic component and manufacturing method therefor |
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| JP2010123854A (en) * | 2008-11-21 | 2010-06-03 | Renesas Technology Corp | Method of manufacturing semiconductor device and wire bonding equipment |
| CN204596789U (en) * | 2015-05-06 | 2015-08-26 | 嘉兴斯达微电子有限公司 | The power semiconductor modular of band clasp structural housing |
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| JP2803159B2 (en) * | 1989-05-23 | 1998-09-24 | セイコーエプソン株式会社 | Active matrix panel |
| JP2005050886A (en) * | 2003-07-29 | 2005-02-24 | Kyocera Corp | Compound substrate and its manufacturing method |
| JP4988531B2 (en) * | 2006-12-18 | 2012-08-01 | 日東電工株式会社 | Adhesive sheet for manufacturing semiconductor device, and method for manufacturing semiconductor device using the same |
| US7825501B2 (en) * | 2007-11-06 | 2010-11-02 | Fairchild Semiconductor Corporation | High bond line thickness for semiconductor devices |
| US9147665B2 (en) * | 2007-11-06 | 2015-09-29 | Fairchild Semiconductor Corporation | High bond line thickness for semiconductor devices |
| JP2011222823A (en) * | 2010-04-12 | 2011-11-04 | Toyota Motor Corp | Circuit device and manufacturing method thereof |
| JP6381489B2 (en) * | 2015-07-02 | 2018-08-29 | 三菱電機株式会社 | Manufacturing method of semiconductor device |
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2017
- 2017-06-07 JP JP2017112239A patent/JP6952503B2/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08236575A (en) * | 1995-02-22 | 1996-09-13 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
| JPH10199923A (en) * | 1997-01-13 | 1998-07-31 | Hitachi Ltd | Power semiconductor module |
| JP2002270629A (en) * | 2001-03-07 | 2002-09-20 | Matsushita Electric Ind Co Ltd | Electronic component and manufacturing method therefor |
| JP2006156795A (en) * | 2004-11-30 | 2006-06-15 | Toyota Motor Corp | Method of joining semiconductor device |
| EP1811557A2 (en) * | 2006-01-24 | 2007-07-25 | NEC Electronics Corporation | Semiconductor apparatus manufacturing method |
| JP2010123854A (en) * | 2008-11-21 | 2010-06-03 | Renesas Technology Corp | Method of manufacturing semiconductor device and wire bonding equipment |
| CN204596789U (en) * | 2015-05-06 | 2015-08-26 | 嘉兴斯达微电子有限公司 | The power semiconductor modular of band clasp structural housing |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109003909A (en) | 2018-12-14 |
| JP6952503B2 (en) | 2021-10-20 |
| JP2018207002A (en) | 2018-12-27 |
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