CN109003574B

CN109003574B - Pixel unit, driving method, pixel module, driving method of pixel module and display device

Info

Publication number: CN109003574B
Application number: CN201810928371.4A
Authority: CN
Inventors: 陈亮; 王磊; 肖丽; 玄明花; 刘冬妮; 赵德涛; 杨盛际; 陈小川
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2018-08-15
Filing date: 2018-08-15
Publication date: 2021-01-22
Anticipated expiration: 2038-08-15
Also published as: CN109003574A

Abstract

The invention provides a pixel unit, a driving method, a pixel module, a driving method of the pixel module and a display device. The pixel unit includes a first light emitting element and a second light emitting element, and the pixel unit further includes: a drive circuit; an initial circuit; a tank circuit; a compensation control circuit; a data write circuit; the first light-emitting control circuit is respectively connected with the second end of the driving circuit, the first light-emitting control line and the first light-emitting element and is used for controlling the connection between the second end of the driving circuit and the first light-emitting element to be switched on or off under the control of the first light-emitting control line; and the second light-emitting control circuit is respectively connected with the second end of the driving circuit, the second light-emitting control line and the second light-emitting element and is used for controlling the connection between the second end of the driving circuit and the second light-emitting element to be switched on or switched off under the control of the second light-emitting control line. The present invention facilitates high PPI (Pixels Per Inch available from Pixels Per inc).

Description

Pixel unit, driving method, pixel module, driving method of pixel module and display device

Technical Field

The invention relates to the technical field of display, in particular to a pixel unit, a driving method, a pixel module, a driving method of the pixel module and a display device.

Background

The OLED (organic light emitting diode) has the advantages of active light emitting, no view angle problem, light weight, small thickness, high brightness, high light emitting efficiency, high response speed, high dynamic picture quality, wide use temperature range, flexible display, simple process, low cost and strong shock resistance. However, since the OLED display requires a complex pixel compensation circuit, the improvement of PPI (pixel Per Inch, number of Pixels Per Inch) of the OLED display screen is restricted.

Disclosure of Invention

The present invention provides a pixel unit, a driving method, a pixel module, a driving method thereof, and a display device, which solve the problem that high PPI (pixel count Per Inch) cannot be achieved in the prior art.

In order to achieve the above object, the present invention provides a pixel unit including a first light emitting element and a second light emitting element, the pixel unit further including:

the control end of the driving circuit is connected with the driving node, the first end of the driving circuit is connected with the first voltage end, and the driving circuit is used for switching on or switching off the connection between the first voltage end and the second end of the driving circuit under the control of the driving node;

the initial circuit is respectively connected with an initial control line, the driving node and an initial voltage end and is used for controlling the writing of the initial voltage on the initial voltage end into the driving node under the control of the initial control line;

the first end of the energy storage circuit is connected with the driving node, and the second end of the energy storage circuit is connected with the data writing node;

the compensation control circuit is respectively connected with the nth row of grid lines, the data writing nodes, the driving nodes and the second end of the driving circuit, and is used for controlling the data voltage on the data lines to be written into the data writing nodes and controlling the driving nodes to be communicated with the second end of the driving circuit under the control of the nth row of grid lines; n is a positive integer;

the data writing circuit is respectively connected with a writing control line, a second voltage end and the data writing node and is used for controlling the writing of a second voltage output by the second voltage end into the data writing node under the control of the writing control line so as to correspondingly change the potential of the driving node;

the first light-emitting control circuit is respectively connected with the second end of the driving circuit, a first light-emitting control line and a first light-emitting element and is used for controlling the connection between the second end of the driving circuit and the first light-emitting element to be switched on or switched off under the control of the first light-emitting control line; and the number of the first and second groups,

and the second light-emitting control circuit is respectively connected with the second end of the driving circuit, the second light-emitting control line and the second light-emitting element and is used for controlling the connection between the second end of the driving circuit and the second light-emitting element to be switched on or switched off under the control of the second light-emitting control line.

In implementation, the writing control line is the (n +1) th row of grid lines;

n is greater than 1, and the initial control line is the (n-1) th row of grid lines; alternatively, n is equal to 1, and the initial control line is a start signal line.

In practice, the first light emitting element is a first organic light emitting diode, and the second light emitting element is a second organic light emitting diode;

the driving circuit comprises a driving transistor, the grid electrode of the driving transistor is the control end of the driving circuit, the first electrode of the driving transistor is the first end of the driving circuit, and the second electrode of the driving transistor is the second end of the driving circuit;

the initial circuit comprises an initial transistor, the grid electrode of the initial transistor is connected with the initial control line, the first pole of the initial transistor is connected with the driving node, and the second pole of the initial transistor is connected with the initial voltage end;

the energy storage circuit comprises a storage capacitor, a first end of the storage capacitor is connected with the driving node, and a second end of the storage capacitor is connected with the data writing node.

In practice, the compensation control circuit includes a first compensation control transistor and a second compensation control transistor, wherein,

the grid electrode of the first compensation control transistor is connected with the nth row of grid lines, the first pole of the first compensation control transistor is connected with the driving node, and the second pole of the first compensation control transistor is connected with the second end of the driving circuit;

a gate of the second compensation control transistor is connected to the nth row gate line, a first pole of the second compensation control transistor is connected to the data writing node, and a second pole of the second compensation control transistor is connected to the data line;

the data writing circuit comprises a data writing transistor, the grid electrode of the data writing transistor is connected with the writing control line, the first pole of the data writing transistor is connected with the second voltage end, and the second pole of the data writing transistor is connected with the data writing node.

In an implementation, the first light-emitting control circuit includes a first light-emitting control transistor, a gate of the first light-emitting control transistor is connected to the first light-emitting control line, a first pole of the first light-emitting control transistor is connected to the second terminal of the driving circuit, and a second pole of the first light-emitting control transistor is connected to the first light-emitting element;

the second light-emitting control circuit comprises a second light-emitting control transistor, a grid electrode of the second light-emitting control transistor is connected with the second light-emitting control line, a first electrode of the second light-emitting control transistor is connected with a second end of the driving circuit, and a second electrode of the second light-emitting control transistor is connected with the second light-emitting element.

The present invention further provides a pixel driving method applied to the pixel unit, where a display period includes a first display sub-period and a second display sub-period, which are sequentially arranged, the first display sub-period includes a first initial stage, a first compensation stage, a first data writing stage and a first light emitting stage, which are sequentially arranged, and the second display sub-period includes a second initial stage, a second compensation stage, a second data writing stage and a second light emitting stage, which are sequentially arranged, and the pixel driving method includes:

in the first initial stage and the second initial stage, an initial voltage end outputs an initial voltage, and an initial circuit controls the initial voltage to be written into a driving node under the control of an initial control line;

in the first compensation stage and the second compensation stage, the data line outputs a data voltage, and the compensation control circuit controls the data voltage to be written into the data writing node under the control of the nth row of grid lines and controls the driving node to be communicated with the second end of the driving circuit; n is a positive integer;

in the first data writing phase and the second data writing phase, under the control of a writing control line, the data writing circuit writes a second voltage V2 output by a second voltage end into a data writing node so as to write the data voltage into the driving node;

in the first light-emitting stage, a driving circuit is controlled by the driving node to conduct the connection between the first voltage end and the second end of the driving circuit, a first light-emitting control circuit is controlled by the first light-emitting control line to conduct the connection between the second end of the driving circuit and the first light-emitting element, and the driving circuit drives the first light-emitting element to emit light;

in the second light-emitting stage, the driving circuit is controlled by the driving node to conduct the connection between the first voltage end and the second end of the driving circuit, the second light-emitting control circuit is controlled by the second light-emitting control line to conduct the connection between the second end of the driving circuit and the second light-emitting element, and the driving circuit drives the second light-emitting element to emit light.

In practice, the pixel driving method of the present invention further includes:

in the first compensation phase and the second compensation phase, the driving circuit turns on the connection between the first terminal and the second terminal thereof until the potential of the driving node becomes V1+ Vth, V1 is a first voltage output by the first voltage terminal, and Vth is a threshold voltage of a driving transistor included in the driving circuit;

controlling the potential of the driving node to become V1+ V2-Vdata + Vth in the first data writing phase and the second data writing phase.

The invention also provides a pixel module, which comprises two pixel units;

the first pixel unit comprises a 2n-1 th row and an m column light-emitting element and a 2n row and an m column light-emitting element, and the second pixel unit comprises a 2n +1 th row and an m column light-emitting element and a 2n +2 th row and an m column light-emitting element;

a first initial circuit included in the first pixel unit is connected with an nth initial control line, and a second initial circuit included in the second pixel unit is connected with an n +1 th initial control line;

the first compensation control circuit included in the first pixel unit is connected with the nth row of grid lines, and the second compensation control circuit included in the second pixel unit is connected with the (n +1) th row of grid lines;

a first data writing circuit included in the first pixel unit is connected with an nth writing control line, and a second data writing circuit included in the second pixel unit is connected with an n +1 th writing control line;

a first light-emitting control circuit included in the first pixel unit is connected with a light-emitting control line of a 2n-1 th row, a second light-emitting control circuit included in the first pixel unit is connected with a light-emitting control line of a 2n-1 th row, a third light-emitting control circuit included in the second pixel unit is connected with a light-emitting control line of a 2n-1 th row, and a fourth light-emitting control circuit included in the second pixel unit is connected with a light-emitting control line of a 2n-1 th row;

n and m are both positive integers.

In implementation, the nth writing control line is a (n +1) th row of gate lines, and the (n +1) th row of writing control line is a (n +2) th row of gate lines;

n is equal to 1, the nth initial control line is an initial signal line, and the (n +1) th initial control line is an nth grid line; or n is larger than 1, the nth initial control line is the (n-1) th grid line, and the (n +1) th initial control line is the nth grid line.

The invention also provides a pixel driving method, which is applied to the pixel module, wherein a display period comprises a first display sub-period and a second display sub-period which are sequentially arranged, the first display sub-period comprises a first initial stage, a first compensation stage, a first data writing stage, a second data writing stage and a first light-emitting stage which are sequentially arranged, the second display sub-period comprises a second initial stage, a second compensation stage, a third data writing stage, a fourth data writing stage and a second light-emitting stage which are sequentially arranged, and the pixel driving method comprises the following steps:

in a first initial stage and a second initial stage, an initial voltage end outputs an initial voltage, and a first initial circuit controls to write the initial voltage into a first driving node under the control of an nth initial control line; n is a positive integer; the first driving node is a driving node in the first pixel unit;

in a first compensation stage, a data line outputs a first data voltage, and a first compensation control circuit controls the first data voltage to be written into a first data writing node under the control of an nth row of grid lines and controls the first driving node to be communicated with a second end of the first driving circuit; the initial voltage end outputs initial voltage, and the second initial circuit controls the initial voltage to be written into a second driving node under the control of an n +1 th initial control line; the first data writing node is a data writing node in the first pixel unit, and the second driving node is a driving node in the second pixel unit;

in the first data writing phase, under the control of the nth writing control line, the first data writing circuit writes the second voltage V2 output by the second voltage end into the first data writing node; the data line outputs a second data voltage, and the second compensation control circuit controls the second data voltage to be written into the second data writing node under the control of the (n +1) th row of grid lines and controls the second driving node to be communicated with the second end of the second driving circuit; the second data writing node is a data writing node in the second pixel unit;

in the second data write phase, the second data write circuit writes the second voltage V2 to the second data write node under the control of the (n +1) th write control line;

in the first light-emitting stage, a first driving circuit is controlled by a first driving node to conduct the connection between a first voltage end and a second end of the first driving circuit, a first light-emitting control circuit is controlled by a 2n-1 row light-emitting control line to conduct the connection between the second end of the first driving circuit and a 2n-1 row mth column light-emitting element, and the first driving circuit drives a 2n-1 row mth column light-emitting element to emit light; the second driving circuit is controlled by a second driving node to conduct the connection between a first voltage end and a second end of the second driving circuit, the third light-emitting control circuit is controlled by a 2n-1 row light-emitting control line to conduct the connection between the second end of the second driving circuit and the m-th column light-emitting element of the 2n +1 row, and the second driving circuit drives the m-th column light-emitting element of the 2n +1 row to emit light;

in the second compensation stage, the data line outputs a third data voltage, and the first compensation control circuit writes the third data voltage into the first data writing node under the control of the nth row of grid lines and controls the first driving node to be communicated with the second end of the first driving circuit; the initial voltage end outputs initial voltage, and the second initial circuit controls the writing of the initial voltage into the second driving node under the control of the (n +1) th initial control line;

in the third data write phase, the second data write circuit writes the second voltage V2 to the second data write node under the control of the nth write control line to write the third data voltage to the first driving node; the data line outputs a fourth data voltage, and the second compensation control circuit controls the fourth data voltage to be written into a second data writing node under the control of the (n +1) th row of grid lines and controls the second driving node to be communicated with a second end of the second driving circuit;

in a fourth data write phase, the second data write circuit writes the second voltage V2 to the second data write node under the control of the (n +1) th write control line to write the fourth data voltage to the second drive node;

in the second light-emitting stage, the first driving circuit is controlled by the first driving node to conduct the connection between the first voltage end and the second end of the first driving circuit, the fourth light-emitting control circuit is controlled by the 2 nth row light-emitting control line to conduct the connection between the second end of the first driving circuit and the 2 nth row and mth column light-emitting element, and the first driving circuit drives the 2 nth row and mth column light-emitting element to emit light; the second driving circuit is controlled by the second driving node to conduct the connection between the first voltage end and the second end of the second driving circuit, the fourth light-emitting control circuit is controlled by the 2 nth row light-emitting control line to conduct the connection between the second end of the second driving circuit and the mth column light-emitting element in the 2n +2 th row, and the second driving circuit drives the mth column light-emitting element in the 2n +2 th row to emit light;

m is a positive integer.

The invention also provides a display device which comprises N stages and M rows of the pixel module, wherein N and M are positive integers.

In practice, the first pixel unit included in the nth-stage mth-column pixel module comprises a 2n-1 th row and an mth column light-emitting element and a 2n th row and an mth column light-emitting element; n and m are both positive integers;

the first pixel unit included in the nth row pixel module is respectively connected with the nth initial control line, the nth row grid line, the nth writing control line, the 2n-1 th row light-emitting control line and the 2 nth row light-emitting control line;

the second pixel unit included in the nth-stage mth-column pixel module comprises a 2n +1 th row and mth column light-emitting element and a 2n +2 nd row and mth column light-emitting element;

the second pixel units included in the mth-stage mth-row pixel module are respectively connected with the (n +1) th initial control line, the (n +1) th row of grid lines, the (n +1) th writing control line, the (2n-1) th row of light-emitting control line and the (2n) th row of light-emitting control line.

In implementation, the nth writing control line is an n +1 th row of gate lines, and the n +1 th writing control line is an n +2 th row of gate lines;

Compared with the prior art, the pixel unit, the driving method, the pixel module, the driving method and the display device drive the two light-emitting elements to emit light through one pixel compensation circuit, so that the pixel compensation circuit is multiplexed, and high PPI is favorably realized.

Drawings

FIG. 1 is a block diagram of a pixel cell according to an embodiment of the invention;

FIG. 2 is a timing diagram illustrating operation of a pixel unit according to an embodiment of the present invention;

FIG. 3 is a circuit diagram of a first embodiment of a pixel cell according to the present invention;

FIG. 4 is a circuit diagram of a second embodiment of a pixel cell according to the present invention;

FIG. 5 is a timing diagram illustrating the operation of a second embodiment of a pixel cell according to the present invention;

FIG. 6 is a block diagram of a pixel module according to an embodiment of the invention;

FIG. 7 is a circuit diagram of one embodiment of a pixel module according to the present invention;

FIG. 8 is a timing diagram illustrating operation of the pixel module according to the embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices having the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except for the gate, one of the two poles is referred to as a first pole, and the other pole is referred to as a second pole. In practical operation, the first pole may be a drain, and the second pole may be a source; alternatively, the first pole may be a source and the second pole may be a drain.

As shown in fig. 1, a pixel unit according to an embodiment of the present invention includes a first light-emitting element EL1 and a second light-emitting element EL2, and the pixel unit further includes:

the driving circuit 11 has a control terminal connected to a driving node a, a first terminal connected to a first voltage terminal VT1, and is configured to turn on or off a connection between the first voltage terminal VT1 and a second terminal of the driving circuit 11 under the control of the driving node a;

an initial circuit 12, respectively connected to an initial control line Gate (n-1), the driving node a and an initial voltage terminal for inputting an initial voltage Vinit, for controlling to write the initial voltage Vinit on the initial voltage terminal into the driving node under the control of the initial control line Gate (n-1);

a first end of the energy storage circuit 13 is connected with the driving node a, and a second end of the energy storage circuit is connected with the data writing node b;

the compensation control circuit 14 is respectively connected to the Gate line Gate (n) in the nth row, the Data line Data, the Data writing node b, the driving node a, and the second end of the driving circuit 11, and is configured to control, under the control of the Gate line Gate (n) in the nth row, writing of the Data voltage on the Data line Data into the Data writing node b, and control communication between the driving node a and the second end of the driving circuit 11; n is a positive integer;

a data writing circuit 15, respectively connected to the writing control line EMn, the second voltage terminal VT2 and the data writing node b, for controlling the writing of the second voltage output from the second voltage terminal VT2 into the data writing node b under the control of the writing control line EMn, so as to correspondingly change the potential of the driving node a;

a first light emission control circuit 16 connected to the second terminal of the driving circuit 11, a first light emission control line EM (n _1), and a first light emitting element EL1, respectively, for controlling on/off of the connection between the second terminal of the driving circuit 11 and the first light emitting element EL1 under the control of the first light emission control line EM (n _ 1); and the number of the first and second groups,

and a second emission control circuit 17 connected to the second terminal of the driving circuit 11, the second emission control line EM (n _2), and the second emission element EL2, respectively, for controlling to turn on or off the connection between the second terminal of the driving circuit 11 and the second emission element EL2 under the control of the second emission control line EM (n _ 2).

The pixel unit according to the embodiment of the invention drives two light emitting elements to emit light through one pixel compensation circuit, so that multiplexing of the pixel compensation circuit is realized, the driving circuit of each two sub-pixels is reduced from 12T2C (12T2C means that 12 transistors and 2 capacitors are adopted) to 7T1C (7T1C means that 7 transistors and 1 capacitor are adopted), and an Active-matrix organic light emitting diode (Active-matrix organic light emitting diode) display device with high PPI is realized.

As shown in fig. 2, when the embodiment of the pixel unit shown in fig. 1 of the present invention is operated, one display cycle includes a first display sub-cycle Subframe1 and a second display sub-cycle Subframe2, which are sequentially arranged, the first display sub-cycle Subframe1 includes a first initial phase t1, a first compensation phase t2, a first data writing phase t3 and a first light-emitting phase t4, which are sequentially arranged, the second display sub-cycle Subframe2 includes a second initial phase t5, a second compensation phase t6, a second data writing phase t7 and a second light-emitting phase t8, which are sequentially arranged,

in the first initial stage t1 and the second initial stage t5, the initial voltage terminal outputs an initial voltage Vinit, which the initial circuit 12 controls to write into the driving node a under the control of the initial control line Gate (n-1);

in the first compensation phase t2 and the second compensation phase t6, the Data line Data outputs a Data voltage Vdata, and the compensation control circuit 14 controls to write the Data voltage Vdata into the Data writing node b under the control of the Gate line Gate (n) in the nth row, and controls the connection between the driving node a and the second end of the driving circuit 11; n is a positive integer;

in the first and second data writing phases t3 and t7, the data writing circuit 15 writes the second voltage V2 output from the second voltage terminal VT2 into the data writing node b under the control of the writing control line EMn to write the data voltage Vdata into the driving node a;

in the first light-emitting period t4, the driving circuit 11 controls to turn on the connection between the first voltage terminal VT1 and the second terminal of the driving circuit 11 under the control of the driving node a, the first light-emitting control circuit 16 controls to turn on the connection between the second terminal of the driving circuit 11 and the first light-emitting element EL1 under the control of the first light-emitting control line EM (n _1), and the driving circuit 11 drives the first light-emitting element EL1 to emit light;

in the second light-emitting period t8, the driving circuit 11 controls the connection between the first voltage terminal VT1 and the second terminal of the driving circuit 11 under the control of the driving node a, the second light-emitting control circuit 17 controls the connection between the second terminal of the driving circuit 11 and the second light-emitting element EL2 under the control of the second light-emitting control line EM (n _2), and the driving circuit 11 drives the second light-emitting element EL2 to emit light.

In a preferred case, the write control line may be an n +1 th row of gate lines, so that the existing gate lines may be used for write control, and the number of control lines is reduced, so that a write control circuit for providing a write control signal to the write control line is not required, which is advantageous for achieving a high PPI (pixel count Per Inch).

When n is larger than 1, the initial control line is the (n-1) th row of grid lines; alternatively, when n is equal to 1, the initial control line is a start signal line.

Specifically, the first light emitting element may be a first organic light emitting diode, and the second light emitting element may be a second organic light emitting diode;

the driving circuit may include a driving transistor, a gate of the driving transistor being a control terminal of the driving circuit, a first terminal of the driving transistor being a first terminal of the driving circuit, and a second terminal of the driving transistor being a second terminal of the driving circuit;

the initialization circuit may include an initialization transistor, a gate of the initialization transistor being connected to the initialization control line, a first pole of the initialization transistor being connected to the driving node, a second pole of the initialization transistor being connected to the initialization voltage terminal;

the tank circuit may include a storage capacitor, a first terminal of the storage capacitor being connected to the driving node, and a second terminal of the storage capacitor being connected to the data writing node.

In particular implementations, the compensation control circuit may include a first compensation control transistor and a second compensation control transistor, wherein,

Specifically, the first light emission control circuit may include a first light emission control transistor, a gate of the first light emission control transistor is connected to the first light emission control line, a first pole of the first light emission control transistor is connected to the second terminal of the driving circuit, and a second pole of the first light emission control transistor is connected to the first light emitting element;

The pixel cell of the present invention is described below with reference to an embodiment.

As shown in fig. 3, the first embodiment of the pixel unit according to the present invention includes a first organic light emitting diode OLED1, a second organic light emitting diode OLED2, a driving circuit, an initial circuit, a tank circuit, a compensation control circuit, a data writing circuit, a first light emitting control circuit, and a second light emitting control circuit, wherein,

the driving circuit includes a driving transistor T3, the initial circuit includes an initial transistor T1, the tank circuit includes a storage capacitor Cst, the compensation control circuit includes a first compensation control transistor T2 and a second compensation control transistor T4, the data writing circuit includes a data writing transistor T5, the first light emission control circuit includes a first light emission control transistor T6, and the second light emission control circuit includes a second light emission control transistor T7;

a gate of T3 is connected to the driving node a, and a source of T3 is connected to a high voltage input terminal ELVDD for inputting a high voltage Vdd;

the grid electrode of the T2 is connected with the grid line Gate (n) of the nth row, the source electrode of the T2 is connected with the driving node a, and the drain electrode of the T2 is connected with the drain electrode of the T3;

the Gate of T4 is connected with Gate (n), the source of T4 is connected with the Data writing node b, and the drain of T4 is connected with Data line Data;

a first terminal of Cst is connected to the driving node a, and a second terminal of Cst is connected to the data writing node b;

the grid electrode of the T1 is connected with an initial control line Gate (n-1), the source electrode of the T1 is connected with the driving node a, and the drain electrode of the T1 is connected with an initial voltage Vinit;

a gate of T5 is connected to a write control line EMn, a source of T5 is connected to a high voltage input terminal ELVDD, and a drain of T5 is connected to the data write node b;

a gate of the T6 is connected to the first emission control line EM (n _1), a source of the T6 is connected to the source of the T3, and a drain of the T6 is connected to the anode of the OLED 1; the cathode of the OLED1 is connected to a low voltage input terminal ELVSS for inputting low voltage Vss;

a gate of the T7 is connected to the second emission control line EM (n _2), a source of the T7 is connected to the source of the T3, and a drain of the T7 is connected to the anode of the OLED 2; the cathode of the OLED2 is connected to a low voltage input terminal ELVSS for inputting low voltage Vss;

n is a positive integer.

In the first embodiment of the pixel unit shown in fig. 3, all the transistors are p-type transistors, but not limited thereto; in actual operation, the transistor may be replaced with an n-type transistor as described above.

As shown in fig. 2, when the first embodiment of the pixel unit shown in fig. 3 of the present invention is operated, one display period includes a first display sub-period Subframe1 and a second display sub-period Subframe2 which are sequentially arranged, the first display sub-period Subframe1 includes a first initial stage t1, a first compensation stage t2, a first data writing stage t3 and a first light-emitting stage t4 which are sequentially arranged, the second display sub-period Subframe2 includes a second initial stage t5, a second compensation stage t6, a second data writing stage t7 and a second light-emitting stage t8 which are sequentially arranged,

in the first initial stage T1, Gate (n), EMn, EM (n _1) and EM (n _2) all output high level, Gate (n-1) outputs low level, T1 is turned on, and the potential of the driving node a is reset to Vinit;

in the first compensation phase T2, Data outputs Data voltage Vdata, Gate (n-1), EMn, EM (n _1) and EM (n _2) output high level, Gate (n) outputs low level, T2 and T4 are both turned on to write Vdata into Data writing node b, and the Gate of T3 is connected to the drain of T3, T3 is turned on, and the potential of the driving node a is Vdd + Vth; vth is a threshold voltage of T3;

in the first data write phase T3, EMn outputs a low level, gates (n-1), Gate (n), EM (n _1), and EM (n _2) outputs a high level, and T5 is turned on to write Vdd to the data write node b, so that the potential of the driving node a becomes 2Vdd + Vth-Vdata;

in the first lighting period T4, EM (n _1) and EMn output low level, Gate (n-1), Gate (n) and EM (n _2) all output high level, T5 is turned on, T3 and T6 are turned on to drive OLED1 to emit light, and OLED2 does not emit light;

in the second initial stage T5, Gate (n), EMn, EM (n _1) and EM (n _2) all output high level, Gate (n-1) outputs low level, T1 is turned on, and the potential of the driving node a is reset to Vinit;

in the second compensation phase T6, Data outputs Data voltage Vdata, Gate (n-1), EMn, EM (n _1) and EM (n _2) output high level, Gate (n) outputs low level, T2 and T4 are both turned on to write Vdata into Data writing node b, and the Gate of T3 is connected to the drain of T3, T3 is turned on, and the potential of the driving node a is Vdd + Vth; vth is a threshold voltage of T3;

in the second data writing phase T7, EMn outputs a low level, gates (n-1), Gate (n), EM (n _1), and EM (n _2) outputs a high level, and T5 is turned on to write Vdd to the data writing node b, so that the potential of the driving node a becomes 2Vdd + Vth-Vdata;

in the second light emitting period T8, EM (n _2) and EMn output low level, Gate (n-1), Gate (n) and EM (n _1) all output high level, T5 is turned on, T3 and T7 are turned on to drive OLED2 to emit light, and OLED1 does not emit light.

As shown in fig. 4, a second embodiment of the pixel unit according to the present invention includes a first organic light emitting diode OLED1, a second organic light emitting diode OLED2, a driving circuit, an initial circuit, a tank circuit, a compensation control circuit, a data writing circuit, a first light emitting control circuit, and a second light emitting control circuit, wherein,

the Gate of T5 is connected to the Gate line Gate (n +1) of the (n +1) th row, the source of T5 is connected to the high voltage input terminal ELVDD, and the drain of T5 is connected to the data write node b;

n is a positive integer.

In the second embodiment of the pixel unit shown in fig. 4, all the transistors are p-type transistors, but not limited thereto; in actual operation, the transistor may be replaced with an n-type transistor as described above.

The second embodiment of the pixel cell of the present invention as shown in fig. 4 differs from the first embodiment of the pixel cell of the present invention as shown in fig. 3 only in that: the Gate of T5 is connected to Gate (n +1), so that EMn is not required, and a write control circuit for supplying a write control signal to a write control line is not required, which is advantageous for realizing high PPI (pixel Per Inch, number of Pixels).

As shown in fig. 5, when the second embodiment of the pixel unit shown in fig. 4 of the present invention is operated, one display period includes a first display sub-period Subframe1 and a second display sub-period Subframe2 which are sequentially arranged, the first display sub-period Subframe1 includes a first initial stage t1, a first compensation stage t2, a first data writing stage t3 and a first light-emitting stage t4 which are sequentially arranged, the second display sub-period Subframe2 includes a second initial stage t5, a second compensation stage t6, a second data writing stage t7 and a second light-emitting stage t8 which are sequentially arranged,

in the first initial stage T1, Gate (n), Gate (n +1), EM (n _1) and EM (n _2) all output high level, Gate (n-1) outputs low level, T1 is turned on, resetting the potential of the driving node a to Vinit;

in the first compensation phase T2, Data outputs Data voltage Vdata, and Gate (n-1), Gate (n +1), EM (n _1) and EM (n _2) output high level, Gate (n) outputs low level, T2 and T4 are both turned on to write Vdata into node b, and make the Gate of T3 connected to the drain of T3, T3 is turned on, at which time the potential of the driving node a is Vdd + Vth; vth is a threshold voltage of T3;

in the first data write phase T3, Gate (n +1) outputs a low level, Gate (n-1), Gate (n), EM (n _1) and EM (n _2) outputs a high level, and T5 is turned on to write Vdd to the data write node b, so that the potential of the driving node a becomes 2Vdd + Vth-Vdata;

in the first light emitting period T4, EM (n _1) outputs low level, Gate (n-1), Gate (n +1) and EM (n _2) all output high level, T5 is turned on, T3 and T6 are turned on to drive OLED1 to emit light, and OLED2 does not emit light;

in the second initial stage T5, Gate (n), Gate (n +1), EM (n _1) and EM (n _2) all output high level, Gate (n-1) outputs low level, T1 is turned on, and the potential of the driving node a is reset to Vinit;

in the second compensation phase T6, Data outputs Data voltage Vdata, Gate (n-1), Gate (n +1), EM (n _1) and EM (n _2) output high level, Gate (n) outputs low level, T2 and T4 are both turned on to write Vdata into node b, and the Gate of T3 is connected to the drain of T3, T3 is turned on, and the potential of the driving node a is Vdd + Vth; vth is a threshold voltage of T3;

in the second data writing phase T7, Gate (n +1) outputs a low level, Gate (n-1), Gate (n), EM (n _1) and EM (n _2) outputs a high level, T5 is turned on to write Vdd to the data writing node b, so that the potential of the driving node a becomes 2Vdd + Vth-Vdata;

in the second light emitting period T8, EM (n _2) outputs low level, Gate (n-1), Gate (n +1) and EM (n _1) all output high level, T5 is turned on, T3 and T7 are turned on to drive OLED2 to emit light, and OLED1 does not emit light.

The pixel driving method according to an embodiment of the present invention is applied to the pixel unit, where a display period includes a first display sub-period and a second display sub-period that are sequentially arranged, the first display sub-period includes a first initial stage, a first compensation stage, a first data writing stage, and a first light emitting stage that are sequentially arranged, and the second display sub-period includes a second initial stage, a second compensation stage, a second data writing stage, and a second light emitting stage that are sequentially arranged, and the pixel driving method includes:

The pixel unit to which the pixel driving method provided by the embodiment of the invention is applied comprises two light emitting elements, and the pixel driving method provided by the embodiment of the invention drives the two light emitting elements to emit light in a time-sharing manner, so that the pixel unit can be simplified from a 12T2C structure to a 7T1C structure, and high PPI is realized.

Specifically, the pixel driving method of the present invention further includes:

controlling the potential of the driving node to become V1+ V2-Vdata + Vth during the first data writing phase and the second data writing phase, so that the gate-source voltage of the driving transistor can compensate the threshold voltage of the driving transistor during the light emitting phase.

The pixel module provided by the embodiment of the invention comprises two pixel units;

n and m are both positive integers.

In practical implementation, the pixel module according to the embodiment of the present invention includes two pixel units according to the embodiment of the present invention, a first pixel unit includes a 2n-1 th row and an m-th column of light emitting elements, a second pixel unit includes a 2n +1 th row and an m-th column of light emitting elements, the first pixel unit is respectively connected to a 2n-1 th row of light emitting control line EM (2n-1) and a2 n-2 th row of light emitting control line EM (2n) and the second pixel unit is also respectively connected to a 2n-1 th row of light emitting control line EM (2n-1) and a2 n-2 nd row of light emitting control line EM (2n),

the light emitting element in the mth column in the 2n-1 th row and the light emitting element in the mth column in the 2n-1 th row share the first pixel driving unit included in the first pixel unit, the light emitting element in the mth column in the 2n +1 th row and the light emitting element in the mth column in the 2n +2 th row share the second pixel driving unit included in the unit of the second pixel, and two pixel units in the same column in adjacent rows share two light emitting control lines: a 2n-1 th row emission control line and a 2n th row emission control line.

In a specific implementation, the first pixel unit may be an nth-stage mth-column pixel unit, and the second pixel unit may be an n + 1-stage mth-column pixel unit.

Preferably, the nth writing control line is a (n +1) th row of gate lines, and the (n +1) th row of writing control lines is a (n +2) th row of gate lines.

Specifically, n is equal to 1, the nth initial control line is a starting signal line, and the (n +1) th initial control line is an nth row of gate lines; or n is larger than 1, the nth initial control line is the (n-1) th grid line, and the (n +1) th initial control line is the nth grid line.

As shown in fig. 6, the first pixel cell Pixeln, m is connected to the 2n-1 th row emission control line EM (2n-1) and the 2n th row emission control line EM (2n), respectively, and the second pixel cell Pixeln +1, m is connected to the 2n-1 th row emission control line EM (2n-1) and the 2n th row emission control line EM (2n), respectively;

the first pixel unit pixel, m is connected with the Gate line Gate (n) of the nth row;

the second pixel unit Pixeln +1, m is connected to the Gate line Gate (n +1) of the (n +1) th row;

the first Pixel cell Pixel, m is connected to an nth write control line EMn, and the second Pixel cell Pixel1, m is connected to an n +1 th write control line EMn + 1.

When the pixel module of the embodiment of the invention works, a display period includes a first display sub-period and a second display sub-period which are sequentially arranged, the first display sub-period includes a first initial stage, a first compensation stage, a first data writing stage, a second data writing stage and a first light-emitting stage which are sequentially arranged, the second display sub-period includes a second initial stage, a second compensation stage, a third data writing stage, a fourth data writing stage and a second light-emitting stage which are sequentially arranged,

in the second light-emitting stage, the first driving circuit is controlled by the first driving node to conduct the connection between the first voltage end and the second end of the first driving circuit, the fourth light-emitting control circuit is controlled by the 2 nth row light-emitting control line to conduct the connection between the second end of the first driving circuit and the 2 nth row and mth column light-emitting element, and the first driving circuit drives the 2 nth row and mth column light-emitting element to emit light; the second driving circuit is controlled by the second driving node to conduct the connection between the first voltage end and the second end of the second driving circuit, the fourth light-emitting control circuit is controlled by the 2 nth row light-emitting control line to conduct the connection between the second end of the second driving circuit and the 2n +2 th row mth column light-emitting element, and the second driving circuit drives the 2n +2 nd row mth column light-emitting element to emit light.

The pixel module according to the present invention is described below with reference to an embodiment.

One embodiment of the pixel module of the present invention includes a first pixel unit and a second pixel unit;

as shown in fig. 7, the first pixel unit includes an mth column organic light emitting diode OLED2n-1 of row 2n-1, an mth column organic light emitting diode OLED2n of row 2 nth, a first driving circuit, a first initialization circuit, a first tank circuit, a first compensation control circuit, a first data writing circuit, a first light emitting control circuit, and a second light emitting control circuit, wherein,

the first driving circuit includes a first driving transistor T3, the first initialization circuit includes a first initialization transistor T1, the first tank circuit includes a first storage capacitor Cst1, the first compensation control circuit includes a first compensation control transistor T2 and a second compensation control transistor T4, the first data write circuit includes a first data write transistor T5, the first light emission control circuit includes a first light emission control transistor T6, the second light emission control circuit includes a second light emission control transistor T7;

a gate of T3 is connected to the first driving node a1, and a source of T3 is connected to a high voltage input terminal ELVDD for inputting a high voltage Vdd;

the Gate of the T2 is connected to the Gate line Gate (n) of the nth row, the source of the T2 is connected to the first driving node a1, and the drain of the T2 is connected to the drain of the T3;

a Gate of the T4 is connected to a Gate (n), a source of the T4 is connected to the first Data writing node b1, and a drain of the T4 is connected to the nth Data line Data (n);

a first terminal of Cst1 is connected to the first driving node a1, and a second terminal of Cst1 is connected to the first data writing node b 1;

the Gate of the T1 is connected with the nth initial control line Gate (n-1), the source of the T1 is connected with the first driving node a1, and the drain of the T1 is connected with the initial voltage Vinit;

the Gate of T5 is connected to the Gate line Gate (n +1) of the (n +1) th row, the source of T5 is connected to the high voltage input terminal ELVDD, and the drain of T5 is connected to the first data write node b 1;

the grid electrode of the T6 is connected with a 2n-1 row light-emitting control line EM (2n-1), the source electrode of the T6 is connected with the source electrode of the T3, and the drain electrode of the T6 is connected with the anode electrode of the OLED2n-1, m; the cathode of the OLED2n-1, m is connected to a low voltage input terminal ELVSS for inputting low voltage Vss;

the gate of T7 is connected to the emission control line EM (2n) of row 2n, the source of T7 is connected to the source of T3, the drain of T7 is connected to the anode of OLED2n, m; the cathode of the OLED2n, m is connected to a low voltage input terminal ELVSS for inputting a low voltage Vss;

the second pixel unit includes a 2n +1 th row and a mth column of organic light emitting diodes OLED2n +1, m, a 2n +2 nd row and a mth column of organic light emitting diodes OLED2n +2, m, a second driving circuit, a second initial circuit, a second tank circuit, a second compensation control circuit, a second data writing circuit, a third light emission control circuit, and a fourth light emission control circuit,

the second driving circuit includes a second driving transistor T2-3, the second initialization circuit includes a second initialization transistor T2-1, the second tank circuit includes a second storage capacitor Cst2, the second compensation control circuit includes a third compensation control transistor T2-2 and a fourth compensation control transistor T2-4, the second data writing circuit includes a second data writing transistor T2-5, the third emission control circuit includes a third emission control transistor T2-6, and the fourth emission control circuit includes a fourth emission control transistor T2-7;

the gate of T2-3 is connected to the second driving node a2, and the source of T2-3 is connected to the high voltage input terminal ELVDD for inputting the high voltage Vdd;

the grid electrode of the T2-2 is connected with the grid line Gate (n +1) of the (n +1) th row, the source electrode of the T2-2 is connected with the second driving node a2, and the drain electrode of the T2-2 is connected with the drain electrode of the T2-3;

the Gate of T2-4 is connected to Gate (n +1), the source of T2-4 is connected to the second Data write node b2, and the drain of T2-4 is connected to the n +1 th Data line Data (n + 1);

a first terminal of Cst2 is connected to the second driving node a2, and a second terminal of Cst2 is connected to the second data writing node b 2;

the grid electrode of the T2-1 is connected with the Gate line Gate (n) of the nth row, the source electrode of the T2-1 is connected with the second driving node a2, and the drain electrode of the T2-1 is connected with an initial voltage Vinit;

the nth row of grid lines Gate (n) is an n +1 th initial control line;

the Gate of T2-5 is connected to the Gate line Gate (n +2) of the (n +2) th row, the source of T2-5 is connected to the high voltage input terminal ELVDD, and the drain of T2-5 is connected to the second data write node b 2;

the grid electrode of the T2-6 is connected with the light-emitting control line EM (2n-1) of the 2n-1 th row, the source electrode of the T2-6 is connected with the source electrode of the T2-3, and the drain electrode of the T2-6 is connected with the anode electrode of the OLED2n +1, m; the cathode of the OLED2n +1, m is connected to a low voltage input terminal ELVSS for inputting low voltage Vss;

the grid electrode of the T2-7 is connected with the light-emitting control line EM (2n) of the 2n th row, the source electrode of the T2-7 is connected with the source electrode of the T2-3, and the drain electrode of the T2-7 is connected with the anode electrode of the OLED2n +2, m; the cathode of the OLED2n +2, m is connected to a low voltage input terminal ELVSS for inputting the low voltage Vss.

In the embodiment of the pixel module shown in fig. 7, all the transistors are p-type transistors, but not limited thereto.

As shown in fig. 8, when the pixel module shown in fig. 7 according to the embodiment of the present invention is in operation, the first display period Subframe includes a first display Subframe sub 1 and a second display Subframe subframer 2, which are sequentially arranged, the first display Subframe subframer 1 includes a first initial phase t11, a first compensation phase t12, a first data writing phase t13, a second data writing phase t14 and a first light-emitting phase t15, which are sequentially arranged, and the second display Subframe includes a second initial phase t21, a second compensation phase t22, a third data writing phase t23, a fourth data writing phase t24 and a second light-emitting phase t25, which are sequentially arranged;

in the first initial stage T11, the initial voltage terminal outputs the initial voltage Vinit, the Gate (n-1) outputs a low level, and T1 is turned on to write Vinit into the first driving node a 1;

in the first compensation phase T12, Data (n) outputs a first Data voltage Vdata1, Gate (n) outputs a low level, T2 and T4 are both turned on to write Vdata1 into the first Data write node b1, the first driving node a1 is connected to the drain of T3, T3 is turned on, the potential of a1 is Vdd + Vth, and Vth is the threshold voltage of T3; the initial voltage terminal outputs an initial voltage Vinit, and T2-1 is turned on to write Vinit into the second driving node a 2;

in the first data writing phase T13, Gate (n +1) outputs low level, T5 is turned on to write Vdd to the first data writing node b1, so that the potential of the first driving node a1 becomes 2Vdd + Vth-Vdata 1; data (n +1) outputs a second Data voltage Vdata2, and T2-2 and T2-4 are all turned on to write Vdata2 into a second Data write node b2, a second driving node a2 is connected with the drain of T2-3, and T2-3 is turned on, when the potential of a2 is Vdd + Vth2, and Vth2 is the threshold voltage of T2-3;

in the second data writing phase T14, Gate (n +2) outputs low level, T2-5 is turned on to write Vdd into the second data writing node b2, so that the potential of the second driving node a2 becomes 2Vdd + Vth2-Vdata 2;

in the first lighting period T15, EM (2n-1) outputs low level, EM (2n) outputs high level, T3 and T6 are both turned on to drive OLED2n-1, m to emit light, T2-3 and T2-6 are both turned on to drive OLED2n +1, m to emit light;

in the second initial stage T21, the initial voltage terminal outputs the initial voltage Vinit, the Gate (n-1) outputs a low level, and T1 is turned on to write Vinit into the first driving node a 1;

in the second compensation phase T22, Data (n) outputs a third Data voltage Vdata3, Gate (n) outputs a low level, T2 and T4 are turned on to write Vdata3 into the first Data write node b1, the first driving node a1 is connected to the drain of T3, and T3 is turned on, where the potential of a1 is Vdd + Vth and Vth is the threshold voltage of T3; the initial voltage terminal outputs an initial voltage Vinit, and T2-1 is turned on to write Vinit into the second driving node a 2;

in the third data writing phase T23, Gate (n +1) outputs low level, T5 is turned on to write Vdd to the first data writing node b1, so that the potential of the first driving node a1 becomes 2Vdd + Vth-Vdata 3; data (n +1) outputs a fourth Data voltage Vdata4, both T2-2 and T2-4 are turned on to write Vdata4 into a second Data write node b2, a second driving node a2 is connected with the drain of T2-3, and T2-3 is turned on, when the potential of a2 is Vdd + Vth2 and Vth2 is the threshold voltage of T2-3;

in the fourth data writing phase T24, Gate (n +2) outputs low level, T2-5 is turned on to write Vdd to the second data writing node b2, so that the potential of the second driving node a2 becomes 2Vdd + Vth2 Vdata 4;

in the second lighting period T12, EM (2n) outputs low level, EM (2n-1) outputs high level, T3 and T7 are both turned on to drive OLED2n, m to emit light, and T2-3 and T2-7 are both turned on to drive OLED2n +2, m to emit light.

The pixel driving method according to the embodiment of the present invention is applied to the pixel module, a display period includes a first display sub-period and a second display sub-period, which are sequentially set, the first display sub-period includes a first initial stage, a first compensation stage, a first data writing stage, a second data writing stage and a first light emitting stage, which are sequentially set, the second display sub-period includes a second initial stage, a second compensation stage, a third data writing stage, a fourth data writing stage and a second light emitting stage, which are sequentially set, and the pixel driving method includes:

m is a positive integer.

The display device comprises N levels and M rows of the pixel modules, wherein N and M are positive integers.

Specifically, the first pixel unit included in the nth-stage mth-column pixel module includes a 2n-1 th row and mth column light-emitting element and a 2n th row and mth column light-emitting element; n and m are both positive integers;

When the display device according to the embodiment of the present invention operates, the light emitting elements in the odd-numbered rows emit light in the first half of one frame display time, and the light emitting elements in the even-numbered rows emit light in the second half of one frame display time.

Preferably, the nth write control line is an n +1 th row of gate lines, and the n +1 th write control line is an n +2 th row of gate lines, so that the existing gate lines can be used for write control, the number of control lines is reduced, a write control circuit for providing a write control signal for the write control lines is not required, and high PPI (pixel Per Inch, number of Pixels Per Inch) is favorably realized.

The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A pixel cell comprising a first light emitting element and a second light emitting element, the pixel cell further comprising:

the second light-emitting control circuit is respectively connected with the second end of the driving circuit, a second light-emitting control line and a second light-emitting element and is used for controlling the connection between the second end of the driving circuit and the second light-emitting element to be switched on or switched off under the control of the second light-emitting control line;

the initial circuit is specifically configured to, in an initial stage, control writing of the initial voltage into the driving node, so that the driving circuit can turn on a connection between the first voltage terminal and the second terminal of the driving circuit at a start of a compensation stage set after the initial stage;

the writing control line is an n +1 th row of grid lines;

2. The pixel cell of claim 1, wherein the first light emitting element is a first organic light emitting diode and the second light emitting element is a second organic light emitting diode;

3. The pixel cell of claim 1, wherein the compensation control circuit comprises a first compensation control transistor and a second compensation control transistor, wherein,

4. The pixel unit according to claim 1, wherein the first light emission control circuit includes a first light emission control transistor, a gate of the first light emission control transistor is connected to the first light emission control line, a first pole of the first light emission control transistor is connected to the second terminal of the drive circuit, and a second pole of the first light emission control transistor is connected to the first light emitting element;

5. A pixel driving method applied to the pixel unit according to any one of claims 1 to 4, wherein a display period includes a first display sub-period and a second display sub-period, which are sequentially arranged, the first display sub-period includes a first initial phase, a first compensation phase, a first data writing phase and a first light emitting phase, which are sequentially arranged, the second display sub-period includes a second initial phase, a second compensation phase, a second data writing phase and a second light emitting phase, which are sequentially arranged, the pixel driving method includes:

in the first initial stage and the second initial stage, an initial voltage end outputs an initial voltage, and an initial circuit controls to write the initial voltage into a driving node under the control of an initial control line, so that the driving circuit can conduct the connection between the first voltage end and the second end of the driving circuit at the beginning of a first compensation stage and at the beginning of a second compensation stage;

6. The pixel driving method according to claim 5, further comprising:

7. A pixel module comprising two pixel cells according to any one of claims 1 to 4;

n and m are both positive integers.

8. The pixel module of claim 7, wherein the nth write control line is an n +1 th row of gate lines, and the n +1 th row of write control lines is an n +2 th row of gate lines;

9. A pixel driving method applied to the pixel module as claimed in claim 7 or 8, wherein a first pixel unit in the pixel module includes a first driving circuit, a second pixel unit in the pixel module includes a second driving circuit, a display period includes a first display sub-period and a second display sub-period which are sequentially arranged, the first display sub-period includes a first initial stage, a first compensation stage, a first data writing stage, a second data writing stage and a first light emitting stage which are sequentially arranged, the second display sub-period includes a second initial stage, a second compensation stage, a third data writing stage, a fourth data writing stage and a second light emitting stage which are sequentially arranged, and the pixel driving method includes:

in a first initial stage and a second initial stage, an initial voltage end outputs an initial voltage, and a first initial circuit controls to write the initial voltage into a first driving node under the control of an nth initial control line; n is a positive integer; the first driving node is a driving node in the first pixel unit, so that at the beginning of a first compensation phase and at the beginning of a second compensation phase, the first driving circuit can conduct the connection between the first voltage end and the second end of the first driving circuit, and the second driving circuit can conduct the connection between the first voltage end and the second end of the second driving circuit;

m is a positive integer.

10. A display device comprising N stages and M columns of the pixel module according to claim 7 or 8, N and M being positive integers.

11. The display device according to claim 10, wherein the nth stage mth column pixel module comprises a first pixel unit including a 2n-1 th row mth column light emitting element and a 2n th row mth column light emitting element; n and m are both positive integers;

12. The display device according to claim 11, wherein the nth write control line is an n +1 th row of gate lines, and the n +1 th write control line is an n +2 th row of gate lines;