CN108984458B - Self-defined serial open type bus - Google Patents
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- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The invention provides a serial open bus of a self-customized bus architecture, which relates to bus design, and is used for finishing the communication between a main control module and each functional module, and comprises the following components: the reset bus is used for sending a uniform instruction to each module so that all the modules can be restored to the initial state value at the same time; the power supply bus is connected with the power supply and is used for providing required voltage for each module; the network bus is used for providing network connection for each module and independently debugging a certain module; and the custom bus is used for adding the corresponding functional bus according to the requirement. The invention can use embedded technology and computer technology as core, and uses DSP, ARM, single chip and FPGA and other high performance devices to construct custom bus, which has higher autonomy, each module can customize bus structure according to specific military test requirement, saves resources, can pass environmental test, and can improve the localization rate of equipment.
Description
Technical Field
The invention relates to bus design, in particular to a self-defined serial open type bus.
Background
Since the 20 th century and 50 th century, the U.S. developed test equipment for military electronic equipment, the variety of the equipment was increasing, and the related research work also received more and more attention. With the improvement of tactical performance and internal structure complexity of weaponry, the requirements of the weaponry on matched test equipment in the research, development, production and use processes are higher and higher. From the middle of the 70 s, China develops research work of automatic test equipment for missiles, and after decades of exploration and practice, the missiles are successively developed and provided with a plurality of sets of missile comprehensive test equipment for troops. At present, missile testing equipment is mostly realized by VXI, PXI or LXI buses, wherein the VXI bus is mostly used. However, although the test equipment developed based on the VXI bus has a strong test function, a high data throughput, and a high degree of system integration, there are still problems of a large volume, a heavy weight, and a poor mobility, and at present, the domestic test equipment categories can be classified into the following categories.
The PXI (PCI Extensions for instrumentation) bus is an instrumentation bus specification with open and modular features proposed by NI corporation in 1997. It combines the electrical characteristics of the PCI bus, the ruggedness of Compact PCI, and the mechanical packaging characteristics of Eurocard into one, and develops mechanical, electrical, and software specifications suitable for testing, measurement, and data acquisition applications. Compared with the bus transmission rate of VXI bus 40MB/s, PXI is based on mature PCI bus technology, the bus transmission rate is 132MB/s or 264MB/s, the size is smaller, the cost performance is better, and at present, many companies in China successively put forward self-developed portable test equipment based on the PXI bus. The typical ones are PS-360 and PXIS-2690P, which are portable devices proposed by Beijing Panhua measurement and control and the Linghuake technology. On one hand, however, the PXI case which can meet the requirement of the field severe environment and has better performance is less; on the other hand, compared with the VXI bus, the PXI bus standard lacks the general participation of manufacturers in the instrument field, and the coverage area of the existing PXI module is relatively narrow, so that the extensive application of the PXI bus in military missile testing equipment is needed to be continued to be earnestly awaited.
The LXI (LAN Extensions for instrumentation) bus is a new generation of instrument platform which is jointly promoted by Agilent company and VXI technology company in 9 months 2004, is based on the Ethernet technology and consists of various small and medium-sized bus modules. The LXI standard not only has the characteristics of small size of a PXI card instrument, high performance of a GPIB instrument, high-speed LAN data throughput and the like, but also meets the requirements of the instrument on indexes such as timing, triggering and electromagnetic compatibility. Since LXI uses Ethernet (IEEE-802.3) as a data transmission medium, and standard software can be used without using a chassis and expensive cables, LXI improves system speed and software versatility while trying to reduce system size and system setup time, and provides great convenience for users to create and reconfigure test devices quickly, economically, and efficiently. However, most of the applications of the LXI bus are focused on distributed test sites, and the LXI bus has not been well applied to highly integrated portable devices despite its promising development.
Although the VXI, PXI, LXI buses and the like have strong test functions and instrument standard support, the VXI, PXI, LXI buses and the like are all in a commercial bus form, and resource allocation and management kernels are relatively closed and cannot be completely opened to users, so that the VXI, PXI, LXI buses and the like are not beneficial to fault location and analysis occasions of military base-level military equipment of troops. On the other hand, because the missile is relatively low in test depth at the base level of the army and the limit of a test process is less, the requirement on a standard instrument is relatively low; the remaining resources of standard instruments may affect the portability and maneuverability of the device.
Disclosure of Invention
In view of the above disadvantages, the present invention provides a serial open bus with a self-customized bus architecture.
The invention discloses a self-defined serial open bus, which is used for finishing the communication between a main control module and each functional module, and comprises: the system comprises a reset bus, a power supply bus, a network bus and one or more custom buses;
the reset bus is used for sending a uniform instruction to each module so that all the modules can be restored to the initial state value at the same time;
the power supply bus is connected with the power supply and is used for providing required voltage for each module;
the network bus is used for providing network connection for each module and independently debugging a certain module;
and the custom bus is used for adding the corresponding functional bus according to the requirement.
Preferably, the custom bus comprises:
the RS-485 bus is used as a local bus and used for transmitting commands and action signals between each function module and the main control module;
the M-LVDS bus is used for high-speed transmission of data among the modules;
and the hard trigger wire is used for adopting a hard trigger mechanism to improve the real-time property of communication.
Preferably, the RS-485 bus includes two RS-485 communication interfaces, one of which is used for transmitting the internal commands of the main control module and each functional module to implement scheduling of each module, and the other is used for returning the test data to implement processing, calculation and analysis of the test data by the main control module.
Preferably, the power supply bus provides the following voltages: +15V, -15V, 5V, 27V and 56V.
Preferably, the network bus further comprises a switch, which is implemented by using a chip IP178CH and a chip 20PT 1024X;
chip IP178CH for providing network connectivity of the remote computer to the embedded computer and the various modules;
and the chip 20PT1024X is used for performing voltage transformation and isolation on the IP178CH chip output differential voltage, so that network connection among different modules is facilitated.
Preferably, the open bus further comprises a time signal bus for enabling each module to have a unified clock for time unification and timing functions.
Preferably, the M-LVDS bus uses a DS91C176 chip to implement data driving reception.
The features mentioned above can be combined in various suitable ways or replaced by equivalent features as long as the object of the invention is achieved.
The invention has the advantages that the invention can use embedded technology and computer technology as the core, and uses high-performance devices such as DSP, ARM, single chip microcomputer and FPGA to construct the self-defined bus, which has higher autonomy, and each module can self-customize the bus architecture according to the specific military test requirement, thereby saving resources, passing the environmental test and simultaneously improving the localization rate of the equipment.
Drawings
Fig. 1 is a schematic diagram of a custom serial open bus according to an embodiment of the present invention.
FIG. 2 is a schematic diagram of an 8-port switch mode;
FIG. 3 is a schematic diagram of the output interface of the chip IP178 CH;
fig. 4 is an internal structure diagram of the chip 20PT 1024X.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
The present embodiment is described with reference to fig. 1, and the present embodiment describes a custom serial open bus, where the open bus of the present embodiment is used to complete communication between a master control module and each functional module, and the master control module of the present embodiment
The open bus of the present embodiment includes: the system comprises a reset bus, a power supply bus, a network bus and one or more custom buses;
the reset bus is used for sending a uniform instruction to each module to enable all the modules to be restored to initial state values at the same time, and the modules have extremely small reset time delay;
the power supply bus is connected with the power supply and is used for providing required voltage for each module; therefore, the power supply modules can provide all power supply voltages on the power supply bus, the power supply bus and each module are directly connected, each unit module has the same power supply and is actually distributed to different required voltages on different modules, the different voltages are converted through the power supply voltage conversion devices on the modules, and the power supply bus provides +15V, -15V, 5V, 27V and 56V.
The network bus is used for providing network connection for each module and independently debugging a certain module;
and the custom bus is used for adding the corresponding functional bus according to the requirement.
The self-defined bus is not fixed in composition, and other buses can be added according to the test requirement. Therefore, the bus of the embodiment is open, which provides convenience for the later function expansion of users.
In a preferred embodiment, the custom bus of this embodiment includes an RS-485 bus, an M-LVDS bus, and a hard trigger line; the RS-485 bus is used as a local bus and used for transmitting commands and action signals between each function module and the main control module;
the RS-485 bus of the embodiment uses IL485 as a level conversion chip, an HDLC protocol, the transmission rate is set to be 2Mb/s, 4 frame heads and 4 frame tails, and 6-wire system is adopted, namely data positive, data negative, clock positive, clock negative, communication control positive and communication control negative. The M-LVDS bus is used for high-speed transmission of data among the modules;
this embodiment uses a DS91C176 data-driven receiving chip that can drive up to 32 loads at clock frequencies up to 100MHz and data transfer rates up to 200 Mb/s. Also using the 6 wire, HDLC protocol, the transmission rate is set to 40 Mb/s.
And the hard trigger wire is used for adopting a hard trigger mechanism to improve the real-time property of communication. Aiming at some applications with higher real-time requirements, a hard-wire trigger mechanism is added into the open bus. The mode of requesting the cooperative work of other unit modules by adopting data communication obviously cannot meet the occasion with higher requirement on real-time performance. In the present embodiment, a total of 16 hard trigger lines are set, and these 16 hard trigger lines are used to cope with an application requiring high real-time performance.
In a preferred embodiment, the RS-485 bus includes two RS-485 communication interfaces, one of which is used for transmitting the internal commands of the main control module and each functional module to implement scheduling of each module, and the other is used for returning the test data to implement processing, calculation and analysis of the test data by the main control module.
In a preferred embodiment, the network bus of this embodiment further includes a switch, which is implemented by using a chip IP178CH and a chip 20PT 1024X;
chip IP178CH for providing network connectivity of the remote computer to the embedded computer and the various modules;
and the chip 20PT1024X is used for performing voltage transformation and isolation on the IP178CH chip output differential voltage, so that network connection among different modules is facilitated.
The network bus is used as an exclusive bus, and a switch needs to be designed to forward remote data. The switch module is directly integrated on the back board, the used switch chip is IP178CH, and the functional characteristics are as follows:
1) supporting the functional configuration of a router and a switch;
2) MAC addresses of 1K are supported;
3) supporting automatic negotiation of a working mode and automatic port turning;
4) and supporting an external configuration chip to perform function configuration.
There are three ways to configure and control the functions of the chip IP178 CH: configuring the level of a chip pin through a pull-up resistor or a pull-down resistor; through the MII/RMII interface, the external processor accesses the MII register by using an SMI interface to control and manage the chip; by configuring the chip EEPROM, the chip can automatically read the content of the EEPROM chip when starting up and configure the on-chip register. The switch chip IP178CH is configured as an 8-port switch mode for network connection of remote computers to embedded computers, and individual modules, depending on the actual requirements. For functional expansion, 14-way network connection can be provided through port interconnection using two IP178CH chips. Two of which are used for the connection of the remote computer and the embedded computer, respectively, the 8-port switch mode is shown in fig. 2, and MAC8 is not used. The configuration mode adopts direct configuration of chip pins, and the configuration contents are shown in table 1. The other pins are set to default mode, and the chip can realize the function of the 8-port switch after being powered on.
Table 1 port configuration content
Signals are input and output through a PHY interface of the chip IP178CH, and in order to enable interconnection among different devices, a network transformer is used for differential voltage conversion, and meanwhile, network devices can be isolated. The network transformer chip adopts 20PT1024X, and each transformer supports two-way network transceiving. The two-way design is shown in fig. 3. The IP178CH chip output differential voltage is referenced to AVCC, voltage converted and isolated by network transformer 20PT1024X, the transformer output can be connected directly to RJ45 jack or to other network devices. The internal structure of the network transformer 20PT1024X is shown in fig. 3.
Each single-chip network transformer supports the transceiving of two paths of network signals, supports the standards of IEEE802.3u and ANSI X3.263, supports the automatic port turnover by symmetrical TX and RX interfaces, and meets the requirement of 10/100M Ethernet.
In a preferred embodiment, the open bus further comprises a time signal bus for enabling each module to have a uniform clock for time-uniforming and timing functions.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that features described in different dependent claims and herein may be combined in ways different from those described in the original claims. It is also to be understood that features described in connection with individual embodiments may be used in other described embodiments.
Claims (6)
1. A self-defined serial open bus is characterized in that the open bus is used for finishing communication between a main control module and each functional module, and the open bus comprises: the system comprises a reset bus, a power supply bus, a network bus and one or more custom buses;
the reset bus is used for sending a uniform instruction to each module so that all the modules can be restored to the initial state value at the same time;
the power supply bus is connected with the power supply and is used for providing required voltage for each module;
the network bus is used for providing network connection for each module and independently debugging a certain module;
the user-defined bus is used for adding the corresponding functional bus according to the requirement;
the custom bus comprises:
the RS-485 bus is used as a local bus and used for transmitting commands and action signals between each function module and the main control module;
the M-LVDS bus is used for high-speed transmission of data among the modules;
and the hard trigger wire is used for adopting a hard trigger mechanism to improve the real-time property of communication.
2. The customized serial open bus according to claim 1, wherein the RS-485 bus comprises two RS-485 communication interfaces, one of which is used for transmitting commands inside the main control module and each functional module to realize the scheduling of each module, and the other is used for returning test data to realize the processing, calculation and analysis of the main control module on the test data.
3. The customized serial open bus according to claim 1, wherein the power supply bus provides the following voltages: +15V, -15V, 5V, 27V and 56V.
4. The customized serial open bus according to claim 1, wherein said network bus further comprises a switch, which is implemented by using chip IP178CH and chip 20PT 1024X;
chip IP178CH for providing network connectivity of the remote computer to the embedded computer and the various modules;
and the chip 20PT1024X is used for performing voltage transformation and isolation on the IP178CH chip output differential voltage, so that network connection among different modules is facilitated.
5. The custom serial open bus according to claim 1, wherein said open bus further comprises a clock signal bus for making modules have a unified clock for time unification and timing.
6. The customized serial open bus according to claim 1, wherein the M-LVDS bus employs a DS91C176 chip to implement data driving reception.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1993015459A1 (en) * | 1992-02-03 | 1993-08-05 | Micro Industries | Live insertion of computer modules |
| CN1279429A (en) * | 1999-06-23 | 2001-01-10 | 日本电气株式会社 | Circuits and method for making bus reset reliably and irrelevant to length of cable |
| CN1471007A (en) * | 2002-07-26 | 2004-01-28 | 赫扬科技股份有限公司 | USB direct on-line display switching apparatus and method |
| CN101690019A (en) * | 2007-07-06 | 2010-03-31 | 默勒有限公司 | System and method for controlling bus-networked devices via an open field bus |
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2018
- 2018-08-09 CN CN201810903646.9A patent/CN108984458B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1993015459A1 (en) * | 1992-02-03 | 1993-08-05 | Micro Industries | Live insertion of computer modules |
| CN1279429A (en) * | 1999-06-23 | 2001-01-10 | 日本电气株式会社 | Circuits and method for making bus reset reliably and irrelevant to length of cable |
| CN1471007A (en) * | 2002-07-26 | 2004-01-28 | 赫扬科技股份有限公司 | USB direct on-line display switching apparatus and method |
| CN101690019A (en) * | 2007-07-06 | 2010-03-31 | 默勒有限公司 | System and method for controlling bus-networked devices via an open field bus |
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Denomination of invention: A custom serial open bus Granted publication date: 20211029 Pledgee: Industrial Bank Co.,Ltd. Harbin Branch Pledgor: Harbin nuoxin measurement and Control Technology Co.,Ltd. Registration number: Y2024230000016 |