CN108983659B - Marine power protection device and method based on CPU and FPGA framework - Google Patents
Marine power protection device and method based on CPU and FPGA framework Download PDFInfo
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- CN108983659B CN108983659B CN201810786267.6A CN201810786267A CN108983659B CN 108983659 B CN108983659 B CN 108983659B CN 201810786267 A CN201810786267 A CN 201810786267A CN 108983659 B CN108983659 B CN 108983659B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
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- G—PHYSICS
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- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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Abstract
A marine electric protection device and method based on a CPU and FPGA framework relates to the field of marine steam turbine protection. The invention aims to solve the problem that the operation safety of a marine steam turbine is influenced because an on-road steam turbine protection system is not suitable for protecting the marine steam turbine. Acquiring alarm conditions issued by an engineer station, analyzing by using a TCP/IP protocol, sending an alarm analysis node to a main task CPU through an FPGA, acquiring a digital quantity input signal and a frequency input signal, filtering the acquired signals, sending the signals to the main task CPU as input variable data, and issuing an alarm action to the outside when receiving the alarm signal sent by the main task CPU; the method comprises the steps of collecting input variable data, analyzing the input variable data into engineering codes by using a minimum execution instruction, judging whether the engineering codes accord with an alarm analysis result, and sending an alarm signal to the FPGA when the engineering codes accord with the alarm analysis result.
Description
Technical Field
The invention belongs to the field of protection of marine steam turbines.
Background
On-road steam turbine systems are generally applied to thermal power plants, nuclear power plants and the like, and the on-road steam turbines have the characteristic of constant rotating speed, namely, the steam turbines are controlled to keep the specific rotating speed unchanged. And the marine steam turbine is mainly used as a main power system of the ship and used for driving the propeller to rotate. In practical application, the rotating speed of the steam turbine can be changed at any time according to the requirement of the speed.
At present, the on-road turbine ETS system (turbine crisis shutdown system) is mostly referred to as a marine turbine protection system. The system does not consider the characteristics of variable rotating speed and complex environment of the marine steam turbine; and the protection system has long delay time and slow response and is easy to break down, thereby further influencing the safety of the operation of the steam turbine.
Disclosure of Invention
The invention provides a marine electric protection device and method based on a CPU and FPGA framework, aiming at solving the problem that the operation safety of a marine steam turbine is affected because an on-road steam turbine protection system is not suitable for the protection of the marine steam turbine.
A ship power protection device based on a CPU and FPGA framework comprises an FPGA, a main task CPU and a protocol stack CPU;
the protocol stack CPU comprises the following units:
a unit for collecting alarm conditions issued by the engineer station,
a unit for resolving the alarm condition using the TCP/IP protocol,
sending the alarm analysis result to a unit of the FPGA;
the FPGA comprises the following units:
the alarm resolution result is sent to the unit of the main task CPU,
a unit for acquiring a digital input signal and a frequency input signal,
a unit for filtering the collected digital quantity input signal and frequency input signal,
the filtered digital quantity input signal and frequency input signal are sent as input variable data to a unit in the main task CPU,
a unit for issuing an alarm action to the outside when receiving an alarm signal sent by the main task CPU;
the main task CPU includes the following units:
a unit for collecting data of an input variable,
the input variable data is parsed into units of engineering code using minimal execution instructions,
a unit for judging whether the engineering code conforms to the alarm analysis result,
and a unit for sending an alarm signal to the FPGA when the engineering code conforms to the alarm analysis result.
The main task CPU also comprises: and when the engineering code does not accord with the alarm condition analysis result, continuing to collect the unit of the input variable data.
The unit of whether the interrupt request exists is judged in real time,
a unit for stopping the current action when there is an interrupt request, using a timer to perform interrupt service,
and after the interrupt service is completed, continuing the unit of the action executed before the interrupt.
A unit for real-time judging whether the minimum execution instruction is abnormal,
and when the minimum execution instruction is abnormal and the stack overflows, performing exception handling and then re-initializing the hardware.
A ship power protection method based on CPU and FPGA architecture is realized based on the following functional modules, including FPGA, main task CPU and protocol stack CPU,
executing the following steps by using a protocol stack CPU:
collecting alarm conditions issued by the engineer station,
a step of resolving the alarm condition using the TCP/IP protocol,
sending an alarm analysis result to the FPGA;
utilizing the FPGA to execute the following steps:
a step of sending the alarm analysis result to the main task CPU,
a step of collecting a digital quantity input signal and a frequency input signal,
a step of filtering the acquired digital quantity input signal and the frequency input signal,
a step of transmitting the filtered digital quantity input signal and the frequency input signal as input variable data to a main task CPU,
when receiving an alarm signal sent by a main task CPU, issuing an alarm action to the outside;
executing the following steps by using a main task CPU:
a step of collecting input variable data,
a step of parsing input variable data into engineering code using a minimum execution instruction,
judging whether the engineering code accords with the alarm analysis result,
and when the engineering code accords with the alarm analysis result, sending an alarm signal to the FPGA.
The main task CPU can also execute the following steps: and when the engineering code does not accord with the alarm condition analysis result, continuing to collect the input variable data.
A step of judging whether an interrupt request exists in real time,
stopping the current action when there is an interrupt request, using a timer to perform interrupt service,
and after the interrupt service is completed, continuing the action executed before the interrupt.
A step of judging whether the minimum execution instruction is abnormal in real time,
and when the minimum execution instruction is abnormal and the stack overflows, performing exception handling and then re-initializing the hardware.
Has the advantages that: according to the marine power protection device and method based on the CPU and FPGA framework, the CPU and FPGA framework is simple, the work division of each sub-module is clear, the response speed of the whole system can be greatly improved in the provided minimum instruction execution process, and the operation safety of a marine steam turbine can be quickly and effectively protected.
Drawings
FIG. 1 is a flow chart of a ship power protection method based on a CPU + FPGA framework.
Detailed Description
The first embodiment is as follows: the ship power protection device based on the CPU and the FPGA framework comprises the FPGA, a main task CPU and a protocol stack CPU;
the protocol stack CPU comprises the following units:
a unit for collecting alarm conditions issued by the engineer station,
a unit for resolving the alarm condition using the TCP/IP protocol,
sending the alarm analysis result to a unit of the FPGA;
the FPGA comprises the following units:
the alarm resolution result is sent to the unit of the main task CPU,
a unit for acquiring a digital quantity input signal (DI) and a frequency input signal (FI),
a unit for filtering the collected digital quantity input signal and frequency input signal,
the filtered digital quantity input signal and frequency input signal are sent as input variable data to a unit in the main task CPU,
a unit for issuing an alarm action to the outside when receiving an alarm signal sent by the main task CPU;
the main task CPU includes the following units:
a unit for collecting data of an input variable,
the input variable data is parsed into units of engineering code using minimal execution instructions,
a unit for judging whether the engineering code conforms to the alarm analysis result,
and a unit for sending an alarm signal to the FPGA when the engineering code conforms to the alarm analysis result.
In the above embodiment, the main task CPU further includes:
when the engineering code does not accord with the alarm condition analysis result, continuing to acquire a unit for inputting variable data;
the unit of whether the interrupt request exists is judged in real time,
a unit for stopping the current action when there is an interrupt request, using a timer to perform interrupt service,
and after the interrupt service is completed, continuing the unit of the action executed before the interrupt.
The main task CPU also includes: the unit for initializing hardware and the unit for initializing minimum execution instructions.
The main task CPU also includes:
a unit for real-time judging whether the minimum execution instruction is abnormal,
and when the minimum execution instruction is abnormal and the stack overflows, performing exception handling and then re-initializing the hardware.
The FPGA sends input variable data to the main task CPU through the double-port RAM.
And the protocol stack CPU sends the alarm analysis result to the FPGA through the dual-port RAM, and the FPGA sends the alarm analysis result to the main task CPU through the dual-port RAM.
The second embodiment is as follows: referring to fig. 1, a method for protecting ship power consumption based on a CPU and an FPGA architecture according to this embodiment is implemented based on the following functional modules, where the functional modules include an FPGA, a main task CPU, and a protocol stack CPU, and the method includes the following steps:
executing the following steps by using a protocol stack CPU:
collecting alarm conditions issued by the engineer station,
a step of resolving the alarm condition using the TCP/IP protocol,
sending an alarm analysis result to the FPGA;
utilizing the FPGA to execute the following steps:
a step of sending the alarm analysis result to the main task CPU,
a step of acquiring a digital input signal (DI) and a frequency input signal (FI),
a step of filtering the acquired digital quantity input signal and the frequency input signal,
a step of transmitting the filtered digital quantity input signal and the frequency input signal as input variable data to a main task CPU,
when receiving an alarm signal sent by a main task CPU, issuing an alarm action to the outside;
executing the following steps by using a main task CPU:
a step of collecting input variable data,
a step of parsing input variable data into engineering code using a minimum execution instruction,
judging whether the engineering code accords with the alarm analysis result,
and when the engineering code accords with the alarm analysis result, sending an alarm signal to the FPGA.
In the above embodiment, the main task CPU may further execute the following steps:
when the engineering code does not accord with the alarm condition analysis result, continuing to collect input variable data;
a step of judging whether an interrupt request exists in real time,
stopping the current action when there is an interrupt request, using a timer to perform interrupt service,
and after the interrupt service is completed, continuing the action executed before the interrupt.
The main task CPU initializes the hardware first and then initializes the minimal execution instructions before performing all steps.
The main task CPU can also execute the following steps: a step of judging whether the minimum execution instruction is abnormal in real time,
and when the minimum execution instruction is abnormal and the stack overflows, performing exception handling and then re-initializing the hardware.
The FPGA sends input variable data to the main task CPU through the double-port RAM.
And the protocol stack CPU sends the alarm analysis result to the FPGA through the dual-port RAM, and the FPGA sends the alarm analysis result to the main task CPU through the dual-port RAM.
Claims (10)
1. A ship power protection device based on a CPU and FPGA framework is characterized by comprising an FPGA, a main task CPU and a protocol stack CPU;
the protocol stack CPU comprises the following units:
a unit for collecting alarm conditions issued by the engineer station,
a unit for resolving the alarm condition using the TCP/IP protocol,
sending the alarm analysis result to a unit of the FPGA;
the FPGA comprises the following units:
the alarm resolution result is sent to the unit of the main task CPU,
a unit for acquiring a digital input signal and a frequency input signal,
a unit for filtering the collected digital quantity input signal and frequency input signal,
the filtered digital quantity input signal and frequency input signal are sent as input variable data to a unit in the main task CPU,
a unit for issuing an alarm action to the outside when receiving an alarm signal sent by the main task CPU;
the main task CPU includes the following units:
a unit for collecting data of an input variable,
the input variable data is parsed into units of engineering code using minimal execution instructions,
a unit for judging whether the engineering code conforms to the alarm analysis result,
and a unit for sending an alarm signal to the FPGA when the engineering code conforms to the alarm analysis result.
2. The marine electric protection device based on the CPU and FPGA framework of claim 1, characterized in that the main task CPU further comprises: and when the engineering code does not accord with the alarm analysis result, continuing to collect the unit of the input variable data.
3. The marine electric protection device based on the CPU and FPGA framework of claim 1, characterized in that the main task CPU further comprises:
the unit of whether the interrupt request exists is judged in real time,
a unit for stopping the current action when there is an interrupt request, using a timer to perform interrupt service,
and after the interrupt service is completed, continuing the unit of the action executed before the interrupt.
4. The marine electric protection device based on the CPU and FPGA framework of claim 1, characterized in that the main task CPU further comprises: the unit for initializing hardware and the unit for initializing minimum execution instructions.
5. The marine electric protection device based on the CPU and FPGA framework of claim 4, characterized in that the main task CPU further comprises:
a unit for real-time judging whether the minimum execution instruction is abnormal,
and when the minimum execution instruction is abnormal and the stack overflows, performing exception handling and then re-initializing the hardware.
6. A ship power protection method based on a CPU and FPGA framework is characterized in that the method is realized based on the following functional modules, wherein the functional modules comprise an FPGA, a main task CPU and a protocol stack CPU,
executing the following steps by using a protocol stack CPU:
collecting alarm conditions issued by the engineer station,
a step of resolving the alarm condition using the TCP/IP protocol,
sending an alarm analysis result to the FPGA;
utilizing the FPGA to execute the following steps:
a step of sending the alarm analysis result to the main task CPU,
a step of collecting a digital quantity input signal and a frequency input signal,
a step of filtering the acquired digital quantity input signal and the frequency input signal,
a step of transmitting the filtered digital quantity input signal and the frequency input signal as input variable data to a main task CPU,
when receiving an alarm signal sent by a main task CPU, issuing an alarm action to the outside;
executing the following steps by using a main task CPU:
a step of collecting input variable data,
a step of parsing input variable data into engineering code using a minimum execution instruction,
judging whether the engineering code accords with the alarm analysis result,
and when the engineering code accords with the alarm analysis result, sending an alarm signal to the FPGA.
7. The marine power protection method based on the CPU and the FPGA framework as claimed in claim 6, wherein the main task CPU is further capable of executing the following steps: and when the engineering code does not accord with the alarm analysis result, continuing to collect the input variable data.
8. The marine power protection method based on the CPU and the FPGA framework as claimed in claim 6, wherein the main task CPU is further capable of executing the following steps:
a step of judging whether an interrupt request exists in real time,
stopping the current action when there is an interrupt request, using a timer to perform interrupt service,
and after the interrupt service is completed, continuing the action executed before the interrupt.
9. The marine power protection method based on the CPU and the FPGA framework as claimed in claim 6, wherein the main task CPU is further capable of executing the following steps:
the main task CPU initializes the hardware first and then initializes the minimal execution instructions before performing all steps.
10. The marine power protection method based on the CPU and FPGA framework as claimed in claim 9, wherein the main task CPU is further capable of executing the following steps:
a step of judging whether the minimum execution instruction is abnormal in real time,
and when the minimum execution instruction is abnormal and the stack overflows, performing exception handling and then re-initializing the hardware.
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| CN103235217B (en) * | 2013-04-11 | 2015-11-18 | 国家电网公司 | Dual protection act consistance monitoring device and monitoring method |
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