CN108983115B - State-dividing pulse testing method for T-type three-level MOSFET inverter - Google Patents

State-dividing pulse testing method for T-type three-level MOSFET inverter Download PDF

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CN108983115B
CN108983115B CN201810940810.3A CN201810940810A CN108983115B CN 108983115 B CN108983115 B CN 108983115B CN 201810940810 A CN201810940810 A CN 201810940810A CN 108983115 B CN108983115 B CN 108983115B
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mosfet
pulse
current
tested
inverter
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CN108983115A (en
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严庆增
赵仁德
徐海亮
何金奎
孙鹏霄
李广琛
王艳松
任旭虎
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China University of Petroleum East China
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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Abstract

The invention discloses a state-divided pulse testing method for a T-type three-level MOSFET inverter, which is characterized in that the voltage and current states of the T-type three-level MOSFET inverter are divided into four types for respective testing, a load inductor is connected to the output end of the inverter, the other end of the load inductor is connected to a negative direct-current bus in the first type and second type state testing, and the other end of the load inductor is connected to a positive direct-current bus in the third type and fourth type state testing. In a first type of test, testing the turn-on and turn-off characteristics of a first MOSFET of the inverter; in the second type of test, the on and off characteristics of a second MOSFET of the inverter are tested, and the synchronous rectification state of a fourth MOSFET is tested; in the third type of test, the on and off characteristics of the fourth MOSFET of the inverter are tested; in the fourth type of test, the on and off characteristics of the third MOSFET of the inverter are tested, and the synchronous rectification state of the first MOSFET is tested. The invention adopts different test circuits and pulses aiming at different working states of the inverter, has comprehensive test and can test the synchronous rectification state at the same time.

Description

State-dividing pulse testing method for T-type three-level MOSFET inverter
Technical Field
The invention belongs to the technical field of power electronics, relates to an inverter testing technology, and particularly relates to a state-division pulse testing method for a T-type three-level MOSFET inverter.
Background
At present, there are two main types of power electronic switching devices which are applied in inverters. One type is an Insulated Gate Bipolar Transistor (IGBT), which is mainly used in medium and high voltage inverters. The other type is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), which is mainly used in low-voltage inverters and has the characteristics of high switching speed and bidirectional channel current flowing. The fast switching speed of the MOSFET can enable the switching frequency of the inverter to be higher, and the weight and the volume of the passive filter are reduced; the channel current can flow in two directions, so that the inverter has a synchronous rectification state, the conduction loss of the device is reduced, and the efficiency of the inverter is improved. In addition, compared with a two-level inverter, the T-type three-level inverter has the advantages of small output harmonic, low device voltage stress, low electromagnetic interference and the like. Compared with the IGBT, the MOSFET has higher switching frequency and synchronous rectification, so that the MOSFET is applied to the T-type three-level inverter, and can replace the IGBT inverter in some application occasions, thereby further reducing the volume of the T-type three-level inverter and improving the power density and the efficiency of the inverter.
After the power circuit and the driving circuit of the T-type three-level MOSFET inverter are designed and manufactured, in order to ensure that the inverter can work reliably for a long time, the MOSFET device needs to be tested to obtain the turn-on characteristic, the turn-off characteristic, the turn-on loss and the turn-off loss of the MOSFET device, and the test is used as an important index for the quality of the inverter design. However, the conventional double-pulse test method usually only provides a test circuit and a test pulse under a certain condition, the test on the actual running state of the inverter is not comprehensive, and the synchronous rectification state of the T-type three-level MOSFET inverter cannot be tested. The T-type three-level MOSFET inverter has multiple working states, and the opening state and the current path are simultaneously related to the voltage and the current direction. Therefore, a pulse testing method which is in different states and can test the synchronous rectification state is needed, and the pulse testing method has very important significance for ensuring the long-term reliable work of the inverter.
Disclosure of Invention
The invention aims to provide a state-dividing pulse testing method for a T-type three-level MOSFET inverter, which can comprehensively test pulses and can test the synchronous current state of the inverter, aiming at the technical problems that the pulse testing is not comprehensive and the synchronous rectification state of the inverter cannot be tested in the prior art.
The technical scheme of the invention is as follows: a method for testing a state-dividing pulse of a T-type three-level MOSFET inverter comprises the following steps:
the inverter voltage and current states are classified into four categories, wherein the first category of voltage and current states are: both the voltage and the current are greater than 0; the second type of voltage and current conditions are: the voltage is less than 0, and the current is greater than 0; the third class of voltage and current states is: the voltage and the current are all less than 0; the fourth class of voltage and current states is: the voltage is greater than 0, and the current is less than 0;
load inductance LloadOne end is connected to MOSFET Q1、MOSFET Q3And MOSFET Q4The other end of the point is connected with a negative direct current bus; MOSFET Q1Applying a double pulse drive signal, MOSFET Q2The drive signal of (1) is kept at a high level, MOSFET Q3And MOSFET Q4The driving signal of (1) is kept at a low level, the inverter with the operation state of a first class voltage and current state is tested, and the MOSFET Q is tested1The turn-on characteristic and the turn-off characteristic of;
load inductance LloadOne end is connected to MOSFET Q1、MOSFET Q3And MOSFET Q4The other end of the point is connected with a negative direct current bus; MOSFET Q1And MOSFET Q3With the drive signal held low, MOSFET Q2Applying a double pulse drive signal to MOSFET Q4Adding a driving pulse for forming a synchronous current state to the driving signal, testing the inverter with the second class voltage and current state, and testing the MOSFET Q2On-and off-characteristics of the test MOSFETT Q4The synchronous rectification state of (1);
load inductance LloadOne end is connected to MOSFET Q1、MOSFET Q3And MOSFET Q4The other end of the point is connected with the positive direct current bus; MOSFET Q4Applying a double pulse drive signal, MOSFET Q3The drive signal of (1) is kept at a high level, MOSFET Q1And MOSFET Q2The driving signal of (1) is kept at a low level, and the inverter with the running state of a third class voltage and current state is tested to test the MOSFET Q4The turn-on characteristic and the turn-off characteristic of;
load inductance LloadOne end is connected to MOSFET Q1、MOSFET Q3And MOSFET Q4The other end of the point is connected with the positive direct current bus; MOSFET Q2And MOSFET Q4With the drive signal held low, MOSFET Q3Applying a double pulse drive signal to MOSFET Q1The driving signal of the inverter is added with a driving pulse for forming a synchronous current state, the inverter with the running state of a fourth class voltage and current state is tested, and a MOSFET Q is tested3On-and off-characteristics of the MOSFET Q1Synchronous rectification state of (1).
Preferably, the test is performed on the inverter operating in the first type of voltage and current state in the mosfet q1By the first pulse period of MOSFET Q1Establishing a required test current for a channel; in MOSFET Q1Between the first pulse and the second pulse, the current flows along the MOSFET Q2Channel and MOSFET Q3The body diode series path of (a); in MOSFET Q1At the second pulse rising edge time of (3), the MOSFET Q is tested1Opening property of (2); in MOSFET Q1At the time of the falling edge of the first pulse and the second pulse, the MOSFET Q is tested1The turn-off characteristic of (c).
Preferably, the test is performed on the inverter with the second type voltage and current state as the operation state of the MOSFET Q2By the first pulse period of MOSFET Q2And MOSFET Q3The body diode of (2) sets up the required test electricityA stream; in MOSFET Q2Between the first pulse and the second pulse, the current flows along the MOSFET Q4Freewheeling in the body diode path of (1); in MOSFET Q2At the second pulse rising edge time of (3), the MOSFET Q is tested2Opening property of (2); in MOSFET Q2At the time of the falling edge of the first pulse and the second pulse, the MOSFET Q is tested2The turn-off characteristic of (c); in MOSFET Q2Between the first pulse and the second pulse, MOSFET Q4The added drive pulse in the drive signal causes the MOSFET Q4Is turned on in reverse direction, the current flows along the MOSFET Q4Channel and MOSFET Q4The body diode parallel path of the circuit is in a synchronous rectification state, and the MOSFET Q is tested4Synchronous rectification state of (1).
Preferably, the test is performed on the inverter with the operation state of the third class voltage and current state in the MOSFET Q4By the first pulse period of MOSFET Q4Establishing a required test current for a channel; in MOSFET Q4During the second pulse period of time, current flows along MOSFET Q3Channel and MOSFET Q2The body diode series path of (a); in MOSFET Q4At the second pulse rising edge time of (3), the MOSFET Q is tested4Opening property of (2); in MOSFET Q1At the time of the falling edge of the first pulse and the second pulse, the MOSFET Q is tested4The turn-off characteristic of (c).
Preferably, the test is performed on the inverter with the fourth class voltage and current state as the operation state of the mosfet q3By the first pulse period of MOSFET Q3Channel and MOSFET Q2The body diode of (a) establishes the required test current; in MOSFET Q3Between the first pulse and the second pulse, the current flows along the MOSFET Q1Freewheeling in the body diode path of (1); in MOSFET Q3At the second pulse rising edge time of (3), the MOSFET Q is tested3Opening property of (2); in MOSFET Q3At the time of the falling edge of the first pulse and the second pulse, the MOSFET Q is tested3The turn-off characteristic of (c); in MOSFET Q3Between the first pulse and the second pulse, MOSFET Q1Adding to drive signalThe drive pulse of (2) makes the MOSFET Q1Is turned on in reverse direction, the current flows along the MOSFET Q1Channel and MOSFET Q1The body diode parallel path of the circuit is in a synchronous rectification state, and the MOSFET Q is tested1Synchronous rectification state of (1).
Compared with the prior art, the invention has the beneficial effects that:
(1) the testing method classifies each voltage and current state of the T-type three-level MOSFET inverter into four working states, adopts different testing circuits and pulses for different working states, has comprehensive pulse testing, and avoids the defect that only partial testing can be carried out on the inverter by adopting the traditional double-pulse testing.
(2) The testing method provided by the invention is used for testing the T-type three-level MOSFET inverter in steps, the pulse testing steps are clear, and the defect that the traditional double-pulse testing is irregular and can be carried out is avoided.
(3) The testing method can test the conventional current loop path of the T-type three-level MOSFET inverter, can test the synchronous rectification state of the T-type three-level MOSFET inverter, can be used for researching the shunting conditions of the MOSFET and the body diode in the synchronous rectification state, and provides a basis for researching to reduce the conduction loss of the MOSFET and improve the efficiency of the inverter.
Drawings
FIG. 1a is a first class voltage and current state diagram of a T-type three level MOSFET inverter in accordance with an embodiment of the present invention;
FIG. 1b shows an embodiment u of the present inventiona＞0,iaPulse test drive signal pattern > 0;
FIG. 1c shows an embodiment u of the present inventiona＞0,iaThe test circuit and the current establish a path diagram when the current is greater than 0;
FIG. 1d shows an embodiment u of the present inventiona＞0,iaA test circuit and current free-wheeling path diagram when > 0;
FIG. 2a is a diagram of a second type of voltage and current state for a T-type three level MOSFET inverter in accordance with an embodiment of the present invention;
FIG. 2b shows an embodiment u of the present inventiona＜0,iaPulse test drive signal pattern > 0;
FIG. 2c shows an embodiment u of the present inventiona＜0,iaThe test circuit and the current establish a path diagram when the current is greater than 0;
FIG. 2d shows an embodiment u of the present inventiona＜0,iaA test circuit and current free-wheeling path diagram when > 0;
FIG. 3a is a third class voltage and current state diagram of a T-type three level MOSFET inverter in accordance with an embodiment of the present invention;
FIG. 3b shows an embodiment u of the present inventiona＜0,iaA pulse test drive signal pattern for < 0;
FIG. 3c shows an embodiment u of the present inventiona＜0,iaThe test circuit and the current when the current is less than 0 establish a path diagram;
FIG. 3d shows an embodiment u of the present inventiona＜0,iaA test circuit and current freewheel path diagram when < 0;
FIG. 4a is a graph illustrating a fourth type of voltage and current state for a T-type three level MOSFET inverter in accordance with an embodiment of the present invention;
FIG. 4b shows an embodiment u of the present inventiona＞0,iaA pulse test drive signal pattern for < 0;
FIG. 4c shows an embodiment u of the present inventiona＞0,iaThe test circuit and the current when the current is less than 0 establish a path diagram;
FIG. 4d shows an embodiment u of the present inventiona＞0,iaTest circuit and current freewheel path diagram at < 0.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention.
The T-type three-level MOSFET inverter has multiple working states, and the opening state and the current path are simultaneously related to the voltage and the current direction. The invention discloses a state-division pulse testing method for a T-type three-level MOSFET inverter, which can perform pulse testing in different states, can test a synchronous rectification state and comprehensively test the actual running state of the inverter.
The invention provides a state-dividing pulse testing method for a T-type three-level MOSFET inverter, which comprises the following steps:
s1, dividing the voltage and current states of the inverter into four types, wherein the first type of voltage and current states are as follows: both the voltage and the current are greater than 0; the second type of voltage and current conditions are: the voltage is less than 0, and the current is greater than 0; the third class of voltage and current states is: the voltage and the current are all less than 0; the fourth class of voltage and current states is: the voltage is greater than 0, and the current is less than 0;
s2, inducing the load with LloadOne end is connected to MOSFET Q1、MOSFET Q3And MOSFET Q4The other end of the point is connected with a negative direct current bus; MOSFET Q1Applying a double pulse drive signal, MOSFET Q2The drive signal of (1) is kept at a high level, MOSFET Q3And MOSFET Q4The driving signal of (1) is kept at a low level, the inverter with the operation state of a first class voltage and current state is tested, and the MOSFET Q is tested1The turn-on characteristic and the turn-off characteristic of;
s3, inducing the load with LloadOne end is connected to MOSFET Q1、MOSFET Q3And MOSFET Q4The other end of the point is connected with a negative direct current bus; MOSFET Q1And MOSFET Q3With the drive signal held low, MOSFET Q2Applying a double pulse drive signal to MOSFET Q4Adding a driving pulse for forming a synchronous current state to the driving signal, testing the inverter with the second class voltage and current state, and testing the MOSFET Q2On-and off-characteristics of the MOSFET Q4The synchronous rectification state of (1);
s4, inducing the load with LloadOne end is connected to MOSFET Q1、MOSFET Q3And MOSFET Q4The other end of the point is connected with the positive direct current bus; MOSFET Q4Applying a double pulse drive signal, MOSFET Q3The drive signal of (1) is kept at a high level, MOSFET Q1And MOSFET Q2The driving signal is kept at low level, and the inverter with the running state of a third class voltage and current state is tested and testedTest MOSFET Q4The turn-on characteristic and the turn-off characteristic of;
s5, inducing the load with LloadOne end is connected to MOSFET Q1、MOSFET Q3And MOSFET Q4The other end of the point is connected with the positive direct current bus; MOSFET Q2And MOSFET Q4With the drive signal held low, MOSFET Q3Applying a double pulse drive signal to MOSFET Q1The driving signal of the inverter is added with a driving pulse for forming a synchronous current state, the inverter with the running state of a fourth class voltage and current state is tested, and a MOSFET Q is tested3On-and off-characteristics of the MOSFET Q1Synchronous rectification state of (1).
The testing method of the invention divides the voltage and current states of the inverter into four types, tests different working states by adopting different testing circuits and pulses, has clear and comprehensive pulse testing steps, can test the synchronous rectification state of the inverter, can be used for researching the shunt conditions of the MOSFET and the body diode in the synchronous rectification state, and provides a basis for researching to reduce the conduction loss of the MOSFET and improve the efficiency of the inverter. The method is suitable for the single-phase and three-phase T-type three-level MOSFET inverters.
As a preferable embodiment of the above test method, in step S2, when the inverter having the first type of voltage and current operation state is tested, the MOSFET Q is used1By the first pulse period of MOSFET Q1Establishing a required test current for a channel; in MOSFET Q1Between the first pulse and the second pulse, the current flows along the MOSFET Q2Channel and MOSFET Q3The body diode series path of (a); in MOSFET Q1At the second pulse rising edge time of (3), the MOSFET Q is tested1Opening property of (2); in MOSFET Q1At the time of the falling edge of the first pulse and the second pulse, the MOSFET Q is tested1The turn-off characteristic of (c).
As a preferable embodiment of the test method, in step S3, when the inverter whose operation state is the second type voltage and current state is tested, the MOSFET Q is used2The first pulse ofDuration of rush time, through MOSFET Q2And MOSFET Q3The body diode of (a) establishes the required test current; in MOSFET Q2Between the first pulse and the second pulse, the current flows along the MOSFET Q4Freewheeling in the body diode path of (1); in MOSFET Q2At the second pulse rising edge time of (3), the MOSFET Q is tested2Opening property of (2); in MOSFET Q2At the time of the falling edge of the first pulse and the second pulse, the MOSFET Q is tested2The turn-off characteristic of (c); in MOSFET Q2Between the first pulse and the second pulse, MOSFET Q4The added drive pulse in the drive signal causes the MOSFET Q4Is turned on in reverse direction, the current flows along the MOSFET Q4Channel and MOSFET Q4The body diode parallel path of the circuit is in a synchronous rectification state, and the MOSFET Q is tested4Synchronous rectification state of (1).
As a preferable embodiment of the test method, in step S4, when the inverter whose operation state is the third type voltage and current state is tested, the MOSFET Q is used4By the first pulse period of MOSFET Q4Establishing a required test current for a channel; in MOSFET Q4During the second pulse period of time, current flows along MOSFET Q3Channel and MOSFET Q2The body diode series path of (a); in MOSFET Q4At the second pulse rising edge time of (3), the MOSFET Q is tested4Opening property of (2); in MOSFET Q1At the time of the falling edge of the first pulse and the second pulse, the MOSFET Q is tested4The turn-off characteristic of (c).
As a preferable embodiment of the test method, in step S5, when the inverter whose operation state is the fourth type voltage and current state is tested, the MOSFET Q is used3By the first pulse period of MOSFET Q3Channel and MOSFET Q2The body diode of (a) establishes the required test current; in MOSFET Q3Between the first pulse and the second pulse, the current flows along the MOSFET Q1Freewheeling in the body diode path of (1); in MOSFET Q3At the second pulse rising edge time of (3), the MOSFET Q is tested3Opening property of (2); in MOSFET Q3First one of (1)Pulse and second pulse falling edge time, testing MOSFET Q3The turn-off characteristic of (c); in MOSFET Q3Between the first pulse and the second pulse, MOSFET Q1The added drive pulse in the drive signal causes the MOSFET Q1Is turned on in reverse direction, the current flows along the MOSFET Q1Channel and MOSFET Q1The body diode parallel path of the circuit is in a synchronous rectification state, and the MOSFET Q is tested1Synchronous rectification state of (1).
In the above test method of the present invention, the sequence of steps S2, S3, S4, and S5 is not limited to the above sequence, and may be interchanged arbitrarily.
To further illustrate the effect of the method for testing the pulse-under-state of the T-type three-level MOSFET inverter according to the present invention, a specific embodiment is described below.
The phase A of the T-type three-level MOSFET inverter will be described as an example, and u is referred toa＞0,ia> 0 (i.e. first class voltage and current states), ua＜0,ia> 0 (i.e. second class voltage and current states), ua＜0,ia< 0 (third class voltage and current state), ua＞0,iaAnd (4) testing and classifying four inverter operation states of < 0 (a fourth type voltage and current state). Referring to fig. 1c-d, 2c-d, 3c-d, 4c-d, the dc bus voltage of the inverter is VdcCapacitor Cdc1And Cdc2Dividing the DC bus voltage into two equal parts Vdc1And Vdc2，Qa1、Qa2、Qa3、Qa4For the MOSFET, a T-connection is formed. Referring to fig. 1a, 2a, 3a and 4a, since the load carried by the inverter is generally a resistive load, the current waveform lags behind the voltage waveform.
The inverter is operated in a state of ua＞0,iaFor > 0 (i.e. first class voltage and current state, see fig. 1a), the load inductance L, see fig. 1c, 1dloadOne end is connected to MOSFET Qa1、MOSFET Qa3And MOSFET Qa4The other end of the point is connected with a negative direct current bus; referring to FIG. 1b, MOSFET Qa1Applying a double pulse drive signal，MOSFET Qa2The drive signal of (1) is kept at a high level, MOSFET Qa3And MOSFET Qa4The driving signal of (1) is kept at a low level; referring to FIG. 1b, in MOSFET Qa1T of1～t2Time period through MOSFET Qa1The required test current is established for the channel, the current path is shown in figure 1 c; in MOSFET Qa1T of2～t3Current flow is along the MOSFET Q shown in FIG. 1da2Channel and MOSFET Qa3The body diode series path of (a); in the MOSFET Qa1T of3Time of day, MOSFET Q is testeda1Opening property of (2); in MOSFET Qa1T of2And t4Time of day, MOSFET Q is testeda1The turn-off characteristic of (c).
The inverter is operated in a state of ua＜0,iaFor > 0 (i.e. the second type of voltage and current state, see fig. 2a), the load inductance L, see fig. 2c, 2dloadOne end is connected to MOSFET Qa1、MOSFET Qa3And MOSFET Qa4The other end of the point is connected with a negative direct current bus; referring to FIG. 2b, MOSFET Qa1And MOSFET Qa3With the drive signal held low, MOSFET Qa2Applying a double pulse drive signal, MOSFET Qa4Adding a drive pulse for forming a synchronous current state to the drive signal; referring to FIG. 2b, in MOSFET Qa1T of1～t2Time period through MOSFET Qa2And MOSFET Qa3The body diode of (a) establishes the required test current, the current path being seen in fig. 2 c; in MOSFET Qa2T of2～t3And t4～t5Time period, current flow along MOSFET Q shown in FIG. 2da4Free-wheeling of the body diode path, MOSFET Q in this stagea4The channel of (a) is not conducting; in MOSFET Qa2T of5Time of day, MOSFET Q is testeda2Opening property of (2); in MOSFET Qa2T of2And t6Time of day, MOSFET Q is testeda2The turn-off characteristic of (c); in MOSFET Qa2T of3～t4Time period, MOSFET Qa4The added drive pulse in the drive signal causes the MOSFET Qa4Is reversely conductedCurrent flow is along the MOSFET Q shown in fig. 2da4Channel and MOSFET Qa4The body diode parallel path of the inverter is in follow current, the circuit is in a synchronous rectification state, and the synchronous rectification state of the inverter is tested. That is, t3～t4The test of the time period can be used for researching the synchronous rectification state of the T-type three-level MOSFET inverter.
The inverter is operated in a state of ua＜0,ia< 0 (third class voltage and current state, see fig. 3a), see fig. 3c, 3d, will load the inductor LloadOne end is connected to MOSFET Qa1、MOSFET Qa3And MOSFET Qa4The other end of the point is connected with the positive direct current bus; referring to FIG. 3b, MOSFET Qa4Applying a double pulse drive signal, MOSFET Qa3The drive signal of (1) is kept at a high level, MOSFET Qa1And MOSFET Qa2The driving signal of (1) is kept at a low level; referring to FIG. 3b, in MOSFET Qa4T of1～t2Time period through MOSFET Qa4The required test current is established for the channel, the current path is shown in figure 3 c; in MOSFET Qa4T of2～t3Time period, current flow along MOSFET Q shown in FIG. 3da3Channel and MOSFET Qa2The body diode series path of (a); in the MOSFET Qa4T of3Time of day, MOSFET Q is testeda4Opening property of (2); in MOSFET Qa4T of2And t4Time of day, MOSFET Q is testeda4The turn-off characteristic of (c).
The inverter is operated in a state of ua＞0,ia< 0 (i.e. fourth class voltage and current conditions, see fig. 4a), see fig. 4c, 4d, will load the inductor LloadOne end is connected to MOSFET Qa1、MOSFET Qa3And MOSFET Qa4The other end of the point is connected with the positive direct current bus; referring to FIG. 4b, MOSFET Qa2And MOSFET Qa4With the drive signal held low, MOSFET Qa3Applying a double pulse drive signal, MOSFET Qa1Adding a drive pulse for forming a synchronous current state to the drive signal; referring to FIG. 4b, in MOSFET Qa3T of1～t2Time period, generalOver MOSFET Qa3Channel and MOSFET Qa2The body diode of (a) establishes the required test current, the current path being seen in fig. 4 c; in MOSFET Qa3T of2～t3And t4～t5Time period, current flow along MOSFET Q shown in FIG. 4da1Free-wheeling of the body diode path, MOSFET Q in this stagea1The channel of (a) is not conducting; in MOSFET Qa3T of5Time of day, MOSFET Q is testeda3Opening property of (2); in MOSFET Qa3T of2And t6Time of day, MOSFET Q is testeda3The turn-off characteristic of (c); in MOSFET Qa3T of3～t4Time period, MOSFET Qa1The added drive pulse in the drive signal causes the MOSFET Qa1Is turned on in reverse direction and current flows along the MOSFET Q shown in fig. 4da1Channel and MOSFET Qa1The body diode parallel path of the inverter is in follow current, the circuit is in a synchronous rectification state, and the synchronous rectification state of the inverter is tested. That is, t3～t4The test of the time period can be used for researching the synchronous rectification state of the T-type three-level MOSFET inverter.
The above description is only a preferred embodiment of the present invention, and not intended to limit the present invention in other forms, and any person skilled in the art may apply the above modifications or changes to the equivalent embodiments with equivalent changes, without departing from the technical spirit of the present invention, and any simple modification, equivalent change and change made to the above embodiments according to the technical spirit of the present invention still belong to the protection scope of the technical spirit of the present invention.

Claims (5)

1. A method for testing the pulse state of T-type three-level MOSFET inverter is characterized by that in the T-type three-level MOSFET inverter, the capacitor Cdc1And a capacitor Cdc2Connected in series to divide the DC bus voltage into two equal parts Vdc1And Vdc2；MOSFET Q1And MOSFET Q4Series connected, MOSFET Q1Connected to a positive DC bus, MOSFET Q4Is connected with a negative direct current busConnecting; MOSFET Q2And MOSFET Q3Series connected, MOSFET Q2Connecting capacitor Cdc1And a capacitor Cdc2Cross point between, MOSFET Q3Connecting MOSFET Q1And MOSFET Q4The intersection point between them; load inductance LloadOne end of which is connected with the MOSFET Q1And MOSFET Q4The other end of the intersection point is connected with a positive direct current bus or a negative direct current bus; the test method comprises the following steps:
the inverter voltage and current states are classified into four categories, wherein the first category of voltage and current states are: both the voltage and the current are greater than 0; the second type of voltage and current conditions are: the voltage is less than 0, and the current is greater than 0; the third class of voltage and current states is: the voltage and the current are all less than 0; the fourth class of voltage and current states is: the voltage is greater than 0, and the current is less than 0;
load inductance LloadOne end is connected to MOSFET Q1、MOSFET Q3And MOSFET Q4The other end of the point is connected with a negative direct current bus; MOSFET Q1Applying a double pulse drive signal, MOSFET Q2The drive signal of (1) is kept at a high level, MOSFET Q3And MOSFET Q4The driving signal of (1) is kept at a low level, the inverter with the operation state of a first class voltage and current state is tested, and the MOSFET Q is tested1The turn-on characteristic and the turn-off characteristic of;
load inductance LloadOne end is connected to MOSFET Q1、MOSFET Q3And MOSFET Q4The other end of the point is connected with a negative direct current bus; MOSFET Q1And MOSFET Q3With the drive signal held low, MOSFET Q2Applying a double pulse drive signal to MOSFET Q4Adding a driving pulse for forming a synchronous current state to the driving signal, testing the inverter with the second class voltage and current state, and testing the MOSFET Q2On-and off-characteristics of the MOSFET Q4The synchronous rectification state of (1);
load inductance LloadOne end is connected to MOSFET Q1、MOSFET Q3And MOSFET Q4Of (2)The other end of the point is connected with a positive direct current bus; MOSFET Q4Applying a double pulse drive signal, MOSFET Q3The drive signal of (1) is kept at a high level, MOSFET Q1And MOSFET Q2The driving signal of (1) is kept at a low level, and the inverter with the running state of a third class voltage and current state is tested to test the MOSFET Q4The turn-on characteristic and the turn-off characteristic of;
load inductance LloadOne end is connected to MOSFET Q1、MOSFET Q3And MOSFET Q4The other end of the point is connected with the positive direct current bus; MOSFET Q2And MOSFET Q4With the drive signal held low, MOSFET Q3Applying a double pulse drive signal to MOSFET Q1The driving signal of the inverter is added with a driving pulse for forming a synchronous current state, the inverter with the running state of a fourth class voltage and current state is tested, and a MOSFET Q is tested3On-and off-characteristics of the MOSFET Q1Synchronous rectification state of (1).
2. The method of claim 1, wherein the testing of the inverter operating at the first type of voltage and current conditions is performed while testing the MOSFET Q1By the first pulse period of MOSFET Q1Establishing a required test current for a channel; in MOSFET Q1Between the first pulse and the second pulse, the current flows along the MOSFET Q2Channel and MOSFET Q3The body diode series path of (a); in MOSFET Q1At the second pulse rising edge time of (3), the MOSFET Q is tested1Opening property of (2); in MOSFET Q1At the time of the falling edge of the first pulse and the second pulse, the MOSFET Q is tested1The turn-off characteristic of (c).
3. The method of claim 1, wherein the MOSFET Q is tested in the event of an inverter operating in the second class of voltage and current conditions2First ofOne pulse period, through MOSFET Q2And MOSFET Q3The body diode of (a) establishes the required test current; in MOSFET Q2Between the first pulse and the second pulse, the current flows along the MOSFET Q4Freewheeling in the body diode path of (1); in MOSFET Q2At the second pulse rising edge time of (3), the MOSFET Q is tested2Opening property of (2); in MOSFET Q2At the time of the falling edge of the first pulse and the second pulse, the MOSFET Q is tested2The turn-off characteristic of (c); in MOSFET Q2Between the first pulse and the second pulse, MOSFET Q4The added drive pulse in the drive signal causes the MOSFET Q4Is turned on in reverse direction, the current flows along the MOSFET Q4Channel and MOSFET Q4The body diode parallel path of the circuit is in a synchronous rectification state, and the MOSFET Q is tested4Synchronous rectification state of (1).
4. The method of claim 1, wherein the MOSFET Q is tested in the event of an inverter operating in a third class of voltage and current conditions4By the first pulse period of MOSFET Q4Establishing a required test current for a channel; in MOSFET Q4During the second pulse period of time, current flows along MOSFET Q3Channel and MOSFET Q2The body diode series path of (a); in MOSFET Q4At the second pulse rising edge time of (3), the MOSFET Q is tested4Opening property of (2); in MOSFET Q1At the time of the falling edge of the first pulse and the second pulse, the MOSFET Q is tested4The turn-off characteristic of (c).
5. The method of claim 1, wherein the MOSFET Q is tested in the event of an inverter operating in a fourth class voltage and current regime3By the first pulse period of MOSFET Q3Channel and MOSFET Q2The body diode of (a) establishes the required test current; in MOSFET Q3First pulse of (2) andbetween the second pulse, current flows along MOSFET Q1Freewheeling in the body diode path of (1); in MOSFET Q3At the second pulse rising edge time of (3), the MOSFET Q is tested3Opening property of (2); in MOSFET Q3At the time of the falling edge of the first pulse and the second pulse, the MOSFET Q is tested3The turn-off characteristic of (c); in MOSFET Q3Between the first pulse and the second pulse, MOSFET Q1The added drive pulse in the drive signal causes the MOSFET Q1Is turned on in reverse direction, the current flows along the MOSFET Q1Channel and MOSFET Q1The body diode parallel path of the circuit is in a synchronous rectification state, and the MOSFET Q is tested1Synchronous rectification state of (1).
CN201810940810.3A 2018-08-17 2018-08-17 State-dividing pulse testing method for T-type three-level MOSFET inverter Expired - Fee Related CN108983115B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2079068A1 (en) * 1991-09-25 1993-03-26 Kazutoshi Takahashi Method and apparatus for testing self-commutative electric power conversion device
CN103105554A (en) * 2013-01-29 2013-05-15 上海电气集团股份有限公司 Test circuit and method of two-electrical-level converter switching performance based on double pulses
CN104965136A (en) * 2015-06-18 2015-10-07 国电南瑞科技股份有限公司 Three-level converter power unit double pulse test method
CN204925331U (en) * 2015-09-17 2015-12-30 湘潭电机股份有限公司 Two pulse switch capability test devices of IGBT power unit
CN105974234A (en) * 2016-05-31 2016-09-28 西安许继电力电子技术有限公司 T-shaped three-level converter power module double-pulse testing loop and testing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2079068A1 (en) * 1991-09-25 1993-03-26 Kazutoshi Takahashi Method and apparatus for testing self-commutative electric power conversion device
CN103105554A (en) * 2013-01-29 2013-05-15 上海电气集团股份有限公司 Test circuit and method of two-electrical-level converter switching performance based on double pulses
CN104965136A (en) * 2015-06-18 2015-10-07 国电南瑞科技股份有限公司 Three-level converter power unit double pulse test method
CN204925331U (en) * 2015-09-17 2015-12-30 湘潭电机股份有限公司 Two pulse switch capability test devices of IGBT power unit
CN105974234A (en) * 2016-05-31 2016-09-28 西安许继电力电子技术有限公司 T-shaped three-level converter power module double-pulse testing loop and testing method

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
周志华.一种三电平功率单元试验方法研究.《电工电气》.2016, *
杨国润 等.一种四管动作的高压大功率三电平变流器双脉冲测试方法.《中国电机工程学报》.2015,第35卷(第3期), *

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