CN108959106B

CN108959106B - Memory access method and device

Info

Publication number: CN108959106B
Application number: CN201710353012.6A
Authority: CN
Inventors: 展旭升; 孙凝晖; 包云岗; 黄巍
Original assignee: Huawei Technologies Co Ltd; Institute of Computing Technology of CAS
Current assignee: Huawei Technologies Co Ltd; Institute of Computing Technology of CAS
Priority date: 2017-05-18
Filing date: 2017-05-18
Publication date: 2020-12-18
Anticipated expiration: 2037-05-18
Also published as: CN108959106A

Abstract

The application discloses a memory access method and a device, which belong to the technical field of memories, and the method comprises the following steps: receiving a memory access request; the memory access request is used for requesting to access a target row in a Dynamic Random Access Memory (DRAM); when the target row is a weak row, determining a mapping address corresponding to the target row in a reserved field in the DRAM according to an offset table and a preset starting address; the offset table comprises address offsets corresponding to weak lines in the DRAM in the reserved domain, and the preset starting address is the starting address of the reserved domain; the row pointed to by the address offset in the reserved field is not a weak row; accessing the reserved domain according to the mapping address; and returning an access result. The method solves the problems that the bus congestion is possibly caused and the performance of the system is reduced due to more refreshing commands in the bus in the related technology; the effects of avoiding bus congestion and improving performance are achieved.

Description

Memory access method and device

Technical Field

The present application relates to the field of memory technologies, and in particular, to a method and an apparatus for accessing a memory.

Background

A Dynamic Random Access Memory (DRAM) constitutes a unit with one transistor and one capacitor, and further stores one bit of data.

Over time, however, the capacitance can leak charge resulting in loss of the data stored in the cell. Therefore, in order to maintain the data stored in the cells, an operation of refreshing the data stored in each cell is periodically performed, and in actual implementation, the refresh operation is performed in units of a row (a word line (word) connects a plurality of cells in the same row in series to form a row). In the DRAM, the duration of data maintenance of most of the cells is above 256ms, while the duration of data maintenance of a few of the cells is less than 256ms or even less than 64ms, so in order to ensure that data of each cell in a certain row is not lost, in the related art, a refresh cycle less than a target duration is required to refresh data in the row. Wherein the target duration is the sustain time corresponding to the cell with the shortest sustain time in the row. For example, if the retention time corresponding to the cell with the shortest retention time in a certain row is 40ms, for the row, the duration of the row needs to be less than 40ms, for example, 35ms of refresh cycle is used for refreshing.

In the above scheme, when there are many weak rows in the DRAM, since the refresh cycle for refreshing each weak row is short, there are many refresh commands in the bus, which may cause bus congestion and reduce system performance.

Disclosure of Invention

In order to solve the problem of low performance of a bus congestion system in the related art, embodiments of the present application provide a memory access method and apparatus.

In a first aspect, a memory access method is provided, where the memory access method includes:

receiving a memory access request; the memory access request is used for requesting to access a target row in the DRAM;

when the target row is a weak row, determining a mapping address corresponding to the target row in a reserved field in the DRAM according to the offset table and a preset initial address; the offset table comprises address offset corresponding to the weak row in the DRAM in the reserved domain, and the preset starting address is the starting address of the reserved domain; the row pointed to by the address offset in the reserved field is not a weak row;

accessing the reserved domain according to the mapping address;

and returning an access result.

When the target line requested to be accessed is a weak line, calculating a mapping address corresponding to the target line in a reserved domain of the DRAM according to a pre-stored offset table and a preset initial address, accessing the reserved domain in the DRAM according to the mapping address, and returning an access result; the rows pointed by the address offsets in the offset table in the reserved field are not weak rows, so that the access address of the weak row is converted when the weak row is requested to be accessed, so that the normal row in the DRAM can be accessed, the DRAM can be refreshed according to the normal refreshing period in the subsequent refreshing process, and the problems that in the related technology, the number of refreshing commands in the bus is large, the bus congestion is possibly caused, and the system performance is reduced are solved; the effects of avoiding bus congestion and improving performance are achieved.

In a first possible implementation manner, returning an access result includes:

receiving a returned result which is returned by the DRAM and carries a first address, wherein the first address is an accessed address in the DRAM;

calculating a difference value between the first address and a preset initial address;

if the difference is larger than 0, calculating a second address corresponding to the first address according to the offset table and a preset initial address;

and returning an access result carrying the second address.

In a second possible implementation manner, the method further includes:

detecting whether a target row is a row in a weak row list, wherein the weak row list comprises each weak row in a DRAM;

if so, the target row is determined to be a weak row.

With reference to the second possible implementation manner, in a third possible implementation manner, the method further includes:

for each row in the DRAM, detecting whether the row comprises a unit with the maintaining time less than the preset time length;

if the unit with the maintaining time shorter than the preset time length is included, determining the line as a weak line;

and generating and storing a weak row list according to the determination result.

With reference to the first aspect and the several possible implementation manners of the first aspect, in a fourth possible implementation manner, before determining, according to the offset table and the preset starting address, a mapping address corresponding to the target row in the reserved field in the DRAM, the method further includes:

acquiring the row number of weak rows in the DRAM and the size of each weak row;

calculating the total size corresponding to each weak row in the DRAM according to the acquired row number and the size of each weak row;

reserving a storage space with a preset size in the DRAM as a reserved domain, wherein the preset size is larger than or equal to the total size obtained by calculation;

and saving the initial address of the reserved domain as a preset initial address.

With reference to the first aspect and the several possible implementation manners of the first aspect, in a fifth possible implementation manner, before determining, according to the offset table and the preset starting address, a mapping address corresponding to the target row in the reserved field in the DRAM, the method further includes:

determining the address offset corresponding to each weak row in a reserved field according to the sequence of each weak row in the DRAM;

an offset table is maintained that includes the respective address offsets.

In a second aspect, there is provided a memory access apparatus, the apparatus comprising: the DRAM is connected with the memory controller; the memory controller is configured to execute instructions, and the memory controller implements the memory access method of the first aspect by executing the instructions.

Drawings

FIG. 1 is a schematic illustration of an implementation environment to which various embodiments of the present application relate;

fig. 2 is a flowchart of a method for accessing a memory according to an embodiment of the present application;

FIG. 3 is a diagram illustrating a memory controller determining an address offset for a weak row according to an embodiment of the present disclosure;

FIG. 4 is a diagram illustrating an offset table stored by a memory controller according to an embodiment of the present disclosure;

fig. 5 is a schematic block diagram of a memory access method according to an embodiment of the present application;

fig. 6 is a schematic diagram of a memory access device according to an embodiment of the present application.

Detailed Description

The terms "first," "second," and the like, as used herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

Reference herein to a "module" generally refers to a program or instructions stored in memory that is capable of performing certain functions; reference herein to "a unit" generally refers to a logically partitioned functional structure, and the "unit" may be implemented by pure hardware or a combination of hardware and software.

Reference herein to "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

Referring to fig. 1, a schematic diagram of an implementation environment according to various embodiments of the invention is shown, as shown in fig. 1, the implementation environment includes a Central Processing Unit (CPU) 110, a memory controller 120, and a DRAM 130. Wherein:

CPU110 is used to access DRAM130 through memory controller 120. For example, CPU110 may send a read/write request to memory controller 120 for reading from or writing to memory. In actual implementation, there may be one or more CPUs 110, which is not limited to this.

Memory controller 120 refers to a device in a terminal that controls DRAM 130. For example, after receiving the read/write request sent by the CPU110, the memory controller 120 may perform a read/write operation on the DRAM according to the address requesting the read/write operation in the read/write request. In addition, the memory controller 120 may also receive the read/write result returned by the DRAM, and feed back the read/write result to the CPU 110.

Referring to fig. 2, a flowchart of a method for accessing a memory according to an embodiment of the present invention is shown, where the method is used in the memory controller shown in fig. 1 for illustration. As shown in fig. 2, the memory access method includes the following steps:

in step 201, for each row in the DRAM, it is detected whether a cell having a retention time less than a preset duration is included in the row.

After the DRAM memory is first inserted into the terminal, the memory controller may detect, for each row in the DRAM, whether a cell having a retention time less than a predetermined duration is included in the row. The preset time duration is a preset time duration in the memory controller, and the preset time duration may be 256ms, and in actual implementation, the preset time duration may also be other values, such as 128ms or 64ms, according to different actual design requirements, which is not limited in this embodiment.

In actual implementation, for each unit in each row, the memory controller may detect whether the retention time of the unit is less than a preset duration, and if the detection result is less than the preset duration, determine that the unit with the retention time less than the preset duration is included in the row; if the detection result is not less than the predetermined threshold, the memory controller may continue to detect other cells in the row until all cells in the row have been detected.

In step 202, if the cells with the retention time less than the preset duration are included, the rows including the cells with the retention time less than the preset duration are determined as weak rows.

If a row includes a cell whose retention time is less than a predetermined duration, it indicates that the data stored in the cell will be lost in a short time, and at this time, the memory controller may determine that the row is weak.

If a row does not include a cell with a retention time less than the predetermined duration, the memory controller may determine that the row is a normal row.

And step 203, generating and saving a weak row list according to the determination result.

The weak row list includes the weak rows in the DRAM. In actual implementation, the weak row list includes addresses of the weak rows. For example, if a row in the DRAM is a weak row and the address of the row (referred to herein as the starting address of the row) is 0xff00, the weak row list may include 0xff 00.

Alternatively, the memory controller may save the list of weak lines in its own hardware.

It should be noted that steps 201 to 203 are executed by the memory controller after the DRAM is first inserted into the terminal.

At step 204, the number of rows of weak rows in the DRAM and the size of each weak row are obtained.

When the terminal is restarted, the memory controller may retrieve the number of rows of weak rows in the DRAM and the size of each weak row. Wherein:

the step of the memory controller obtaining the row number of the weak row comprises the following steps: and reading the weak row list stored by the user, and counting the row number of all weak rows according to the reading result.

The step of the memory controller obtaining the size of each weak row comprises the following steps: the size of each row in the DRAM is read as preset. DRAM is an array memory, and the number of cells in each row is the same, i.e., the size of each row is the same and is determined by the DRAM hardware, so the memory controller can directly read the size of the row in the DRAM. For example, if the row size in a DRAM is 8kB, the memory controller can read the weak rows to have a size of 8 kB.

Step 205, calculating the total size corresponding to the weak row in the DRAM according to the obtained number of rows and the size of each weak row.

Alternatively, the memory controller may calculate a product of the acquired number of rows and the size of each weak row, and use the product as the total size corresponding to each weak row in the DRAM.

Step 206, reserving a storage space with a preset size in the DRAM as a reserved field, where the preset size is greater than or equal to the calculated total size.

After calculating the total size, the memory controller may reserve a memory space of a predetermined size in the DRAM. The preset size may be the calculated total size, and to ensure normal operation of the DRAM, the preset size may also be the total size + a fixed size, which is the size of a reserved storage space for subsequent use.

Optionally, the memory controller may reserve a memory space of a preset size at the last of the DRAM; or reserving a storage space with a preset size at the initial address of the DRAM; or, a memory space with a preset size is reserved at a preset position of the DRAM, which is not limited in this embodiment. The following description will take the example of reserving the storage space at the end unless otherwise specified.

Note that the memory area in the DRAM other than the reserved field is a normal field.

Step 207, the start address of the reserved field is saved as a preset start address.

After the memory controller reserves the reserved field, the memory controller may save the start address of the reserved field as a preset start address. In practice, the memory controller may store the default start Address in its Base Address memory (Base Address Register).

And step 208, determining the address offset corresponding to each weak row in the reserved field according to the sequence of each weak row in the DRAM.

The memory controller may obtain the ordering of each weak row according to the address of each weak row in the weak row list. For example, the memory controller obtains that the weak rows in a certain DRAM are respectively row 3, row 10, row 12, and so on, that is, the 3 rd row is ranked as the 0 th bit in the weak row, the 10 th row is ranked as the 1 st bit in the weak row, and so on, the ranks of the weak rows can be obtained. Alternatively, the memory controller may obtain the ordering of the various weak rows in the normal domain.

Thereafter, the memory controller determines the address offset for each weak row based on the retrieved rank. Alternatively, for a weak row ranked at the ith bit, the memory controller may determine i as the address offset of the weak row. For example, for the weak row of row 3 above, the memory controller may determine that the address offset of the weak row is 0, and for the weak row of row 10, the memory controller may determine that the address offset of the weak row is 1.

In practical implementation, since the reserved field may also include a weak row, when determining the address offset, for the weak row ranked at the ith bit, the memory controller may detect whether the row in the reserved field after the offset j is a weak row, if so, j +1 is detected, and whether the row in the reserved field after the offset j is a weak row is detected again until the row after the offset j is not a weak row, and j is determined as the address offset of the weak row; and if not, determining j as the address offset of the weak row. Wherein j-1 is the address offset corresponding to the weak row ranked at the i-1 th bit.

In an exemplary example, for the weak row of the above row 3, since the starting address of the reserved field, that is, the first row of the reserved field, is not a weak row, the memory controller may determine 0 as the address offset of the row; for the weak row of the 10 th row, since the 2 nd row in the reserved field is a weak row, the memory controller may detect whether the 3 rd row in the reserved field is a weak row, and determine 2 as the address offset of the row when the row is not a weak row, and so on, the memory controller may determine the address offset corresponding to each weak row in the normal field. For example, the determined address offsets are 0, 2, 3, 6, 7, and so on in sequence.

For example, referring to FIG. 3, a possible diagram of the memory controller determining the address offset is shown.

It should be noted that, since the size of each row in the DRAM is the same and fixed, the row after the offset j refers to a space corresponding to the reserved field after the offset j × n. Where n is the size of each row in the DRAM.

It should be noted that, the above is only illustrated by the address offset being represented by the number of offset lines, and in practical implementation, the address offset may also be represented by an offset address, that is, the address offset is a difference between an address after offset and an address before offset.

At step 209, an offset table is saved that includes the respective address offsets.

Alternatively, the memory controller may save the offset table in its own hardware. For example, referring to FIG. 4, a possible offset table maintained by the memory controller is shown.

Step 210, receiving a memory access request; the memory access request is for requesting access to a target row in a dynamic random access memory DRAM.

When the CPU needs to access the DRAM, the CPU may send a memory access request to the memory controller, and the memory controller may receive the memory access request accordingly. The memory access request may be a read request or a write request, and the memory access request carries a target address of a target row requested to be accessed in actual implementation.

For example, when the CPU needs to write content to 0xfff0 in the DRAM, the CPU may send a write request carrying 0xfff0 to the memory controller.

Optionally, after receiving the memory access request, the memory controller puts the memory access request into an Input Queue (Input Queue).

Step 211, detect whether the target row is a row in the weak row list.

The memory controller may detect whether the target address in the memory access request is included in the weak row list, and if so, determine that the target row requested to be accessed is a weak row, otherwise, determine that the target row requested to be accessed is not a weak row.

If yes, step 212 determines that the target row is a weak row.

If the detection result is that the target row is not a weak row, then at this time, the memory controller may access the DRAM through an access method provided by the related art, which is not described herein again.

And step 213, when the target row is a weak row, determining a mapping address corresponding to the target row in a reserved field in the DRAM according to the offset table and the preset starting address.

If the memory controller detects that the target line requested to be accessed is a weak line, it indicates that the data stored in the line may be lost, at this time, to ensure data security, the memory controller may query an offset table for an address offset corresponding to the target line, and determine an address in the reserved field after the address offset queried from the preset starting address is offset as a mapping address corresponding to the target line in the reserved field.

For example, if the preset starting address is 0xfff0, when the queried address offset is 0, the determined mapping address is 0xfff 0; when the searched address offset is 1, the determined mapping address is the address after shifting by one row from 0xfff 0.

Alternatively, after determining the mapped address, the memory controller may convert the memory access request into a series of DRAM commands and place the DRAM commands into a Queue Pool (Queue Pool).

Step 214, accessing the reserved domain according to the mapping address.

The memory controller can directly access the position corresponding to the mapping address in the reserved domain. For example, when the memory access request is a write request, writing the content into the memory space corresponding to the mapping address; for another example, when the memory access request is a read request, the content in the memory space corresponding to the mapping address is read.

In practical implementation, the memory controller may select a command to be executed in the queue pool according to a preset scheduling policy, and then send the selected command to the DRAM through the signal interface, and after receiving the command, the DRAM executes a corresponding operation in the storage space corresponding to the mapping address.

Step 215, receiving the access result carrying the first address returned by the DRAM. The first address is an address accessed in the DRAM.

After the memory controller accesses the reserved field in the DRAM according to the mapping address, the DRAM can return the access result to the memory controller. Wherein, the address of the access result returned by the DRAM is the address actually accessed in the DRAM. That is, when the memory controller accesses the DRAM according to the mapped address, the access result carries the mapped address.

In actual implementation, the access result may further include other content, for example, when the memory access request is a read request, the access result may further include read content; when the memory access request is a write request, the access result may further include a write result, such as information carrying write success or information carrying write failure.

In step 216, a difference between the first address and the predetermined starting address is calculated.

After receiving the access result, the memory controller may calculate a difference between the first address in the access result and the preset starting address.

Step 217, if the difference is greater than 0, calculating a second address corresponding to the first address according to the offset table and the preset start address.

If the difference is greater than 0, it indicates that the access result accesses the content in the reserved field in the DRAM, that is, the memory access request requests the weak line in the DRAM, so that, in order to recover the original address corresponding to the access result and enable the CPU to recognize the access result, the memory controller may calculate the second address corresponding to the first address according to the offset table and the preset starting address.

Optionally, the memory controller may query the address of the weak row corresponding to the calculated difference in the offset table, and use the address of the weak row obtained through the query as the second address. For example, if the difference between the first address and the preset start address is the content of 2 rows, it may be determined that the address offset is 2, and at this time, the memory controller may query the address of the weak row with the address offset of 2 in the offset table shown in fig. 4.

It should be noted that, if the difference is smaller than 0, it indicates that the memory access request accesses a normal domain in the DRAM, that is, the memory access request accesses the content of a normal row, and at this time, the memory controller may directly return the access result to the CPU.

Step 218, returning the access result carrying the second address.

Optionally, after determining the second address, the memory controller may add the access result after updating the address to a Return Transaction Queue (Return Transaction Queue), and then Return the content in the Return Transaction Queue to the CPU according to a preset scheduling rule.

Referring to fig. 5, a schematic diagram of the memory access method provided in the present embodiment is shown.

In one exemplary embodiment, the total capacity of the DRAM is 32GB, and comprises 2 channels, each channel having 4 memory banks (rank), each rank having 8 memory array banks, and each bank having 64000 rows. The size of each line is 8 KB. There are 28 rows for rows with a retention time less than 128ms, 978 rows for retention times between 128ms and 256ms, and all remaining rows have a retention time greater than 256 ms. In the present invention, all 1006 rows with a retention time of less than 256ms are regarded as weak rows, and 32GB memory space is divided into two parts, namely a normal domain and a reserved domain, wherein the size of the reserved domain is 8KB × 7.86MB, which is less than 0.024% of the total capacity, but in the above scheme, when the memory controller refreshes data stored in each cell in the DRAM, the memory controller can refresh with a refresh cycle of 256ms, that is, the scheme provided in this embodiment replaces 4 times of the refresh cycle with 0.024% of the total capacity of the memory space.

It should be noted that, the steps 210 to 218 may be executed once after the step 209, or may be executed multiple times, which is not limited in this embodiment.

It should be noted that, in the above embodiments, the method is implemented by using a memory controller as an example, and in practical implementation, the method may also be implemented by adding a controller, where the controller may be located between a CPU and the memory controller, or between the memory controller and a DRAM, which is not limited herein.

In summary, in the memory access method provided in this embodiment, when the target row requested to be accessed is a weak row, the mapping address corresponding to the target row in the reserved field of the DRAM is calculated according to the pre-stored offset table and the preset starting address, and then the reserved field in the DRAM is accessed according to the mapping address, and the access result is returned; the rows pointed by the address offsets in the offset table in the reserved field are not weak rows, so that the access address of the weak row is converted when the weak row is requested to be accessed, so that the normal row in the DRAM can be accessed, the DRAM can be refreshed according to the normal refreshing period in the subsequent refreshing process, and the problems that in the related technology, the number of refreshing commands in the bus is large, the bus congestion is possibly caused, and the system performance is reduced are solved; the effects of avoiding bus congestion and improving performance are achieved.

Referring to fig. 6, a schematic structural diagram of a memory access device according to an embodiment of the present invention is shown, as shown in fig. 6, the memory access device may include: a receiving unit 610, a determining unit 620, an accessing unit 630 and a returning unit 640.

A receiving unit 610, configured to receive a memory access request; the memory access request is used for requesting to access a target row in a Dynamic Random Access Memory (DRAM);

a determining unit 620, configured to determine, when the target row is a weak row, a mapping address corresponding to the target row in a reserved field in the DRAM according to an offset table and a preset starting address; the offset table comprises address offsets corresponding to weak lines in the DRAM in the reserved domain, and the preset starting address is the starting address of the reserved domain; the row pointed to by the address offset in the reserved field is not a weak row;

an accessing unit 630, configured to access the reserved domain according to the mapping address;

a returning unit 640 for returning the access result.

To sum up, in the memory access device provided in this embodiment, when the target row requested to be accessed is a weak row, the mapping address corresponding to the target row in the reserved field of the DRAM is calculated according to the pre-stored offset table and the preset starting address, and then the reserved field in the DRAM is accessed according to the mapping address, and the access result is returned; the rows pointed by the address offsets in the offset table in the reserved field are not weak rows, so that the access address of the weak row is converted when the weak row is requested to be accessed, so that the normal row in the DRAM can be accessed, the DRAM can be refreshed according to the normal refreshing period in the subsequent refreshing process, and the problems that in the related technology, the number of refreshing commands in the bus is large, the bus congestion is possibly caused, and the system performance is reduced are solved; the effects of avoiding bus congestion and improving performance are achieved.

Based on the memory access device provided in the foregoing embodiment, optionally, the returning unit 640 is further configured to:

receiving a return result which is returned by the DRAM and carries a first address, wherein the first address is an address accessed in the DRAM;

calculating a difference value between the first address and the preset starting address;

if the difference is larger than 0, calculating a second address corresponding to the first address according to the offset table and the preset starting address;

and returning the access result carrying the second address.

Optionally, the apparatus further comprises:

a first detection unit, configured to detect whether the target row is a row in a weak row list, where the weak row list includes each weak row in the DRAM;

the determining unit 620 is further configured to determine that the target row is a weak row when the detection result of the first detecting unit is that the target row is a row in a weak row list.

Optionally, the apparatus further comprises:

the second detection unit is used for detecting whether a unit with the maintaining time less than the preset time length is included in each row in the DRAM;

the determining unit 620 is further configured to determine the row as a weak row when the detection result of the second detecting unit is that the row includes a unit whose retention time is less than the preset duration;

and the first storage unit is used for generating and storing the weak row list according to the determination result.

Optionally, the apparatus further comprises:

the obtaining unit is used for obtaining the number of rows of weak rows in the DRAM and the size of each weak row before the determining unit determines the mapping address corresponding to the target row in the reserved field in the DRAM according to the offset table and the preset starting address;

the calculating unit is used for calculating the total size corresponding to each weak row in the DRAM according to the acquired row number and the size of each weak row;

a reservation unit, configured to reserve a storage space with a preset size in the DRAM as the reserved field, where the preset size is greater than or equal to the calculated total size;

and the second storage unit is used for storing the initial address of the reserved domain as the preset initial address.

Optionally, the apparatus further comprises:

the determining unit 620 is further configured to determine, before determining, according to an offset table and a preset starting address, a mapping address corresponding to the target row in a reserved field in the DRAM, an address offset corresponding to each weak row in the reserved field according to an ordering of each weak row in the DRAM;

a third holding unit that holds the offset table including the respective address offsets.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation.

It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the apparatuses and units described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units may be merely a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for memory access, the method comprising:

receiving a memory access request; the memory access request is used for requesting to access a target row in a Dynamic Random Access Memory (DRAM);

when the target row is a weak row, determining a mapping address corresponding to the target row in a reserved field in the DRAM according to an offset table and a preset starting address; the offset table comprises address offsets corresponding to weak lines in the DRAM in the reserved domain, and the preset starting address is the starting address of the reserved domain; the row pointed to by the address offset in the reserved field is not a weak row;

accessing the reserved domain according to the mapping address;

receiving a return result which is returned by the DRAM and carries a first address, wherein the first address is an accessed address in the DRAM;

and returning an access result carrying the second address.

2. The method of claim 1, further comprising:

detecting whether the target row is a row in a weak row list, wherein the weak row list comprises all weak rows in the DRAM;

if yes, determining that the target row is a weak row.

3. The method of claim 2, further comprising:

and generating and storing the weak row list according to the determination result.

4. The method of any of claims 1 to 3, wherein before determining the mapping address corresponding to the target row in the reserved field in the DRAM according to the offset table and the preset start address, the method further comprises:

reserving a storage space with a preset size in the DRAM as the reserved domain, wherein the preset size is larger than or equal to the total size obtained by calculation;

and saving the initial address of the reserved domain as the preset initial address.

5. The method of any of claims 1 to 3, wherein before determining the mapping address corresponding to the target row in the reserved field in the DRAM according to the offset table and the preset start address, the method further comprises:

determining the address offset corresponding to each weak row in the reserved field according to the sequence of each weak row in the DRAM;

maintaining the offset table including respective address offsets.

6. A memory access apparatus, the apparatus comprising:

a receiving unit, configured to receive a memory access request; the memory access request is used for requesting to access a target row in a Dynamic Random Access Memory (DRAM);

the determining unit is used for determining a mapping address corresponding to the target row in a reserved field in the DRAM according to an offset table and a preset starting address when the target row is a weak row; the offset table comprises address offsets corresponding to weak lines in the DRAM in the reserved domain, and the preset starting address is the starting address of the reserved domain; the row pointed to by the address offset in the reserved field is not a weak row;

the access unit is used for accessing the reserved domain according to the mapping address;

the receiving unit is further configured to receive a return result carrying a first address returned by the DRAM, where the first address is an address accessed in the DRAM;

the determining unit is further configured to calculate a difference between the first address and the preset starting address;

the determining unit is further configured to calculate a second address corresponding to the first address according to the offset table and the preset starting address if the difference is greater than 0;

and the return unit is used for returning the access result carrying the second address.

7. The apparatus of claim 6, further comprising:

the determining unit is further configured to determine that the target row is a weak row when the detection result of the first detecting unit is that the target row is a row in a weak row list.

8. The apparatus of claim 7, further comprising:

the determining unit is further configured to determine the row as a weak row when the detection result of the second detecting unit is that the row includes a unit whose retention time is less than the preset duration;

9. The apparatus of any of claims 6 to 8, further comprising:

10. The apparatus of any of claims 6 to 8, further comprising:

the determining unit is further configured to determine, according to an offset table and a preset starting address, an address offset corresponding to each weak row in a reserved field in the DRAM, before determining, according to the offset table and the preset starting address, a mapping address corresponding to the target row in the reserved field in the DRAM, and according to the ordering of each weak row in the DRAM;