CN108933173A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
CN108933173A
CN108933173A CN201710355400.8A CN201710355400A CN108933173A CN 108933173 A CN108933173 A CN 108933173A CN 201710355400 A CN201710355400 A CN 201710355400A CN 108933173 A CN108933173 A CN 108933173A
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China
Prior art keywords
contact hole
electrode
contact
dielectric layer
active area
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CN201710355400.8A
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Chinese (zh)
Inventor
吴健
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201710355400.8A priority Critical patent/CN108933173A/en
Priority to US15/951,033 priority patent/US10580694B2/en
Publication of CN108933173A publication Critical patent/CN108933173A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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    • H01L21/76841—Barrier, adhesion or liner layers
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention discloses a kind of semiconductor device and its manufacturing methods, are related to technical field of semiconductors.This method includes：Substrat structure is provided, substrat structure includes substrate, the active area on substrate, at least one electrode in active area and the interlevel dielectric layer at least covering active area and electrode, etching interlevel dielectric layer exposes the contact hole of electrode to be formed, conductive adhesive is formed in the bottom and side wall of contact hole, forms the contact of filling contact hole in conductive adhesive.The present invention is by forming conductive adhesive in contact hole bottom and side wall, so that active area electrode be avoided to will not be oxidized in contact forming process, thus can effectively reduce the contact impedance and barrier height of semiconductor device.

Description

Semiconductor device and its manufacturing method
Technical field
The present invention relates to technical field of semiconductors, in particular to semiconductor device and its manufacturing method.
Background technique
Fin formula field effect transistor (Fin Field-Effect Transistor, referred to as FinFET) is a kind of novel Complementary MOS (CMOS) transistor, have preferable short-channel effect control ability, higher driving current and Lower power consumption has low in energy consumption, the small advantage of area, is hopeful to continue Moore's Law, has begun 14 nanometers at present Node promotes.It is currently formed in fin formula field effect transistor in the technique of contact of active area, it is as shown in Figure 1A by removing Organic distribution layer 1 to expose active area electrode, as shown in Figure 1B.Wherein, semiconductor fin 21 is NFET, semiconductor fin 22 For PFET.Electrode 31 and electrode 33 are source electrode, and electrode 32 and electrode 34 are drain electrode.To which Fig. 2 can be seen that since etching can be led It causes the silicon in active area electrode to be oxidized, to form Si oxide 301,302,303 and 304, thus can bring higher connect Impedance and barrier height are touched, the quality of semiconductor device is thus reduced.
Summary of the invention
The inventors found that above-mentioned exist in the prior art problem, and therefore at least one in described problem A problem proposes new technical solution.
The first purpose of one embodiment of the invention is：A kind of manufacturing method of semiconductor device is provided.The present invention one The first purpose of embodiment is：A kind of semiconductor device is provided.By passing through interlevel dielectric layer to expose active area electrode Contact hole bottom and side wall on form conductive adhesive, to avoid active area electrode will not be by contact forming process Oxidation, thus can effectively reduce the contact impedance and barrier height of semiconductor device.
According to the first aspect of the invention, a kind of manufacturing method of semiconductor device is provided, is included the following steps：
Substrat structure is provided, substrat structure includes：
Substrate；
Active area on substrate；
At least one electrode in active area；And
At least cover the interlevel dielectric layer of active area and electrode；
Etching interlevel dielectric layer exposes the contact hole of electrode to be formed；
Conductive adhesive is formed in the bottom and side wall of contact hole；And
The contact of filling contact hole is formed in conductive adhesive.
In one embodiment, at least one electrode includes source electrode and drain electrode；
Contact hole includes：Expose the first contact hole of source electrode and exposes the second contact hole of drain electrode；
Contact includes：Fill the second contact of the second contact hole of the first connector and filling of the first contact hole.
In one embodiment, active area is semiconductor fin.
In one embodiment, contact hole includes the first part on electrode and second on first part Part, wherein the transverse width of first part is less than the transverse width of second part.
In one embodiment, etching interlevel dielectric layer includes the step of the contact hole for exposing electrode to be formed：
Interlevel dielectric layer is performed etching to form the opening for exposing electrode；
A part of the side wall of opening is performed etching, to form contact hole.
In one embodiment, substrat structure further includes：Gate structure on the active area, wherein source electrode and drain electrode point Not in gate structure two sides, interlevel dielectric layer covers gate structure.
In one embodiment, gate structure includes：Gate dielectric layer in a part of surfaces of active regions and Grid on gate dielectric layer.
In one embodiment, before forming contact, method further includes：
Sacrificial layer, sacrificial layer filling contact hole are formed on forming the substrat structure after conductive adhesive；
Sacrificial layer and interlevel dielectric layer are performed etching to form the connecting hole for exposing grid；And
Remove sacrificial layer.
In one embodiment, during forming contact, the connector with gate contact is formed in connecting hole.
According to another aspect of the present invention, a kind of semiconductor device is provided, including：
Substrat structure, substrat structure include：
Substrate；
Active area on substrate；
At least one electrode in active area；And
At least cover the interlevel dielectric layer of active area and electrode；
Expose the contact hole of electrode across interlevel dielectric layer；
Conductive adhesive in the bottom and side wall of contact hole；And
The contact that filling contact hole is formed in conductive adhesive.
In one embodiment, at least one electrode includes source electrode and drain electrode；
Contact hole includes：Expose the first contact hole of source electrode and exposes the second contact hole of drain electrode；
Contact includes：Fill the second contact of the second contact hole of the first connector and filling of the first contact hole.
In one embodiment, active area is semiconductor fin.
In one embodiment, contact hole includes the first part on electrode and second on first part Part, wherein the transverse width of first part is less than the transverse width of second part.
In one embodiment, substrat structure further includes：Gate structure on the active area, wherein source electrode and drain electrode point Not in gate structure two sides, interlevel dielectric layer covers gate structure.
In one embodiment, gate structure includes：Gate dielectric layer in a part of surfaces of active regions and Grid on gate dielectric layer.
In one embodiment, the connecting hole of grid is exposed across interlevel dielectric layer；
Fill the connector of connecting hole formation and gate contact.
By referring to the drawings to the detailed description of exemplary embodiment of the present invention, other feature of the invention and its Advantage will become apparent.
Detailed description of the invention
The attached drawing for constituting part of specification describes the embodiment of the present invention, and together with the description for solving Release the principle of the present invention.
The present invention can be more clearly understood according to following detailed description referring to attached drawing, wherein：
Figure 1A and Figure 1B is the stage in the manufacturing process of semiconductor device according to prior art that schematically shows Structural schematic diagram.
Fig. 2 is the schematic diagram for schematically showing manufacturing method for semiconductor device according to some embodiments of the invention.
Fig. 3 is the schematic diagram for schematically showing manufacturing method for semiconductor device according to some embodiments of the invention.
Fig. 4 A- Fig. 4 J is one in the manufacturing process for schematically show semiconductor device according to some embodiments of the invention The structural schematic diagram in a stage.
Specific embodiment
Carry out the various exemplary embodiments of detailed description of the present invention now with reference to attached drawing.It should be noted that：Unless in addition having Body explanation, the unlimited system of component and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally The range of invention.
Simultaneously, it should be appreciated that for ease of description, the size of various pieces shown in attached drawing is not according to reality Proportionate relationship draw.
Be to the description only actually of at least one exemplary embodiment below it is illustrative, never as to the present invention And its application or any restrictions used.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable In the case of, the technology, method and apparatus should be considered as authorizing part of specification.
It is shown here and discuss all examples in, any occurrence should be construed as merely illustratively, without It is as limitation.Therefore, the other examples of exemplary embodiment can have different values.
It should be noted that：Similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi It is defined in a attached drawing, then in subsequent attached drawing does not need that it is further discussed.
Fig. 2 is the schematic diagram for schematically showing manufacturing method for semiconductor device according to some embodiments of the invention.Its In, the method and step of the present embodiment includes：
Step 201, substrat structure is provided.
Wherein substrat structure includes：Substrate, the active area on substrate, at least one electrode in active area, And at least cover the interlevel dielectric layer of active area and electrode.
Optionally, active area is semiconductor fin.
Wherein, substrate can be silicon substrate, and the material of fin can be silicon.Interlevel dielectric layer can for silicon oxide layer or Silicon nitride layer.
Optionally, at least one above-mentioned electrode includes source electrode and drain electrode.
Step 202, etching interlevel dielectric layer is to form the contact hole for exposing electrode.
Optionally, contact hole includes：Expose the first contact hole of source electrode and exposes the second contact hole of drain electrode.
Wherein, in each contact hole, contact hole may include first part on respective electrode and be located at first / on second part, wherein the transverse width of first part be less than second part transverse width.
Optionally, above-mentioned etching interlevel dielectric layer includes the step of the contact hole for exposing electrode to be formed：First to layer Between dielectric layer perform etching with formed expose electrode opening, then a part of the side wall of opening is performed etching again, with Just contact hole is formed.
Since the transverse width on contact hole top is extended, so that the performance of semiconductor devices can be improved.
Step 203, conductive adhesive is formed in the bottom and side wall of contact hole.
Wherein, conductive adhesive can be formed in the bottom and side wall of the first contact hole and the second contact hole, so as to source Pole and drain electrode are protected.
Step 204, the contact of filling contact hole is formed in conductive adhesive.
Optionally, contact includes the second contact for filling the second contact hole of the first connector and filling of the first contact hole Part.
The present invention is passing through interlevel dielectric layer by handling substrat structure to expose the contact of active area electrode Conductive adhesive is formed in the bottom and side wall of hole, so that active area electrode is avoided to will not be oxidized in contact forming process, Thus the contact impedance and barrier height of semiconductor device be can effectively reduce.
Optionally, substrat structure may also include：Gate structure on the active area, wherein source electrode and drain electrode is respectively in grid Pole structure two sides, interlevel dielectric layer cover gate structure.
Wherein, gate structure includes：Gate dielectric layer in a part of surfaces of active regions and in gate-dielectric Grid on layer.
Fig. 3 is the schematic diagram for schematically showing manufacturing method for semiconductor device according to some embodiments of the invention.Its In, the method and step of the present embodiment includes：
Step 301, substrat structure is provided.
Wherein substrat structure includes：Substrate, the active area on substrate, at least one electrode in active area, At least cover the interlevel dielectric layer of active area and electrode, and gate structure on the active area.
Step 302, etching interlevel dielectric layer is to form the contact hole for exposing electrode.
Optionally, contact hole includes：Expose the first contact hole of source electrode and exposes the second contact hole of drain electrode.
Wherein, in each contact hole, contact hole may include first part on respective electrode and be located at first / on second part, wherein the transverse width of first part be less than second part transverse width.
Step 303, conductive adhesive is formed in the bottom and side wall of contact hole.
Wherein, conductive adhesive can be formed in the bottom and side wall of the first contact hole and the second contact hole, so as to source Pole and drain electrode are protected.
Step 304, sacrificial layer, sacrificial layer filling contact hole are formed on forming the substrat structure after conductive adhesive.
Step 305, sacrificial layer and interlevel dielectric layer are performed etching to form the connecting hole for exposing grid.
Step 306, sacrificial layer is removed.
Step 307, the contact that filling contact hole is formed in conductive adhesive, formation and gate contact in connecting hole Connector.
Below by a specific example, the present invention will be described.
As shown in Figure 4 A, substrat structure is provided.Wherein substrat structure includes substrate 40 and the active area on substrate 40, And at least cover the interlevel dielectric layer of active area and electrode.Wherein, active area can be two fins on substrate 40 51 and 61, wherein fin 51 is NFET, and fin 61 is PFET.It is equipped with source electrode 52 and drain electrode 53 in fin 51, is equipped in fin 61 Source electrode 62 and drain electrode 63.In addition, substrat structure may also include gate structure on the active area.As shown in Figure 4 A, 52 He of source electrode Respectively in gate structure two sides, interlevel dielectric layer covers gate structure for drain electrode 53.
Wherein, gate structure may include：Gate dielectric layer in a part of surfaces of active regions and it is situated between in grid electricity Grid on matter layer.As shown in Figure 4 A, gate structure includes grid 71, work function regulating course 72, high-k dielectric layer 73, interval Object 74 and gate insulating layer 75.
Optionally, substrat structure may also include the first insulant 41 and the second insulant 42, also set in source electrode and drain electrode There is dielectric layer 43, and covers the dielectric layer 44 of active area source electrode, drain electrode, dielectric layer 43, gate structure.
As shown in Figure 4 B, hard mask layer 45 is formed on substrat structure.
As shown in Figure 4 C, hard mask layer 45 is patterned, to be formed across hard mask layer 45 and layer part dielectric Layer and the contact hole 54 for exposing source electrode and drain electrode.
As shown in Figure 4 D, hard mask layer 45 is removed.The conductive adhesive formed in the bottom and side wall of contact hole simultaneously 46。
Optionally, in figure 4 c, etching interlevel dielectric layer may include the step of the contact hole for exposing electrode to be formed：It is first First to interlevel dielectric layer perform etching with formed expose electrode opening, then again to a part of the side wall of the opening into Row etching, to form contact hole.To which contact hole includes first part on electrode and on first part Second part, wherein the transverse width of first part is less than the transverse width of second part.As shown in Figure 4 D.
As shown in Figure 4 E, sacrificial layer 47 is formed on forming the substrat structure after conductive adhesive 46, which fills out Fill contact hole.
Wherein, sacrificial layer 47 can be organic distribution layer.
As illustrated in figure 4f, exposure mask is formed on sacrificial layer 47.Wherein, exposure mask may include anti-reflecting layer 48 and photoresist 49. By being performed etching to photoresist 49, anti-reflecting layer 48 and sacrificial layer 47 to form the connecting hole 76 for exposing grid.
As shown in Figure 4 G, photoresist 49 and anti-reflecting layer 48 are removed.
As shown at figure 4h, sacrificial layer 47 is removed.It should be noted that since the present invention is in advance in the bottom of contact hole and side Conductive adhesive 46 is formed on wall, therefore avoids silicon from being oxidized in etching sacrificial layer 47.To which semiconductor device be effectively reduced Contact impedance and barrier height.
As shown in fig. 41, conductive material layer 80 is formed on substrat structure with filling contact hole 54 and connecting hole 76.
As shown in fig. 4j, corresponding with source electrode to obtain by carrying out chemical mechanical polish process to conductive material layer 80 The first contact 81 and corresponding second contact 82 of drain electrode, connector 83 corresponding with grid.
The present invention also provides a kind of semiconductor devices, and as shown in fig. 4j, wherein semiconductor device includes substrat structure, substrate Structure includes substrate, the active area on substrate, at least one electrode in active area, and at least covers active area With the interlevel dielectric layer of electrode.
Wherein, active area can be semiconductor fin.
Optionally, at least one above-mentioned electrode includes source electrode and drain electrode.
The semiconductor device further includes the contact hole across interlevel dielectric layer to expose electrode, contact hole bottom and Conductive adhesive 46 on side wall, and the contact 81,82 that filling contact hole is formed in conductive adhesive.
Wherein, contact hole includes the first contact hole for exposing source electrode and the second contact hole for exposing drain electrode, and contact includes Fill the second contact of the second contact hole of the first connector and filling of the first contact hole.
Optionally, contact hole includes the first part on electrode and the second part on first part, The transverse width of middle first part is less than the transverse width of second part, as shown in Figure 4 D.
Optionally, substrat structure further includes：Gate structure on the active area, wherein source electrode and drain electrode is respectively in grid Structure two sides, interlevel dielectric layer cover gate structure.Wherein, gate structure may include：In a part of surfaces of active regions Gate dielectric layer and the grid on gate dielectric layer, as shown in Figure 4 A.
Optionally, which may also include the connecting hole for exposing grid across interlevel dielectric layer, such as Fig. 4 F It is shown.And the connector with gate contact is formed by filling connecting hole, as shown in fig. 4j.
The present invention by pass through interlevel dielectric layer with expose active area electrode contact hole bottom and side wall on formed Thus conductive adhesive can effectively reduce and partly lead so that active area electrode be avoided to will not be oxidized in contact forming process The contact impedance and barrier height of body device.
So far, the method for manufacturing semiconductor devices according to the present invention is described in detail and is formed by semiconductor device Part.In order to avoid covering design of the invention, some details known in the field are not described.Those skilled in the art according to Above description, completely it can be appreciated how implementing technical solution disclosed herein.
Although some specific embodiments of the invention are described in detail by example, the skill of this field Art personnel it should be understood that above example merely to being illustrated, the range being not intended to be limiting of the invention.The skill of this field Art personnel are it should be understood that can without departing from the scope and spirit of the present invention modify to above embodiments.This hair Bright range is defined by the following claims.

Claims (16)

1. a kind of manufacturing method of semiconductor device, which is characterized in that include the following steps：
Substrat structure is provided, the substrat structure includes：
Substrate；
Active area on the substrate；
At least one electrode in the active area；And
At least cover the interlevel dielectric layer of the active area and the electrode；
The interlevel dielectric layer is etched to form the contact hole for exposing the electrode；
Conductive adhesive is formed in the bottom and side wall of the contact hole；And
The contact for filling the contact hole is formed in the conductive adhesive.
2. the method as described in claim 1, which is characterized in that
At least one described electrode includes source electrode and drain electrode；
The contact hole includes：Expose the first contact hole of the source electrode and exposes the second contact hole of the drain electrode；
The contact includes：It fills the first connector of first contact hole and fills the second of second contact hole and connect Contact element.
3. the method as described in claim 1, which is characterized in that
The active area is semiconductor fin.
4. the method as described in claim 1, which is characterized in that
The contact hole includes the first part on the electrode and the second part on first part, wherein institute The transverse width for stating first part is less than the transverse width of the second part.
5. method as claimed in claim 4, which is characterized in that
Etch the interlevel dielectric layer includes the step of the contact hole for exposing the electrode to be formed：
The interlevel dielectric layer is performed etching to form the opening for exposing the electrode；
A part of the side wall of the opening is performed etching, to form contact hole.
6. method according to claim 2, which is characterized in that
The substrat structure further includes：Gate structure on the active area, wherein the source electrode and the drain electrode exist respectively The gate structure two sides, the interlevel dielectric layer cover the gate structure.
7. method as claimed in claim 6, which is characterized in that
The gate structure includes：Gate dielectric layer in a part of the surfaces of active regions and it is situated between in the grid electricity Grid on matter layer.
8. the method for claim 7, which is characterized in that
Before forming the contact, the method also includes：
Sacrificial layer is formed on forming the substrat structure after the conductive adhesive, the sacrificial layer fills the contact hole；
The sacrificial layer and the interlevel dielectric layer are performed etching to form the connecting hole for exposing the grid；And
Remove the sacrificial layer.
9. method according to claim 8, which is characterized in that
During forming contact, the connector with the gate contact is formed in the connecting hole.
10. a kind of semiconductor device, which is characterized in that including：
Substrat structure, the substrat structure include：
Substrate；
Active area on the substrate；
At least one electrode in the active area；And
At least cover the interlevel dielectric layer of the active area and the electrode；
Expose the contact hole of the electrode across the interlevel dielectric layer；
Conductive adhesive in the bottom and side wall of the contact hole；And
The contact that the contact hole is formed is filled in the conductive adhesive.
11. device as claimed in claim 10, which is characterized in that
At least one described electrode includes source electrode and drain electrode；
The contact hole includes：Expose the first contact hole of the source electrode and exposes the second contact hole of the drain electrode；
The contact includes：It fills the first connector of first contact hole and fills the second of second contact hole and connect Contact element.
12. device as claimed in claim 10, which is characterized in that
The active area is semiconductor fin.
13. device as claimed in claim 10, which is characterized in that
The contact hole includes the first part on the electrode and the second part on first part, wherein institute The transverse width for stating first part is less than the transverse width of the second part.
14. device as claimed in claim 11, which is characterized in that
The substrat structure further includes：Gate structure on the active area, wherein the source electrode and the drain electrode exist respectively The gate structure two sides, the interlevel dielectric layer cover the gate structure.
15. device as claimed in claim 14, which is characterized in that
The gate structure includes：Gate dielectric layer in a part of the surfaces of active regions and it is situated between in the grid electricity Grid on matter layer.
16. device as claimed in claim 15, which is characterized in that further include：
Expose the connecting hole of the grid across the interlevel dielectric layer；
Fill the connector of the connecting hole formation and the gate contact.
CN201710355400.8A 2017-05-19 2017-05-19 Semiconductor device and its manufacturing method Pending CN108933173A (en)

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