CN108933129B

CN108933129B - Semiconductor device with a plurality of semiconductor chips

Info

Publication number: CN108933129B
Application number: CN201810488728.1A
Authority: CN
Inventors: 田中英俊
Original assignee: Socionext Inc
Current assignee: Socionext Inc
Priority date: 2017-05-25
Filing date: 2018-05-21
Publication date: 2023-01-31
Anticipated expiration: 2038-05-21
Also published as: CN108933129A; US10483348B2; US20200044017A1; JP2018200916A; JP6841161B2; US20180342575A1; US10971581B2

Abstract

The invention provides a semiconductor device having an ESD protection circuit capable of suppressing generation of EM. The semiconductor device includes: a substrate; a first transistor formed on the substrate and having a first impurity region and a second impurity region of a first conductivity type; a first guard ring formed on the substrate, located at a position surrounding the first transistor in a plan view, and having a second conductivity type different from the first conductivity type; a first wiring formed on the first guard ring and electrically connected to the first guard ring; and a ground wiring formed on the first wiring and electrically connected to the first wiring and the second impurity region, wherein the first transistor includes a first portion spaced from the first guard ring by a first distance in a plan view, and a second portion spaced from the first guard ring by a second distance shorter than the first distance in the plan view, the first portion is located at a position distant from the ground wiring in the plan view, and the second portion is located at a position overlapping the ground wiring in the plan view.

Description

Semiconductor device with a plurality of semiconductor chips

Technical Field

The present invention relates to a semiconductor device.

Background

In a semiconductor device, it is known to provide an electrostatic Discharge (ESD) protection circuit between a power supply terminal (VDD) and a ground terminal (VSS).

For example, a semiconductor device including an ESD protection circuit surrounded by a guard ring to which a ground wiring is connected can be cited (see, for example, patent documents 1 and 2).

Patent document 1: japanese laid-open patent publication No. 2012-43845

Patent document 2: japanese unexamined patent publication No. 2014-154595

In addition, with the recent miniaturization of semiconductor devices, reliability failure of metal wiring due to Electromigration (EM) has become a problem. Since EM is a phenomenon generated by a current flowing through a metal wiring, there is a possibility that EM is generated in the metal wiring by an ESD current flowing through the metal wiring. However, a semiconductor device including an ESD protection circuit in which generation of EM is taken into consideration is not known.

Disclosure of Invention

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device including an ESD protection circuit capable of suppressing the generation of EM.

The semiconductor device includes: a substrate; a first transistor formed on the substrate and having a first impurity region and a second impurity region of a first conductivity type; a first guard ring formed on the substrate, located at a position surrounding the first transistor in a plan view, and having a second conductivity type different from the first conductivity type; a first wiring formed on the first guard ring and electrically connected to the first guard ring; and a ground wiring formed on the first wiring and electrically connected to the first wiring and the second impurity region, wherein the first transistor includes a first portion spaced from the first guard ring by a first distance in a plan view, and a second portion spaced from the first guard ring by a second distance shorter than the first distance in the plan view, the first portion is located apart from the ground wiring in the plan view, and the second portion is located to overlap the ground wiring in the plan view.

According to the disclosed technology, a semiconductor device provided with an ESD protection circuit capable of suppressing the generation of EM is provided.

Drawings

Fig. 1 is a circuit diagram of a semiconductor device according to a first embodiment.

Fig. 2 is a plan view illustrating the structure of the semiconductor device according to the first embodiment.

Fig. 3 is a plan view of a portion a of fig. 2.

Fig. 4 isbase:Sub>A sectional view taken along linebase:Sub>A-base:Sub>A of fig. 3.

Fig. 5 is a sectional view taken along line B-B of fig. 3.

Fig. 6 is a sectional view taken along line C-C of fig. 3.

Fig. 7 is a sectional view taken along line D-D of fig. 3.

Fig. 8 is a plan view corresponding to fig. 3 of the semiconductor device according to modification 1 of the first embodiment.

Fig. 9 isbase:Sub>A sectional view taken along linebase:Sub>A-base:Sub>A of fig. 8.

Fig. 10 is a sectional view taken along line B-B of fig. 8.

Fig. 11 is a sectional view taken along line C-C of fig. 8.

Fig. 12 is a sectional view taken along line D-D of fig. 8.

Fig. 13 isbase:Sub>A cross-sectional view taken along linebase:Sub>A-base:Sub>A of fig. 8 in the case where the semiconductor device 1 isbase:Sub>A nanowire FET.

Fig. 14 is a cross-sectional view taken along the line B-B of fig. 8 in the case where the semiconductor device 1 is a nanowire FET.

Fig. 15 is a diagram illustrating the arrangement of VDD wiring, VSS wiring, and the like.

Fig. 16 is a plan view illustrating the structure of modification 3 of the first embodiment.

Fig. 17 is a plan view illustrating the structure of the semiconductor device according to the second embodiment.

Fig. 18 is a circuit diagram of a semiconductor device according to a third embodiment.

Fig. 19 is a plan view illustrating the structure of the semiconductor device according to the third embodiment.

Fig. 20 is a circuit diagram (1 thereof) of the other subject circuit.

Fig. 21 is a plan view illustrating the structure of the semiconductor device shown in fig. 20.

Fig. 22 is a circuit diagram of the other subject circuit (2 thereof).

Fig. 23 is a plan view illustrating the structure of the semiconductor device shown in fig. 22.

Fig. 24 is a circuit diagram of other subject circuits (3 thereof).

Fig. 25 is a plan view illustrating the structure of the semiconductor device shown in fig. 24.

Fig. 26 is a plan view illustrating the structure of the semiconductor device according to the fourth embodiment.

Description of the symbols

1. 1A, 1B, 1C, 1D … semiconductor devices; 11. 12 … NMOS; 21. 22 … PMOS; 111. 112, 121, 122, 211, 212, 221, 222 … impurity region; 113. 123, 213, 223 … gate electrodes; 113D, 123D … gate electrode configurations; 115 … nanowire; 117. 217 … guard ring; 130 … substrate; 131 … P-Well;132 … STI;133 … silicide layer; 134 … a gate insulating film; 135 … barrier film; 136. 137, 138 … interlayer insulating films; 151. 154 …; 152 … VDD wiring; 153 … VSS wiring; 170 … I/O unit

Detailed Description

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and overlapping description may be omitted. In addition, in the present application, the first conductivity type is N type or P type, and the second conductivity type is P type or N type of a conductivity type opposite to the first conductivity type.

First embodiment

Fig. 1 is a circuit diagram of a semiconductor device according to a first embodiment. As shown in fig. 1, the semiconductor device 1 has an NMOS11 (first transistor), wherein the NMOS11 is an N-type Field Effect Transistor (FET). The NMOS11 is connected between VDD and VSS. The ESD trigger circuit C11 is connected to the gate electrode 113 of the NMOS11. D11 is a parasitic diode.

The ESD trigger circuit C11 detects an ESD surge, and turns on the NMOS11 during the surge generation time. This can protect the protection target circuit connected between VDD and VSS from ESD surge. Further, the protection target circuit may be all circuits connected between VDD and VSS.

In the first embodiment, the following description will be given taking a case where the semiconductor device 1 is a planar FET as an example.

As shown in fig. 1 and 2, in the semiconductor device 1, the N-type impurity region 111 (first impurity region) of the NMOS11 is electrically connected to VDD (power supply terminal) via a VDD interconnection 152. The N-type impurity region 112 (second impurity region) of the NMOS11 is electrically connected to VSS (ground terminal) via a VSS wiring 153. N-type impurity regions 111 of NMOS11 arranged in the Y direction are electrically connected to each other via a wiring 151.

The

impurity regions

111 and 112 and the gate electrode 113 of the NMOS11 are surrounded by a guard ring 117 (first guard ring) which is a P-type impurity region. Guard ring 117 is connected to VSS wiring 153 via wiring 154 of metal wiring layer M1 disposed on guard ring 117. The wiring 154 is arranged to surround the NMOS11 in a plan view.

In fig. 2, the via hole V0 disposed in the guard ring 117, the wiring of the wiring layer M1 for electrically connecting the impurity regions 112 to each other, and the wiring of the wiring layer M1 for electrically connecting the gate electrodes 113 to each other are omitted.

In the present application, the guard ring is an impurity region formed in the substrate and surrounds the transistor and the circuit. However, the impurity region may be discontinuous so as to surround the transistor or the circuit as in the case of a FinFET or a nanowire FET described later.

In the semiconductor device 1, the distance W2 or W3 between the guard ring 117 (which is a first portion) below the VSS wiring 153 and the impurity region 111 of the NMOS11 is narrower than the distance W1 between a portion different from the first portion of the guard ring 117 and the impurity region 111 of the NMOS11.

If ESD current flows from VSS to VDD in a configuration in which no difference is provided between W1, W2, and W3, the ESD current flows below VSS wiring 153 and then reaches VDD via wiring 154 of metal wiring layer M1, and therefore EM may be generated in wiring 154.

In the semiconductor device 1, since the interval W2 or W3 is narrower than the interval W1, the ESD current flows more easily in the portion of the interval W2 or W3 having a lower resistance than in the portion of the interval W1 having a higher resistance. This can suppress the ESD current from flowing through the wiring 154 on the guard ring 117, and can suppress the occurrence of EM in the wiring 154 due to the ESD current.

In fig. 2, an example in which 4-segment NMOS11 is arranged in the Y direction in the guard ring 117 is shown as an example, but the present invention is not limited to this.

The layout of the semiconductor device 1 will be described in more detail below. Fig. 3 is a plan view of a portion a of fig. 2. Fig. 4 isbase:Sub>A sectional view taken along linebase:Sub>A-base:Sub>A of fig. 3. Fig. 5 is a sectional view taken along line B-B of fig. 3. Fig. 6 is a sectional view taken along line C-C of fig. 3. Fig. 7 is a sectional view taken along line D-D of fig. 3.

Referring to fig. 3 to 7, in the semiconductor device 1, a P-Well131 containing a P-type impurity, an STI132 (Shallow Trench Isolation), N-

type impurity regions

111 and 112, a P-type guard ring 117, and the like are formed on a substrate 130 made of an N-type semiconductor. A wiring 154 is formed on the guard ring 117. The wiring 154 is connected to the grommet 117 via a via hole V0. In addition, when the substrate 130 has a P-type conductivity, the formation of the P-Well131 may be omitted.

A silicide layer 133 made of, for example, nickel silicide or cobalt silicide is formed on the surfaces of the

impurity regions

111 and 112 and the guard ring 117. The STI132 is formed of, for example, a silicon oxide film. In the figure, a region where the concentration of the P-type impurity of P + is higher than that of the P-type impurity of P-Well is shown, and a region where the concentration of the N-type impurity of N + is higher than that of the N-Well is shown.

A gate electrode 113 is formed in a region between the impurity region 111 and the impurity region 112 on the substrate 130 via a gate insulating film 134. The gate electrode 113 can be formed of, for example, polysilicon. The gate electrode 113 may have a metal such as titanium nitride. The gate insulating film 134 can be formed of, for example, a silicon oxide film. The gate insulating film 134 may have an oxide of hafnium, zirconium, lanthanum, yttrium, aluminum, titanium, or tantalum.

An isolation film 135 made of, for example, a silicon oxide film, a silicon nitride film, or the like is provided on the side surfaces of the gate insulating film 134 and the gate electrode 113. The silicide layer 133, the isolation film 135, and the gate electrode 113 are covered with an interlayer insulating film 136.

The metal wiring layer M1 is connected to the

impurity regions

111 and 112, the guard ring 117, and the like via a via hole V0 provided in the interlayer insulating film 136. The side surface of the metal wiring layer M1 is covered with an interlayer insulating film 137. The upper surface of the metal wiring layer M1 is covered with an interlayer insulating film 138.

The metal wiring layer M2 is connected to the metal wiring layer M1 via a via hole V1 provided in the interlayer insulating film 138. The side surface of the metal wiring layer M2 is covered with an interlayer insulating film 138.

The metal wiring layers M1 and M2 and the via hole V1 can be formed of, for example, tantalum nitride, a barrier metal film of tantalum, copper, or the like. The via hole V0 can be formed of, for example, a titanium nitride adhesive film, a tungsten film, or the like. The metal wiring layer M1 can be, for example, a single damascene structure. The metal wiring layer M2 and the via hole V1 can be, for example, a dual damascene structure.

The interlayer insulating film 136 can be formed, for example, by a silicon oxide film or the like. The

interlayer insulating films

137 and 138 can be formed of a low dielectric constant material such as SiOC (carbon-added silicon oxide) or a porous film.

Further, the wiring 154 is included in the metal wiring layer M1, and the VDD wiring 152 and the VSS wiring 153 are included in the metal wiring layer M2. Hereinafter, fig. 3 to 7 will be described in more detail.

As shown in fig. 3, below the VSS wiring 153, the distance between the guard ring 117 and the impurity region 111 of the NMOS11 is W2, and the distance between the guard ring 117 and the impurity region 111 of the NMOS11 in the other portion is W1, which is larger than the distance W2.

In addition, the density in the extending direction (Y direction in fig. 3) of the guard rings 117 of the via holes V0 at the positions overlapping with the VSS wiring 153 in a plan view may be higher than the density in the extending direction of the guard rings 117 of the via holes V0 at the positions not overlapping with the VSS wiring 153 in a plan view. This makes it possible to easily flow the ESD current to the guard ring 117 below the VSS wiring 153. However, the density in the extending direction of the guard ring 117 of the via hole V0 at the position overlapping with the VSS wiring 153 in a plan view may be the same as the density in the extending direction of the guard ring 117 of the via hole V0 at the position not overlapping with the VSS wiring 153 in a plan view. The density here means the number of via holes V0 arranged per unit length extending in a fixed direction in a plan view.

As shown in fig. 3, the distance between the guard ring 117 and the NMOS11 may be gradually increased as the distance from the VSS wiring 153 increases. That is, the distance from the guard ring 117 may be gradually increased between a portion of the NMOS11 at a narrow distance from the guard ring 117 (a portion at the distance W2) and a portion at a wide distance from the guard ring 117 (a portion at the distance W1).

By being configured in this way, the effect of EM suppression is obtained and the number of NMOS within the guard ring 117 can be increased, and the performance (e.g., driving capability, ESD protection capability) of the semiconductor device 1 can be improved.

As shown in fig. 3, one of the wirings 151 may be connected to the impurity region 111 at a position overlapping with the VSS wiring 153 in a plan view, and may be connected to the VDD wiring 152 at a position not overlapping with the impurity region 111 in a plan view (for example, on the STI132 between the guard ring 117 and the impurity region 112).

Fig. 3 is an enlarged view of the right portion of fig. 2, but the same configuration may be applied to the left portion of fig. 2.

In fig. 3, a wiring of the wiring layer M1 extending in the Y direction is shown, in which the impurity region 112 and the VSS wiring 153 are electrically connected, and the plurality of impurity regions 112 are electrically connected to each other. In addition, the wiring of the wiring layer M1, which electrically connects the plurality of gate electrodes 113 to each other and extends in the Y direction, is illustrated.

As shown in FIGS. 4 and 5, since the distance W1 is larger than the distance W2, the resistance value of P-Well131 below the STI132 of FIG. 4 (above the arrow of W1) is larger than the resistance value of P-Well131 below the STI132 of FIG. 5 (above the arrow of W2). Note that the resistance marks in the portion of P-Well131 in fig. 4 schematically show a large resistance value (the same applies to the other figures).

As shown in fig. 6 and 7, the wires 151 of the metal wiring layer M1 are connected to the impurity regions 111 of the NMOS11 through the via holes V0. The wiring 151 extends in the Y direction from below the VSS wiring 153 to below the VDD wiring 152 across the STI132 in the region where the NMOS11 is not arranged, and is connected to the VDD wiring 152 via the via hole V1.

In fig. 4 to 7, VDD wiring 152 and VSS wiring 153 are arranged in metal wiring layer M2, but may be arranged in a metal wiring layer above metal wiring layer M2.

As described above, in the semiconductor device 1 according to the first embodiment, the portion having a wide space (the portion having the space W1) from the guard ring 117 in a plan view is located at a position separated from the VSS wiring 153 (not overlapping in a plan view), and the portion having a narrow space (the portion having the space W2 or W3) is located at a position overlapping the VSS wiring 153 in a plan view. Accordingly, the ESD current flows more easily in the portion of the interval W2 or W3 having a lower resistance than in the portion of the interval W1 having a higher resistance. As a result, the ESD current can be suppressed from flowing through the wiring 154 on the guard ring 117, and the generation of EM in the wiring 154 due to the ESD current can be suppressed.

In addition, the density in the extending direction (Y direction in fig. 3) of the guard rings 117 of the via holes V0 at the positions overlapping with the VSS wiring 153 in a plan view may be higher than the density in the extending direction of the guard rings 117 of the via holes V0 at the positions not overlapping with the VSS wiring 153 in a plan view. Accordingly, the ESD current easily flows below the VSS wiring 153, and therefore, the occurrence of EM on the wiring 154 due to the ESD current can be further suppressed.

Further, the distance between the guard ring 117 and the NMOS11 may be gradually increased as being separated from the VSS wiring 153. By having such a configuration, the effect of EM suppression is obtained, and the number of NMOS in the guard ring 117 can be increased, and the performance (e.g., drive capability, ESD protection capability) of the semiconductor device 1 can be improved.

In the present embodiment, the NMOS11 is provided between VSS and VDD, but the NMOS11 may be provided between the input/output signal terminal (PAD) and VSS instead of VDD, for example.

Modification 1 of the first embodiment

In modification 1 of the first embodiment, an example is shown in the case where the semiconductor device 1 is a field effect transistor having a channel in the shape of a FIN (FIN). Note that, in modification 1 of the first embodiment, description of the same components as those of the already described embodiment may be omitted.

Fig. 8 is a plan view corresponding to fig. 3. Fig. 9 isbase:Sub>A sectional view taken along linebase:Sub>A-base:Sub>A of fig. 8. Fig. 10 is a sectional view taken along line B-B of fig. 8. Fig. 11 is a sectional view taken along line C-C of fig. 8. Fig. 12 is a sectional view taken along line D-D of fig. 8.

As shown in fig. 8, the basic configuration is the same as the case of fig. 3. However, in the case where the semiconductor device 1 is a FinFET, unlike the case of a planar FET, a plurality of fins (Fin) extending in the X direction are arranged in the Y direction in the NMOS11. The gate electrode 113 and the local interconnect L0 are formed across a plurality of fins in the Y direction.

In fig. 8, the dummy gate electrode structure 113D is formed on the terminal of the Fin (Fin), but this is not essential, and the dummy gate electrode structure 113D may not be formed.

The grommet 117 is also formed of a fin. When the semiconductor device 1 is a planar FET, the guard ring 117 is one (see fig. 2 and the like), but when the semiconductor device 1 is a FinFET, the guard ring 117 is an aggregate of separated fins.

In the example of fig. 8, the number of fins is four, but the number of fins may be one or a plurality of fins other than four.

In addition, as in the case of fig. 3, the NMOS11 may have the same configuration as that of fig. 8 on both right and left sides in a plan view.

As shown in fig. 9 and 10, the fins are formed by patterning a semiconductor substrate, for example, and impurity regions corresponding to the source and drain of each transistor are formed by ion implantation. The fin and the wiring of the metal wiring layer M1 are connected via the local wiring L0 and the via hole V0 in the local wiring L0. Further, the gate electrode 113 also has a portion where the local wiring L0 is formed, and a via hole 0 and a metal wiring layer M1 (not shown) are formed thereon. Further, the via hole V0 and the wiring of the metal wiring layer M1 can be, for example, a dual damascene structure. In this case, the via hole V0 and the wiring of the metal wiring layer M1 can be formed of, for example, tantalum nitride, a barrier metal film of tantalum, copper, or the like. The local interconnect L0 can be formed of, for example, a titanium nitride glue film, a tungsten film, or the like.

As shown in fig. 11 and 12, the basic cross-sectional structure from the metal wiring layer M1 to the metal wiring layer M2 is the same as that in fig. 6 and 7. However, unlike the case where the semiconductor device 1 is a planar FET, the portion constituting the source-drain of the transistor has a fin shape protruding from the substrate 130.

In this way, even when the semiconductor device 1 is a FinFET, by providing a difference in the intervals W1, W2, and W3 as in the first embodiment, the ESD current flows more easily in the portion of the interval W2 or W3 where the resistance is low than in the portion of the interval W1 where the resistance is high. As a result, the ESD current can be suppressed from flowing through the wiring 154 on the guard ring 117, and the generation of EM in the wiring 154 due to the ESD current can be suppressed.

Further, as in the first embodiment, the arrangement density of the via holes 0 in the direction in which the guard ring 117 extends may be made higher below the VSS wiring 153 and lower at a portion different from the portion below the VSS wiring 153. In addition, the interval between the guard ring 117 and the NMOS11 may be gradually increased as being distant from the VSS wiring 153. In these cases, the same effects as those of the first embodiment are obtained.

Modification 2 of the first embodiment

In modification 2 of the first embodiment, an example is shown in which the semiconductor device 1 is a nanowire FET. Note that, in modification 2 of the first embodiment, description of the same components as those of the already described embodiment may be omitted.

Since the plan view is the same as that of fig. 8, illustration is omitted. Fig. 13 isbase:Sub>A cross-sectional view taken along the linebase:Sub>A-base:Sub>A of fig. 8 in the case where the semiconductor device 1 isbase:Sub>A nanowire FET. Fig. 14 is a cross-sectional view taken along line B-B of fig. 8 in the case where the semiconductor device 1 is a nanowire FET.

As shown in fig. 13 and 14, the basic cross-sectional structure is the same as that in fig. 9 and 10.

However, when the semiconductor device 1 is a nanowire FET, the channel portion of the FinFET is linear, and a gate insulating film and a gate electrode are formed so as to surround the channel.

The relationship between the spaces W1 and W2, the number of via holes in the guard ring, the structure of the guard ring gradually separated from the guard ring, and the arrangement of the wiring layers are basically the same as those in the first embodiment and modification 1.

The nanowire 115 shown in fig. 13 and 14 is a thin wire through which current flows, and both ends of the wire are connected to a plate-like structure including portions to be the source region and the drain region of the nanowire FET. The nanowire 115 is formed of a semiconductor material such as silicon, germanium, or a mixture thereof, and serves as a channel of a transistor. The number of nanowires 115 can be arbitrarily determined. At least a portion overlapping with the gate electrode 113 is of a different conductivity type from the source-drain, or is not implanted with impurities.

The number of nanowires 115 in the Z direction shown in fig. 13 and 14 is 2, but may be one or more than 3. As shown in fig. 8, the number of nanowires 115 in the NMOS11 in the Y direction is four, but one nanowire may be used, or a plurality of nanowires other than four may be used.

In the examples of fig. 13 and 14, the guard ring 117 has a structure without a nanowire (a plate-like structure similar to a FinFET), but a nanowire structure may be formed as needed. Note that, the portion functioning as a transistor is not limited to the NMOS11 and guard ring 117 in the present application, and a plate-like structure similar to a FinFET may be formed in other regions. Specifically, in a semiconductor device including a nanowire FET, for example, a well tap region for supplying a potential to a substrate or a well may be configured to have a plate shape. Since the area connected to the substrate is larger in the plate-like structure than in the nanowire structure such as the nanowire FET, the resistance can be reduced in the region connected to the substrate by adopting such a structure as compared with the case where all the structures are the same as the nanowire FET.

As described above, even in the case where the semiconductor device 1 is a nanowire FET, differences are provided in the intervals W1, W2, and W3 as in the first embodiment, and thus ESD current flows more easily in the portion of the interval W2 or W3 having a lower resistance than in the portion of the interval W1 having a higher resistance. As a result, the ESD current can be suppressed from flowing through the wiring on the guard ring 117, and the generation of EM in the wiring 154 due to the ESD current can be suppressed.

As in the first embodiment, the arrangement density of the via holes 0 in the direction in which the guard ring 117 extends may be set higher below the VSS wiring 153 and lower in a portion different from the portion below the VSS wiring 153. In addition, the interval between the guard ring 117 and the NMOS11 may be gradually increased as being distant from the VSS wiring 153. In these cases, the same effects as those of the first embodiment are obtained.

Modification 3 of the first embodiment

In modification 3 of the first embodiment, an example in which the arrangement of the circuit surrounded by the guard ring is different is shown. In modification 3 of the first embodiment, the description of the same components as those of the above-described embodiment may be omitted.

As shown in fig. 15, the VDD interconnection 152 and the VSS interconnection 153 described in the first embodiment and the modifications 1 and 2 can be arranged to surround the periphery of the substrate 130, for example. The VDD line 152 and the VSS line 153 are disposed inside a moisture-proof ring (not shown) provided to prevent moisture and the like from entering the semiconductor device. However, VDD interconnection 152 and VSS interconnection 153 may not necessarily have a ring shape, and VDD interconnection 152 may be arranged outside VSS interconnection 153. In addition, the VDD wiring 152 and the VSS wiring 153 may be plural. Further, VSS wiring 153 may be arranged between a plurality of VDD wirings 152, or a plurality of VDD wirings 152 and a plurality of VSS wirings 153 may be alternately arranged.

The I/O cell 170 is a partition in which semiconductor elements for input and output are provided, and is disposed on the upper and lower sides (sides extending in the X direction) or the left and right sides (sides extending in the Y direction) of the substrate 130 in the periphery of the substrate 130. The circuitry of the present invention (the portion enclosed by the guard ring 117) is disposed within the I/O cell 170. However, a part or all of the I/O cell 170 may be located below the power supply pad, the signal input/output pad, or the dummy pad.

The first embodiment and the modifications 1 and 2 have been described in the case where the I/O cell 170 is disposed on the upper and lower sides (sides extending in the X direction) of the substrate 130, but the I/O cell 170 may be disposed on the left and right sides (sides extending in the Y direction) of the substrate 130, for example, as shown in fig. 16.

Specifically, when the I/O cell 170 is disposed on the left and right sides (sides extending in the Y direction) of the substrate 130, the VDD wiring 152 and the VSS wiring 153 are arranged in the X direction while extending in the Y direction, as shown in fig. 16. Therefore, the positions of the portions where the distances W1, W2, and W3 between the NMOS11 and the guard ring 117 are different are also changed. That is, in the first embodiment and the modifications 1 and 2, the portions having the difference in the intervals W1 and W2 are arranged in the Y direction, and in the second embodiment, are arranged in the X direction.

Note that, in the case of aligning the direction of the NMOS11 in the chip, particularly in the case of a FinFET or a nanowire FET, the arrangement in the circuit may be changed depending on the position in the chip, but the circuit is equivalent to the first embodiment and the modifications 1 and 2.

In fig. 16, the via hole V0 disposed in the guard ring 117, the wiring of the wiring layer M1 electrically connecting the impurity regions 112 to each other, and the wiring of the wiring layer M1 electrically connecting the gate electrodes 113 to each other are omitted.

Second embodiment

In the second embodiment, an example in which the width of the interval between the NMOS and the guard ring is determined is different from that in the first embodiment. In the second embodiment, the description of the same components as those of the already described embodiment may be omitted.

Fig. 17 is a plan view illustrating the structure of the semiconductor device according to the second embodiment. In fig. 17, the upper side is a weight shape, and the distance between the NMOS11 and the guard ring 117 at a position (portion B) distant from the VSS wiring 153 is narrower, unlike the case of fig. 2. That is, in fig. 17, portions with a narrow interval from the grommet 117 are arranged on both sides in the Y direction of a portion with a wide interval from the grommet 117 in a plan view.

In fig. 17, the via hole V0 disposed in the guard ring 117, the wiring of the wiring layer M1 for electrically connecting the impurity regions 112 to each other, and the wiring of the wiring layer M1 for electrically connecting the gate electrodes 113 to each other are omitted.

In fig. 17, since the B portion is located away from the VSS wiring 153 and the resistance value from the VSS wiring 153 is high, the ESD current is less likely to flow to the narrowed B portion. Therefore, the suppression effect of EM generation is exhibited, and the number of the NMOS11 can be increased, and the performance (e.g., driving capability, ESD protection capability) of the semiconductor device 1 can be improved.

As shown in fig. 17, the portion B may overlap the VDD interconnection 152 in a plan view. As shown in fig. 17, a wiring 151 having a portion extending in the Y direction at a position not overlapping with the impurity region 111 in a plan view (on the STI132 between the guard ring 117 and the impurity region 112) may be connected to the impurity region 111 of the NMOS11 in the B portion and the impurity region 111 at a position overlapping with the VSS wiring 153. The guard ring 117 in the B portion may have the same distance from the impurity region 111 as the guard ring 117 at the position overlapping the VSS wiring 153.

Other configurations are the same as the first embodiment, and various FETs may be used as in modifications 1 and 2 of the first embodiment, or the direction of the circuit may be changed as in modification 3. In addition to between VSS and VDD, NMOS11 may be provided between the input/output signal terminal (PAD) and VSS instead of VDD.

Third embodiment

In the third embodiment, an example in which a PMOS is used instead of an NMOS is shown. In the third embodiment, the description of the same components as those of the already described embodiments may be omitted.

Fig. 18 is a circuit diagram of a semiconductor device according to a third embodiment. As shown in fig. 18, the semiconductor device 1A has a PMOS21 (second transistor), wherein the PMOS21 is a P-type field effect transistor. PMOS21 is connected between VDD and VSS. The gate electrode 213 of the PMOS21 is connected to an ESD trigger circuit C11. D11 is a parasitic diode.

Fig. 19 is a plan view illustrating a structure of the semiconductor device according to the third embodiment. As shown in fig. 18 and 19, in the semiconductor device 1A, the P-type impurity region 211 (third impurity region) of the PMOS21 is connected to VDD (power supply terminal) via the VDD interconnection 152. P-type impurity region 212 (fourth impurity region) of PMOS transistor 21 is connected to VSS (ground terminal) via VSS wiring 153. P-type impurity regions 212 of PMOS transistors 21 arranged in the Y direction are connected to each other via a wiring 151. Further, the wiring 151 is simply drawn.

In fig. 19, the via hole V0 disposed in the guard ring 217, the wiring of the wiring layer M1 electrically connecting the impurity regions 211 to each other, and the wiring of the wiring layer M1 electrically connecting the gate electrodes 213 to each other are omitted.

The

impurity regions

211 and 212 and the gate electrode 213 of the PMOS transistor 21 are surrounded by a guard ring 217 (second guard ring) which is an N-type impurity region. Guard ring 217 is connected to VDD interconnection 152 via interconnection 154 of metal interconnection layer M1 disposed on guard ring 217.

If ESD current flows from VSS to VDD in a configuration in which no difference is provided between W1, W2, and W3, if ESD current flows below VSS wiring 153, it may reach VDD through wiring 154 of metal wiring layer M1, and EM may occur.

However, as shown in fig. 19, in the semiconductor device 1A, the distance W2 or W3 between the guard ring 217 below the VDD wiring 152 where the ESD current is intended to flow and the impurity region 212 of the PMOS21 is narrower than the distance W1 between the guard ring 217 and the impurity region 212 of the PMOS21 in other portions.

That is, a portion (a portion of the interval W1) having a wide interval from the guard ring 217 in a plan view is located at a position distant from the VDD wiring 152 in a plan view, and a portion (a portion of the interval W2 or W3) having a narrow interval is located at a position overlapping with the VDD wiring 152 in a plan view.

Accordingly, the ESD current flows more easily in the portion of the interval W2 or W3 having a lower resistance than in the portion of the interval W1 having a higher resistance. As a result, the ESD current can be suppressed from flowing in the wiring 154 on the guard ring 217, and the generation of EM in the wiring 154 due to the ESD current can be suppressed.

Further, although the ESD current flows from the VSS wiring 153 to the PMOS21 below the VDD wiring 152 via the wiring 151, the ESD current is dispersed and EM is less likely to occur because the wiring 151 is arranged more frequently than the wiring 154 on the guard ring 217.

In the PMOS21, various FETs may be used as in modifications 1 and 2 of the first embodiment, or the circuit direction may be changed as in modification 3. In addition, the input/output signal terminal may be used instead of VDD instead of VSS to VDD. In addition, as in the second embodiment, the PMOS distant from the VDD wiring 152 may be arranged near the guard ring 217 (hammer type).

Target circuit

The above-described embodiments and modifications can be applied to circuits other than those shown in fig. 1 and 18. Here, a target circuit to which the above-described embodiments and modifications can be applied will be described. In the following description, the same components as those of the above-described embodiment may be omitted.

[ 1 thereof ]

Fig. 20 is a circuit diagram of other subject circuits (1 thereof). As shown in fig. 20, the semiconductor device 1B has NMOS11 and 12, wherein the NMOS11 and 12 are N-type field effect transistors. The NMOS11 and 12 are connected in series between VDD and VSS.

Specifically, in the semiconductor device 1B, the N-type impurity region 111 of the NMOS11 is connected to VDD (power supply terminal) via a VDD line. The N-type impurity region 122 of the NMOS12 is connected to VSS (ground terminal) via a VSS wiring. Further, the N-type impurity region 112 of the NMOS11 and the N-type impurity region 121 of the NMOS12 are connected.

The ESD trigger circuit C11 is connected to the gate electrode 113 of the NMOS11 and the gate electrode 123 of the NMOS12. D11 is a parasitic diode.

Fig. 21 is a plan view illustrating the structure of the semiconductor device shown in fig. 20. In fig. 21 (a), within the I/O cell 170, the NMOS11 and 12 are surrounded by a P-type guard ring 117.

Since VDD interconnection 152 (not shown) is connected to impurity region 111 of NMOS11, differences are provided in NMOS11 with respect to spacings W1, W2, and W3, as in the first and second embodiments and the modified examples.

Accordingly, the ESD current flows more easily in the portion of the interval W2 or W3 having a lower resistance than in the portion of the interval W1 having a higher resistance. As a result, the ESD current can be suppressed from flowing through the wiring on the guard ring 117, and the generation of EM in the wiring due to the ESD current can be suppressed. As shown in fig. 21 (b), a portion extending in the X direction between the NMOS11 and the NMOS12 may be omitted in the guard ring 117.

In fig. 21 (a) and 21 (b), the NMOS11 and the NMOS12 are arranged in the Y direction, but the NMOS11 and the NMOS12 may be alternately arranged in the X direction, for example.

[ 2 thereof ]

Fig. 22 is a circuit diagram of the other subject circuit (2 thereof). As shown in fig. 22, the semiconductor device 1C has a PMOS21 and an NMOS11, wherein the PMOS21 is a P-type field effect transistor and the NMOS11 is an N-type field effect transistor. The PMOS21 and NMOS11 are connected in series between VDD and VSS.

Specifically, in the semiconductor device 1C, the P-type impurity region 211 of the PMOS21 is connected to VDD (power supply terminal) via a VDD interconnection. The N-type impurity region 112 of the NMOS11 is connected to VSS (ground terminal) via a VSS wiring. Further, the P-type impurity region 212 of the PMOS21 and the N-type impurity region 111 of the NMOS11 are connected, and the PAD11 as an input/output terminal is further connected to a connection portion between the impurity region 212 and the impurity region 111.

The gate electrode 213 of the PMOS21 and the gate electrode 113 of the NMOS11 are connected to the driver circuits C12 and C13. D11 is a parasitic diode.

Fig. 23 is a plan view illustrating the structure of the semiconductor device shown in fig. 22. In fig. 23, in the I/O cell 170, the PMOS21 is surrounded by the N-type guard ring 217, and the NMOS11 is surrounded by the P-type guard ring 117.

The PMOS21 is provided with a difference in the distances W1, W2, and W3 as in the third embodiment, and the NMOS11 is provided with a difference in the distances W1, W2, and W3 as in the first and second embodiments and the modified examples.

Accordingly, the ESD current flows more easily in the portion of the interval W2 or W3 having a lower resistance than in the portion of the interval W1 having a higher resistance. As a result, EM can be suppressed from being generated by the ESD current in the wiring from PAD11 to VDD and the wiring from VSS to PAD11.

[ 3 thereof ]

Fig. 24 is a circuit diagram of other subject circuits (3 thereof). As shown in fig. 24, the semiconductor device 1D includes PMOS21 and 22 and NMOS11 and 12, the PMOS21 and 22 are P-type field effect transistors, and the NMOS11 and 12 are N-type field effect transistors.

PMOS21, PMOS22, NMOS11, and NMOS12 are connected in series between VDD and VSS.

Specifically, in the semiconductor device 1D, the P-type impurity region 211 of the PMOS21 is connected to VDD (power supply terminal) via a VDD line. Further, P-type impurity region 212 of PMOS21 and P-type impurity region 221 of PMOS22 are connected.

The N-type impurity region 122 of the NMOS12 is connected to VSS (ground terminal) via a VSS wiring. Further, the N-type impurity region 121 of the NMOS12 and the N-type impurity region 112 of the NMOS11 are connected.

The P-type impurity region 222 of the PMOS22 and the N-type impurity region 111 of the NMOS11 are connected, and a PAD11 serving as an input/output terminal is also connected to a connection portion between the impurity region 222 and the impurity region 111.

The PMOS driver control circuit C14 is connected to the gate electrode 213 of the PMOS21 and the gate electrode 223 of the PMOS 22. Further, an NMOS driver control circuit C15 is connected to the gate electrode 113 of the NMOS11 and the gate electrode 123 of the NMOS12. D11 is a parasitic diode.

Fig. 25 is a plan view illustrating the structure of the semiconductor device shown in fig. 24. In fig. 25 (a), in the I/O cell 170, the PMOS21 and 22 are surrounded by the N-type guard ring 217, and the NMOS11 and 12 are surrounded by the P-type guard ring 117.

Since VDD interconnection 152 (not shown) is connected to impurity region 211 of PMOS21, differences are provided for intervals W1, W2, and W3 in PMOS21, as in the third embodiment. In addition, similarly to the circuit of fig. 20, the NMOS11 is provided with differences in the intervals W1, W2, and W3 similarly to the first and second embodiments and the modified examples.

Accordingly, the ESD current flows more easily in the portion of the interval W2 or W3 having a lower resistance than in the portion of the interval W1 having a higher resistance. As a result, EM can be suppressed from being generated by the ESD current in the wiring from PAD11 to VDD and the wiring from VSS to PAD11. As shown in fig. 25 (b), the guard ring 117 may omit a portion extending in the X direction between the NMOS11 and the NMOS12. Similarly, in the guard ring 217, a portion extending in the X direction between the PMOS21 and the PMOS22 may be omitted.

Fourth embodiment

In the fourth embodiment, an example in which the circuit shown in fig. 20 or the like is disposed in the guard ring is shown. In the fourth embodiment, the description of the same components as those of the previously described embodiments may be omitted.

Fig. 26 is a plan view illustrating a structure of the semiconductor device according to the fourth embodiment. For example, in a circuit in which NMOS11 and NMOS12 are cascade-connected between VDD and VSS as shown in fig. 20, NMOS11 and NMOS12 may be alternately arranged in the X direction as shown in fig. 26. In FIG. 26, for the sake of convenienceFor explanation, use 151 _D The symbol (M1) denotes a wiring 151 of the metal wiring layer M1 electrically connected to the

VDD wiring

152, and 151 denotes _S The symbol (M1) indicates the wiring 151 of the metal wiring layer M1 electrically connected to the VSS wiring 153.

In the case of fig. 26, as in the other embodiments and modifications, the distance W2 or W3 between guard ring 117 (which is the first portion) below VSS wiring 153 and impurity region 111 of NMOS11 is narrower than the distance W1 between the portion of guard ring 117 different from the first portion and impurity region 111 of NMOS11.

Accordingly, as in the other embodiments and modifications, since the ESD current flows more easily in the portion of the interval W2 or W3 having a lower resistance than in the portion of the interval W1 having a higher resistance, it is possible to suppress the ESD current from flowing through the wiring 154 on the grommet 117 and to suppress the generation of EM in the wiring 154 due to the ESD current.

In addition, the density in the extending direction of the guard ring 117 of the via hole V0 at a position overlapping with the VSS wiring 153 in a plan view may be higher than the density in the extending direction of the guard ring 117 of the via hole V0 at a position not overlapping with the VSS wiring 153 in a plan view. Accordingly, the ESD current easily flows below the VSS wiring 153, and therefore, the occurrence of EM on the wiring 154 due to the ESD current can be further suppressed.

In addition, the interval between the guard ring 117 and the NMOS11 may be gradually increased as being distant from the VSS wiring 153. By being configured in this way, an effect of EM suppression is obtained, and the number of NMOS within the guard ring 117 can be increased, and the performance (e.g., driving capability, ESD protection capability) of the semiconductor device can be improved.

In the NMOS11 and 12, a FinFET or a nanowire FET may be used as in modifications 1 and 2 of the first embodiment, or the direction of a circuit may be changed as in modification 3. Further, as in the second embodiment, the NMOS11 located at a position distant from the VDD interconnection 152 may be disposed in the vicinity of the guard ring 117 (hammer type).

The description so far has been made with respect to the circuit of fig. 20, and for example, in the circuit of fig. 24, the NMOS11 and 12 cascade-connected between VSS (ground terminal) and PAD11 (input-output terminal) may be arranged in the same manner as fig. 26.

In the circuit of fig. 24, the PMOS21 and 22 cascade-connected between VDD (power supply terminal) and PAD11 (input/output terminal) may be arranged in the same manner as in fig. 26.

However, in the case of the PMOS transistors 21 and 22, similarly to the case of fig. 19, the

impurity regions

211 and 212 and the gate electrode 213 of the PMOS transistor 21 are surrounded by the guard ring 217 which is an N-type impurity region, and the guard ring 217 is connected to the VDD line 152 via the line 154 of the metal wiring layer M1 disposed on the guard ring 217.

While the preferred embodiments have been described in detail, the present invention is not limited to the above embodiments, and various modifications and substitutions can be made to the above embodiments without departing from the scope of the present invention as set forth in the claims.

For example, the embodiments and the modifications can be combined as appropriate as needed.

The following remarks are also disclosed with respect to the above embodiments and modifications.

(note 1) a semiconductor device, comprising:

a substrate;

a first transistor formed on the substrate and having a first impurity region and a second impurity region of a first conductivity type;

a first guard ring formed on the substrate, located at a position surrounding the first transistor in a plan view, and having a second conductivity type different from the first conductivity type;

a first wiring formed on the first guard ring and electrically connected to the first guard ring; and

a ground wiring formed on the first wiring and electrically connected to the first wiring and the second impurity region,

the first transistor includes a first portion spaced from the first guard ring by a first distance in a plan view and a second portion spaced from the first guard ring by a second distance shorter than the first distance in the plan view,

the first portion is located apart from the ground wiring in a plan view, and the second portion is located to overlap the ground wiring in a plan view.

(note 2) the semiconductor device according to note 1, wherein,

the first impurity region is electrically connected to a power supply wiring.

(additional note 3) a semiconductor device characterized in that,

a substrate;

a second transistor formed on the substrate and having a third impurity region and a fourth impurity region of a second conductivity type;

a second guard ring formed on the substrate, located at a position surrounding the second transistor in a plan view, and having a first conductivity type different from the second conductivity type;

a second wiring formed on the second guard ring and electrically connected to the second guard ring; and

a power supply wiring formed on the second wiring and electrically connected to the second wiring and the third impurity region,

the second transistor includes a third portion spaced from the second guard ring by a third distance in a plan view, and a fourth portion spaced from the second guard ring by a fourth distance shorter than the third distance in the plan view,

the third portion is located away from the power supply wiring in a plan view, and the fourth portion is located so as to overlap the power supply wiring in a plan view.

(additional note 4) A semiconductor device, characterized in that,

a substrate;

a first wiring formed on the first guard ring and electrically connected to the first guard ring;

a ground wiring formed on the first wiring and electrically connected to the first wiring and the second impurity region;

the first portion is located at a position distant from the ground wiring in a plan view, and the second portion is located at a position overlapping with the ground wiring in a plan view,

the second transistor includes a third portion spaced from the second guard ring by a third distance in a plan view, and a fourth portion spaced from the second guard ring by a shorter distance in a plan view than the third distance,

the third portion is located at a position distant from the power supply wiring in a plan view, and the fourth portion is located at a position overlapping with the power supply wiring in a plan view.

(additional character 5) the semiconductor device according to additional character 1, 2, or 4,

a first via hole connecting the first guard ring and the first wiring is provided,

the density in the extending direction of the first guard ring of the first via hole at a position overlapping with the ground wiring in a plan view is higher than the density in the extending direction of the first guard ring of the first via hole at a position not overlapping with the ground wiring in a plan view.

(additional note 6) the semiconductor device according to additional note 3 or 4, wherein,

a second via hole connecting the second guard ring and the second wiring is provided,

the density in the extending direction of the second guard ring of the second via hole at a position overlapping with the power supply wiring in a plan view is higher than the density in the extending direction of the second guard ring of the second via hole at a position not overlapping with the power supply wiring in a plan view.

(additional note 7) the semiconductor device according to additional note 4, wherein,

a density in an extending direction of the first guard ring of the first via hole at a position overlapping with the ground wiring in a plan view is higher than a density in an extending direction of the first guard ring of the first via hole at a position not overlapping with the ground wiring in a plan view,

(additional note 8) the semiconductor device according to additional note 4 or 7, wherein,

the first impurity region and the fourth impurity region are connected to an input/output terminal.

(additional character 9) the semiconductor device according to additional character 1, 4, 7, or 8,

a plurality of the first transistors are connected in series.

(note 10) the semiconductor device according to note 1, 2, 4, 5, 7, 8, or 9, wherein,

the first transistor has a fifth portion spaced from the first guard ring by a fifth distance shorter than the first distance in a plan view,

the second portion is located between the first portion and the fifth portion in a plan view.

(note 11) the semiconductor device according to note 1, 2, 4, 5, 7, 8, 9, or 10, wherein,

the first transistor and the first guard ring are gradually spaced apart from each other between the first portion and the second portion in a plan view.

(note 12) the semiconductor device according to

note

1, 2, 4, 5, 7, 8, 9, 10, or 11, wherein,

the first transistor is a FinFET.

(note 13) the semiconductor device according to

note

1, 2, 4, 5, 7, 8, 9, 10, or 11, wherein,

the first transistor is a nanowire FET.

(note 14) the semiconductor device according to note 3, 4 or 6, wherein,

the second transistor has a sixth portion spaced from the second guard ring by a sixth distance shorter than the third distance in a plan view,

the fourth portion is located between the third portion and the sixth portion in a plan view.

(additional character 15) the semiconductor device according to additional character 3, 4, 6, or 14,

the second transistor and the second guard ring are spaced apart from each other gradually from the third portion to the fourth portion in a plan view.

(note 16) the semiconductor device according to note 3, 4, 6, 14 or 15, wherein,

the second transistor is a FinFET.

(additional character 17) the semiconductor device according to additional character 3, 4, 6, 14, or 15,

the second transistor is a nanowire FET.

Claims

1. A semiconductor device is characterized by comprising:

a substrate;

a first guard ring formed on the substrate and located at a position surrounding the first transistor in a plan view, the first guard ring having a second conductivity type different from the first conductivity type;

the first transistor includes a first portion and a second portion arranged in a first direction in a plan view, a first distance between the first portion and the first guard ring in a second direction in a plan view, a second distance shorter than the first distance between the second portion and the first guard ring in the second direction in the plan view, and a second direction orthogonal to the first direction,

2. The semiconductor device according to claim 1,

the first impurity region is electrically connected to a power supply wiring.

3. A semiconductor device is characterized by comprising:

a substrate;

a second guard ring formed on the substrate and located at a position surrounding the second transistor in a plan view, the second guard ring having a first conductivity type different from the second conductivity type;

the second transistor includes a third portion and a fourth portion arranged in a third direction in a plan view, the third portion being spaced from the second guard ring in a fourth direction by a third distance in the plan view, the fourth portion being spaced from the second guard ring in the fourth direction by a fourth distance shorter than the third distance in the plan view, the third direction orthogonal to the fourth direction,

the third portion is located apart from the power supply wiring in a plan view, and the fourth portion is located to overlap the power supply wiring in a plan view.

4. A semiconductor device is characterized by comprising:

a substrate;

the first portion is located apart from the ground wiring in a plan view, the second portion is located to overlap the ground wiring in a plan view,

5. The semiconductor device according to claim 1, 2, or 4,

a first via hole connecting the first guard ring and the first wiring,

6. The semiconductor device according to claim 3 or 4,

7. The semiconductor device according to claim 4,

8. The semiconductor device according to claim 4 or 7,

9. The semiconductor device according to claim 1, 4, or 7,

a plurality of the first transistors are connected in series.

10. The semiconductor device according to claim 1, 2, 4, or 7,

11. The semiconductor device according to claim 1, 2, 4, or 7,

the first transistor and the first guard ring are spaced apart from each other gradually between the first portion and the second portion in a plan view.