CN108918937B - Universal oscillographic card and system based on PCI interface - Google Patents

Universal oscillographic card and system based on PCI interface Download PDF

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Publication number
CN108918937B
CN108918937B CN201811070715.9A CN201811070715A CN108918937B CN 108918937 B CN108918937 B CN 108918937B CN 201811070715 A CN201811070715 A CN 201811070715A CN 108918937 B CN108918937 B CN 108918937B
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signal
card
fpga
universal
oscillographic
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CN108918937A (en
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刘博�
张云
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Beijing Chucai Precision Instrument Technology Co ltd
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Beijing Chucai Precision Instrument Technology Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R13/00—Arrangements for displaying electric variables or waveforms
    • G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
    • G01R13/0209—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form in numerical form
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R13/00—Arrangements for displaying electric variables or waveforms
    • G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
    • G01R13/0281—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form using electro-optic elements
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/21—Pc I-O input output
    • G05B2219/21014—Interface, module with relays
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/21—Pc I-O input output
    • G05B2219/21137—Analog to digital conversion, ADC, DAC

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Computer Hardware Design (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)

Abstract

The application discloses a universal oscillographic card and a system based on PCI interface, the oscillographic card comprises: PCI interface circuit, FPGA, signal amplitude control device, signal acquisition device and memory; the FPGA is used for receiving a control instruction transmitted by a user through the upper computer through the PCI interface; the signal amplitude control device is used for adjusting the amplitude of the input signal to obtain an adjusted signal; the signal acquisition device is used for acquiring the adjusted signals; and the FPGA is used for storing the signals acquired by the signal acquisition device into an external memory according to a preset triggering mode when the signals are determined to meet the preset triggering conditions. When detecting the data reading instruction of the upper computer, the data is sent to the upper computer interface to be displayed in a waveform mode. By the mode, the adjustment of the gear position, the signal amplification and the like of the signal can be more flexible, and the adjustment range is wider; and the sampling frequency can be flexibly adjusted. The signals collected by the oscillographic card can be displayed in real time through the upper computer.

Description

Universal oscillographic card and system based on PCI interface
Technical Field
The application relates to the field of electronic test and measurement, in particular to a universal oscillographic card and a universal oscillographic system based on a PCI interface.
Background
Oscilloscopes are one of the most widely used measuring instruments in the field of electronic measurement. Oscilloscopes are indispensable measuring tools in scientific research, experiments, production debugging, maintenance, and other disciplines where signal waveforms need to be observed. To facilitate the storage, processing and computation of test data, conventional analog oscilloscopes are gradually replaced by digital oscilloscopes. However, the digital oscilloscope has limited signal storage, processing and computing capabilities, and in many cases, people need massive data storage, complex processing functions and deep computing capabilities. Therefore, the digital oscilloscope gradually expands a plurality of computer interfaces, and the functions of the digital oscilloscope are improved by means of the powerful functions of the computer. However, the connection between the digital oscilloscope and the computer is often indirect and cumbersome, and brings a lot of inconvenience to the operation of the user.
Disclosure of Invention
The application aims to provide a universal oscillographic card and a universal oscillographic system based on a PCI interface, which are used for solving the problems that the prior oscilloscope has limited storage, processing and calculation capabilities on signals and the connection between a digital oscilloscope and a computer is complicated.
In order to achieve the above object, the present application provides a universal oscillographic card based on a PCI interface, the universal oscillographic card being inserted into an external device interconnection (Peripheral Component Interconnect, abbreviated as PCI) card slot of an upper computer, the universal oscillographic card based on the PCI interface comprising: PCI interface circuit, field programmable gate array (Field-Programmable Gate Array, FPGA), signal amplitude control device, signal acquisition device and memory;
the PCI interface circuit establishes communication connection between the FPGA and the upper computer;
the FPGA is respectively and electrically connected with the signal amplitude control device, the signal acquisition device and the memory;
the FPGA is used for receiving a control instruction transmitted by a user through the upper computer through the PCI interface, and the control instruction is used for indicating the FPGA to control the signal amplitude control device and the signal acquisition device to execute corresponding operations;
the signal amplitude control device is used for adjusting the amplitude of the input signal to obtain an adjusted signal;
the signal acquisition device is used for acquiring the adjusted signals, acquiring acquired data and sending the acquired data to the FPGA;
the FPGA is used for storing the data acquired by the signal acquisition device into an external memory according to a preset triggering mode when the acquired data are determined to meet the preset triggering condition, and transmitting the data to the upper computer for display after detecting an upper computer reading data instruction and reading the data from the memory, wherein the preset triggering mode corresponds to the preset triggering condition.
The application has the following advantages: the signal amplitude control device, the signal acquisition device, the memory, the FPGA and the like are integrated on the oscillographic card, the oscillographic card is inserted into a clamping groove of the upper computer, a user can input parameters on the interactive interface, the FPGA is used for adjusting the settings of the signal amplitude control device, the signal acquisition device and the like according to the parameters, further indirectly adjusting the measurement gear, amplifying the amplitude of a signal, changing the sampling frequency, adjusting the oscillographic card to execute continuous acquisition or single acquisition, and displaying the acquired signal on the graphical interface in a waveform mode. Through the mode, the adjustment of the gear position, the signal amplification and the like of the signal is more flexible, and the adjustment range is wider. And the sampling frequency can be flexibly adjusted. The signals collected by the oscillographic card can be displayed in real time through the upper computer.
The application also provides a universal oscillography system based on PCI interface, which comprises:
an upper computer and at least one universal oscillographic card based on PCI interface; the universal oscillograph based on the PCI interface is the universal oscillograph based on the PCI interface;
the upper computer comprises clamping grooves with the same number as the universal oscillographic cards based on the PCI interface; the universal oscillograph card based on the PCI interface is inserted into a slot of the upper computer; each universal oscillographic card based on the PCI interface comprises corresponding ID information;
and the upper computer sends a control instruction to the universal oscillographic card based on the PCI interface corresponding to the ID information according to the ID information, so that the universal oscillographic card based on the PCI interface corresponding to the ID information responds to the control instruction, and the acquired data is displayed on the upper computer in a waveform form.
The application has the following advantages: the system comprises an upper computer and at least one universal oscillographic card based on a PCI interface, so that one machine with multiple cards can be realized. That is, the computer may select one universal oscillograph card to perform work at the same time, or may select a plurality of universal oscillographs to perform work at the same time. The working efficiency is greatly improved. The working cost is reduced, and meanwhile, the user experience degree can be improved.
Drawings
FIG. 1 is a schematic diagram of a general oscillographic card structure based on a PCI interface according to an embodiment of the present application;
fig. 2 is a schematic diagram of an internal workflow of an FPGA according to an embodiment of the present application.
Detailed Description
The following examples are illustrative of the application and are not intended to limit the scope of the application.
Example 1
The embodiment 1 of the application provides a general oscillographic card structure diagram based on a PCI interface. The universal oscillograph card is inserted into a PCI card slot of an upper computer, and specifically as shown in fig. 1, the universal oscillograph card may include: PCI interface circuit, field programmable gate array FPGA, signal amplitude control device, signal acquisition device and memory. In fig. 1 the "thick arrow" indicates the signal flow direction and the "thin arrow" indicates the flow direction of the configuration parameters.
The PCI interface circuit establishes communication connection between the FPGA and the upper computer, and the FPGA is respectively and electrically connected with the signal amplitude control device, the signal acquisition device and the memory.
The FPGA is used for receiving a control instruction transmitted by a user through the upper computer through the PCI interface, and the control instruction is used for indicating the FPGA to control the signal amplitude control device, the signal acquisition device and the memory to execute corresponding operations; for example, the signal amplitude control device is used for adjusting the amplitude of the input signal to obtain an adjusted signal; the signal acquisition device is used for acquiring the adjusted signals, acquiring acquired data and sending the data to the FPGA;
the FPGA is used for storing signals acquired by the signal acquisition device into an external memory according to a preset triggering mode when the acquired data are determined to meet the preset triggering condition;
when the data reading instruction of the upper computer is detected, the data is read from the memory and then transmitted to the upper computer for display, wherein the preset triggering mode corresponds to the preset triggering condition.
In one specific example, the PCI interface circuit is composed of a PCI gold finger, a PCI9054 chip and a configuration EEPROM memory. The EEPROM can be realized by a plurality of chips, such as 93CS56, and the like, and the PCI interface realizes the direct and rapid data communication between the upper computer and the FPGA.
Optionally, the signal amplitude control device specifically includes: the device comprises a signal interface, a gear selector, a voltage-controlled amplifier and a digital-analog converter. The FPGA is electrically connected with the gear selector and the digital-analog converter (Digital to analog converter, DAC for short) respectively; the DAC is electrically connected to a voltage controlled amplifier.
The signal interface is connected with the gear selector; the signal interface is used for receiving an input signal.
The FPGA is used for sending the range parameters of the gears to the gear selector, and the input signals are output after the gears of the gear selector are selected.
And/or the FPGA is used for sending the amplification factor for amplifying the signal output by the gear selector to the DAC. The DAC is used for converting the amplification factor of the signal output by the gear selector into a voltage signal to act on the voltage-controlled amplifier; and the voltage-controlled amplifier is used for amplifying the signal output by the gear selector according to the voltage signal.
Optionally, the gear selector includes: the device comprises a Darlington pipe, a relay and a voltage dividing network;
one end of the Darlington tube is electrically connected with the FPGA, and the other end of the Darlington tube is electrically connected with the relay; the voltage divider network includes: a low range channel and a high range channel;
the Darlington tube is used for driving a relay switch according to the gear range parameter so as to switch a low range channel or a high range channel in the voltage division network.
Optionally, the voltage controlled amplifier specifically includes: a low noise high speed operational amplifier and a voltage controlled gain amplifier; the low-noise high-speed operational amplifier is used for performing first-stage amplification on the signal output by the gear selector; and the voltage-controlled gain amplifier is used for carrying out second-stage gain amplification on the signal subjected to the first-stage amplification by the low-noise high-speed operational amplifier.
Optionally, the signal acquisition device includes: a low distortion differential amplifier, a filter, an analog-to-digital converter (Analog to digital converter, ADC for short), and a buffer; the low-distortion differential amplifier is used for converting the signal amplified by the voltage-controlled amplifier into a differential signal; the filter is used for filtering the differential signals;
the ADC is used for converting the filtered differential signal into a digital signal; the buffer is used for buffering the digital signals and inputting the digital signals to the FPGA. The ADC is specifically used for: and carrying out AD conversion on the differential signals according to the sampling clock signals output by the FPGA.
The above description of the components of the universal oscillometric card, as well as the specific connection relationships, is only from a hardware perspective. The working principle of the oscillometric card will be described in detail, and specifically includes:
the user inputs parameters which want to adjust the input signals, such as functions of measuring gear, amplitude, sampling frequency, triggering mode, recording mode, storage position and the like of the input signals, through a man-machine interaction interface in upper computer software on an upper computer. The upper computer software converts the operation of the user into a control instruction and transmits the control instruction to the FPGA through the PCI interface. The FPGA executes corresponding operations according to the control signal amplitude control device, the signal acquisition device, the memory and the like corresponding to the control instruction. And uploading the acquired signals to the upper computer so that the upper computer can display in real time. The control instructions are embodied in the form of keywords, such as keywords in a triggering mode and keywords in a triggering characteristic mode during signal acquisition. The sampling frequency is also embodied in a sampling rate key form, the gear range parameter is also embodied in a gear key form, and the magnification is embodied in a magnification key form. The specific keyword form is preset. For example, the gain factor is 10 times, and the gain key may be set to 10. If the shift range is desired to be set to the low shift range, the shift key corresponding thereto may be set to 01 or the like. If there are trigger patterns and trigger conditions, it can be embodied in the form of two keywords appearing simultaneously, such as 1-1,2-2, etc., with the former 1 representing the trigger pattern and the latter 1 representing the manifestation of the trigger condition.
As described above, the signal amplitude control unit is composed of the signal interface, the gear selector, the voltage-controlled amplifier, and the DAC. The input signal is generally an analog signal, and is fed through a signal interface, and the FPGA can adjust the range of the gear selector according to the range parameter. The gear selector consists of a Darlington tube, a relay and a voltage dividing network. After the input signal enters the port, it first passes through a voltage divider network. The FPGA drives a relay switch through a Darlington tube to switch the voltage division channel. The voltage dividing network has two channels, when the input voltage is within the range of-0.5V to 0.5V, the relay is switched to the low-range channel, and the original input signal is introduced into the subsequent stage. When the input voltage exceeds the range of-0.5V to 0.5V, the relay is switched to a high-range channel, and the divided signals are introduced into the subsequent stage. The second-stage relay selects a direct current coupling mode or an alternating current coupling mode through a capacitance blocking circuit to output signals.
After the gear selector selects the corresponding range channel output signal, the signal is amplified by a voltage-controlled amplifier. The voltage-controlled amplifier mainly comprises two stages of amplifier cascade connection, wherein the first stage of amplifier adopts a low-noise high-speed operational amplifier, and the amplification factor is 1. The primary function of the first-stage amplifier is to realize the electrical isolation of the front and back-stage circuits. The second stage amplifier adopts a gain amplifier, and the gain multiple of specific amplification is determined by the voltage output by the DAC. Specifically, the user has actually entered the magnification of the magnification at this time in the initial case. However, since the input form is input in the form of a digital signal, the digital signal needs to be converted into a voltage signal by a DAC and then applied to a gain amplifier to amplify the signal. For example, the ADR510 generates 1V voltage as a reference voltage of the DAC, the output voltage of the DAC is input as the positive terminal of the gain amplifier AD603, and the 500mV level generated by dividing the 1V level is input as the negative terminal of the gain of the AD 603. The signal VOUT amplified by the AD603 is output to the signal acquisition unit.
After being amplified by the voltage-controlled amplifier, the output signal enters the signal acquisition device, so that the signal acquisition device is convenient for signal acquisition.
Specifically, the signal acquisition device may be composed of a low-distortion differential amplifier, a filter, a high-speed ADC, and a buffer. The low distortion differential amplifier may be an AD8138. The high speed ADC may be an AD9215 which may achieve a sampling rate of up to 100MHz, a data resolution of 10 bits. The low-distortion differential amplifier converts the single-ended output signal amplified by the voltage-controlled amplifier into a differential signal, and the filter filters the differential signal, and in this embodiment, a low-pass filter is used. And the ADC is controlled by a sampling clock output by the FPGA to realize high-speed analog-to-digital conversion of the signals, namely, the filtered differential signals are subjected to analog-to-digital conversion and converted into digital signals. And is input into the FPGA after passing through the buffer. The specific acquisition can be single acquisition or continuous acquisition. And whether the single acquisition or the continuous acquisition is determined by an upper computer instruction. The results of the acquisition will be temporarily stored in a 1k capacity FIFO. The FPGA judges whether the signal acquired by the current signal acquisition device meets the triggering condition or not. Different triggering modes correspond to different triggering conditions. The triggering mode may include: external trigger signal, input signal level trigger, input signal pulse width trigger, input signal slope trigger, etc. Then the corresponding specific trigger conditions may include: for the external trigger signal mode, the trigger condition can be selected as the high level trigger, the low level trigger, the rising edge trigger and the falling edge trigger of the external signal. For the input signal level triggering mode, the triggering condition can be selected as follows: the input signal is above a certain set amplitude trigger and/or the input signal is below a certain set amplitude trigger. For the input signal pulse width triggering mode, the triggering conditions can be selected as follows: the signal time width of the input signal at a certain amplitude is larger than a certain time trigger or smaller than a certain time trigger. For the input signal slope triggering mode, the triggering condition can be selected as follows: the input signal waveform is triggered when the slope of the input signal waveform within a certain set amplitude interval is higher than a certain value or lower than a certain value.
When the set trigger condition is satisfied, the signal is stored into an external RAM. When the external RAM is full, after the FPGA receives a data reading instruction sent by the upper computer, the RAM space data designated by the user is transmitted to the upper computer display window for display. So that the upper computer can read and display on the display screen at any time. In practice, the triggering mode and the triggering condition are both selected in advance by the user.
Of course, if the set sampling mode is single sampling, the signal acquisition function is finished. If the sampling mode is set to be continuous acquisition, the upper computer starts the data reading instruction once again after delaying the preset time length. And repeatedly starting the data reading instruction and executing the subsequent operation. And displaying the RAM space data appointed by the user in the upper computer display window in sequence. The specific delay time can be determined by the refresh rate of the signal in the display window of the upper computer. Theoretically, it is assumed that the memory of the oscillograph card adopts a RAM with a 1M space, so that the maximum display point number of the upper computer display window is 1M. However, since the resolution of the display generally cannot support such multiple points to be displayed on the display window at the same time, only one segment of the storage space is often selected for display. Whereas typically 1K display points have clearly enough to trace the signal waveform in the window, the present solution defaults to 1K display points. The current display waveform can be a signal waveform close to the trigger point or a signal after a period of time from the trigger point, and the time from the display waveform to the trigger point is determined by the displacement of the display waveform. When the signals are continuously collected, the signals in the window are continuously rolled and refreshed, and the refresh rate is required to be set smaller than the refresh rate of the screen.
The data storage path determines the storage path and storage format of the current window display data. When the user selects single acquisition, the upper computer reads data from the address corresponding to the memory in the space designated by the display waveform control through the PCI interface, and then sequentially displays the read data in the window. When the user selects continuous acquisition, the upper computer continuously reads data from the address corresponding to the memory in the space appointed by the display waveform control, and the reading frequency is the refresh rate set in the display waveform control. The workflow in the FPGA is shown in fig. 2, and the detailed workflow is described above, and will not be described in detail here.
It should be noted that, when the triggering condition is external triggering, the oscillometric card should also include an external signal interface and a photocoupler. The external signal interface is used for receiving external trigger signals, and the photoelectric coupler is used for converting the external trigger signals with any level into TTL level, so that stable receiving of the FPGA is ensured. The photoelectric coupler can be conducted by feeding an electric signal with the voltage greater than 0.7V from an external signal interface, so that the level range of a trigger signal is enlarged, and the FPGA is protected from being damaged by high-voltage signals.
In practice, after the user opens the upper computer software, default parameters may be written into corresponding register locations in the FPGA to initialize the oscillographic card. And then the user can adjust the parameters of each introduced functional module according to the display requirement, and the upper computer writes the modified keywords into the corresponding storage positions in real time and then executes subsequent operations. This process is mainly for providing the user with a basis for adjusting the respective parameters, and is not a step which must be performed.
The universal oscillographic card based on the PCI interface provided by the embodiment of the application integrates the signal amplitude control device, the signal acquisition device, the memory, the FPGA and the like on the oscillographic card, the oscillographic card is inserted into the clamping groove of the upper computer, a user can input parameters on the interactive interface, the FPGA is used for adjusting the setting of the signal amplitude control device, the signal acquisition device and the like according to the parameters, further indirectly adjusting the measurement gear, amplifying the amplitude of the signal, changing the sampling frequency, adjusting the oscillographic card to execute continuous acquisition or single acquisition, and displaying the acquired signal on the graphical interface in a waveform mode. The gear of the signal, signal amplification and the like are more flexibly adjusted, and the adjusting range is wider. And the sampling frequency can be flexibly adjusted. The signals collected by the oscillographic card can be displayed in real time through the upper computer. The response speed and the amplitude resolution reach or exceed the level of the prior oscilloscope, and the cost and the power consumption are low. The computer can realize the function of the oscilloscope.
Example 2
In the above, only one general oscillometric card is taken as an example, and the structure and the working principle of the oscillometric card are described in detail. In practice, the present application may also include a universal oscillometric system based on a PCI interface, which may include at least one universal oscillometric card based on a PCI interface and a host computer as described above. The upper computer comprises the same number of clamping grooves as the number of the universal oscillographic cards based on the PCI interface; the universal oscillographic card based on the PCI interface is inserted into a slot of the upper computer; each universal oscillographic card based on the PCI interface comprises corresponding ID information; the upper computer firstly sends a control instruction to the universal oscillographic card based on the PCI interface corresponding to the ID information according to the ID information, so that the universal oscillographic card based on the PCI interface corresponding to the ID information executes the corresponding control instruction, and the acquired data is displayed on the upper computer in a waveform mode. The specific implementation is the same or similar to that of embodiment 1, and the system can expand the number of universal oscillometric cards based on PCI interfaces and increase the number of sampling channels.
While the application has been described in detail in the foregoing general description and specific examples, it will be apparent to those skilled in the art that modifications and improvements can be made thereto. Accordingly, such modifications or improvements may be made without departing from the spirit of the application and are intended to be within the scope of the application as claimed.

Claims (10)

1. The utility model provides a general oscillographic card based on PCI interface which characterized in that, general oscillographic card inserts in the PCI draw-in groove of host computer, general oscillographic card includes: PCI interface circuit, field programmable gate array FPGA, signal amplitude control device, signal acquisition device and memory;
the PCI interface circuit establishes communication connection between the FPGA and the upper computer;
the FPGA is electrically connected with the signal amplitude control device, the signal acquisition device and the memory respectively;
the FPGA is used for receiving a control instruction transmitted by a user through the upper computer through the PCI interface, and the control instruction is used for instructing the FPGA to control the signal amplitude control device, the signal acquisition device and the memory to execute corresponding operations;
the signal amplitude control device is used for adjusting the amplitude of an input signal to obtain an adjusted signal;
the signal acquisition device is used for acquiring the adjusted signals, acquiring acquired data and sending the data to the FPGA;
the FPGA is used for storing the data acquired by the signal acquisition device into an external memory according to a preset triggering mode when the acquired data are determined to meet the preset triggering condition; when a data reading instruction of the upper computer is detected, the data is read from the memory and then transmitted to the upper computer for display, wherein the preset triggering mode corresponds to the preset triggering condition;
the signal amplitude control device specifically comprises: a signal interface and a gear selector;
the FPGA is electrically connected with the gear selector; the signal interface is connected with the gear selector;
the signal interface is used for receiving an input signal input from the outside;
the FPGA is used for sending gear selection parameters to the gear selector;
the gear selector is used for outputting an input signal of the signal interface through the selected gear range after selecting the gear range according to the gear range parameter; and/or the number of the groups of groups,
the FPGA is used for sending the amplification factor for amplifying the signal output by the gear selector.
2. The universal oscillometric card of claim 1, wherein the signal amplitude control means further comprises: a voltage controlled amplifier and a digital to analog converter DAC;
the FPGA is electrically connected with the DAC; the DAC is electrically connected with the voltage-controlled amplifier;
the FPGA is used for sending the amplification factor for amplifying the signal output by the gear selector to the DAC;
the DAC is used for converting the amplification factor of the signal output by the gear selector into a voltage signal to act on the voltage-controlled amplifier;
the voltage-controlled amplifier is used for amplifying the signal output by the gear selector according to the voltage signal.
3. The universal oscillometric card of claim 1, wherein,
the voltage controlled amplifier specifically includes: a low noise high speed operational amplifier and a voltage controlled gain amplifier;
the low-noise high-speed operational amplifier is used for performing first-stage amplification on the signal output by the gear selector;
the voltage-controlled gain amplifier is used for performing second-stage gain amplification on the signal subjected to the first-stage amplification by the low-noise high-speed operational amplifier.
4. The universal oscillometric card of claim 1, wherein the gear selector comprises: the device comprises a Darlington pipe, a relay and a voltage dividing network;
one end of the Darlington tube is electrically connected with the FPGA, and the other end of the Darlington tube is electrically connected with the relay; the voltage divider network includes: a low range channel and a high range channel;
the Darlington tube is used for driving a relay switch according to the gear range parameter so as to switch a low range channel or a high range channel in the voltage division network.
5. The universal oscillometric card of claim 1, wherein the signal acquisition means comprises: a low distortion differential amplifier, a filter, an analog-to-digital converter ADC, and a buffer;
the low-distortion differential amplifier is used for converting the signal amplified by the voltage-controlled amplifier into a differential signal;
the filter is used for filtering the differential signal;
the ADC is used for converting the filtered differential signals into digital signals;
the buffer is used for buffering the digital signals and inputting the digital signals to the FPGA.
6. The universal oscillometric card of claim 5, wherein the ADC is specifically configured to: and according to the sampling clock signal output by the FPGA, performing analog-digital AD conversion on the differential signal.
7. The universal oscillometric card of any of claims 1-6, wherein the control instructions are embodied in a key form.
8. The universal oscillometric card according to any of claims 1-6, wherein the predetermined triggering means comprises: external signal triggering, input signal level triggering, input signal pulse width triggering or input signal slope triggering.
9. The universal oscillometric card of claim 8, wherein when the predetermined trigger mode is an external signal trigger, the universal oscillometric card further comprises: an external signal interface and a photo coupler;
the external signal interface is electrically connected with the photoelectric coupler; the photoelectric coupler is electrically connected with the FPGA;
the external signal interface is used for receiving an external trigger signal; the photoelectric coupler is used for converting the external trigger signal into a TTL level signal.
10. A universal oscillometric system based on a PCI interface, wherein the system comprises a host computer and at least one universal oscillometric card based on a PCI interface, the universal oscillometric card being the oscillometric card according to any of claims 1-6;
the upper computer comprises clamping grooves with the same number as the universal oscillographic cards; the universal oscillographic card is inserted into a slot of the upper computer; and each universal oscillographic card contains a corresponding ID information;
and the upper computer sends a control instruction to the oscillographic card corresponding to the ID information according to the ID information, so that the oscillographic card corresponding to the ID information responds to the control instruction, and the acquired data is displayed on the upper computer in a waveform mode.
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