CN108899370A - The VDMOS device in integrated resistor area - Google Patents
The VDMOS device in integrated resistor area Download PDFInfo
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- CN108899370A CN108899370A CN201810961256.7A CN201810961256A CN108899370A CN 108899370 A CN108899370 A CN 108899370A CN 201810961256 A CN201810961256 A CN 201810961256A CN 108899370 A CN108899370 A CN 108899370A
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- 230000001413 cellular effect Effects 0.000 claims abstract description 82
- 210000000746 body region Anatomy 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims description 41
- 229910052751 metal Inorganic materials 0.000 claims description 41
- 239000000758 substrate Substances 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims 1
- 238000002955 isolation Methods 0.000 claims 1
- 238000011084 recovery Methods 0.000 abstract description 10
- 238000009825 accumulation Methods 0.000 abstract description 6
- 238000002347 injection Methods 0.000 abstract description 5
- 239000007924 injection Substances 0.000 abstract description 5
- 230000007246 mechanism Effects 0.000 abstract description 5
- 230000005404 monopole Effects 0.000 abstract description 4
- 230000000903 blocking effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- -1 and certainly Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Abstract
The present invention relates to a kind of VDMOS devices in integrated resistor area, the first conduction type ohmic contact regions and the first conductivity type body region is arranged in it between cellular groove, charge is injected in gate dielectric layer, under VDMOS forward conduction state, gate dielectric layer and the first conductivity type body region form accumulation layer, the second conductive-type body area is not present between cellular groove groove, conducting resistance will be greatly reduced.Under body diode on state, after a small amount of few charge of the electron of injection, first conduction type ohmic contact regions and the first conductivity type body region can be connected, to reduce the forward conduction voltage drop of body diode, conductive mechanism is based on monopole type at this time, minority carrier concentration is lower in first conduction type drift region, greatly improves the reverse recovery characteristic of body diode.Under VDMOS blocking state, the charge in gate dielectric layer can form depletion region, and compared with existing VDMOS structure, pressure resistance is constant.
Description
Technical field
The present invention relates to a kind of VDMOS device, especially a kind of VDMOS device in integrated resistor area belongs to VDMOS device
Technical field.
Background technique
VDMOS is most widely used one kind power device in power semiconductor, it have input impedance it is high, easily driving,
The advantages that switching speed is fast, thermal stability is good.In low-pressure field, groove gate type VDMOS device is because eliminating the area JFET resistance and tool
There is smaller cellular size, to be widely adopted with lower than conducting resistance.
Super node MOSFET is a kind of important power device occurred in recent years, its basic principle is charge balance original
Reason, by introducing super-junction structure in the drift region of common power MOSFET, substantially improves the conducting resistance of common MOSFET
Tradeoff between breakdown voltage, thus have been widely used in the power system.Basic super-junction structure is to hand over
The P column and N column replaced, and P column, N column strictly meet charge balance.Under reverse bias, due to transverse electric field and longitudinal electric field
Interaction, P post region and N column area will be completely depleted, and longitudinal electric field distribution tends to uniformly, thus theoretically puncture in depletion region
Voltage depends only on the thickness of Withstand voltage layer, unrelated with doping concentration, because Withstand voltage layer doping concentration can be improved nearly one
The order of magnitude, to significantly reduce the conducting resistance of device.
Trench gate VDMOS in the on-state, can be equivalent to not consider that drain electrode and source electrode connect by draining to the resistance of source electrode
When electric shock resistance, VDMOS conducting resistance RON mainly includes following part：Source region resistance (RN+), channel resistance (RCH), accumulation layer
Resistance (RA), drift zone resistance (RD) and resistance substrate (RSUB).For high pressure VDMOS device, due to drift doping concentration
Low, drift region is longer, and drift zone resistance (RD) accounts for relatively high.But for mesolow VDMOS and hyperconjugation VDMOS device, due to drift
It is larger to move area's doping concentration, channel resistance (RCH) accounts for relatively high, how to reduce channel resistance resistance into reduction conducting resistance
The key of RON.
In VDMOS application process, it usually needs work in third quadrant (N-MOSFET) or fourth quadrant (P-
MOSFET), as voltage adjusts mould group VRM (Voltage Regulator Module) and H bridge circuit for controlling motor.With P-
For MOSFET, traditional VDMOS is operable with second and fourth quadrant, and internal structure is integrated with PIN body diode.It integrates
PIN body diode due to PN junction Built-in potential Vbi (Si base device about 0.7V at room temperature, 4H-SiC device about 2.5~3.0V),
Therefore its conduction voltage drop is high, and Si base device is not less than 0.7V, and 4H-SiC base device is not less than 2.5V.In addition, being led in body diode
When logical, due to big injection effect, lead in drift region that there are a large amount of electron-hole pairs, during diode reverse recovery,
It needs to extract electron-hole pair, slow so as to cause its switching speed, reverse recovery loss is big, significantly limits circuit
Working frequency.For the switching speed for improving diode, the mode of electron irradiation or integrated schottky diode is generallyd use.But
Electron irradiation can improve VDMOS conducting resistance while its electron irradiation thermal stability is poor, and characteristic is easily degenerated.And integrated schottky
Diode, under the high temperature conditions, Leakage Current are big.
Reverse-biased Leakage Current further to solve the problems, such as Schottky diode is big, proposes integrated MOS diode, uses
Mos gate pole control diode is switched on or off, and such as the file of Publication No. CN107924950A, it discloses MOS diodes
With MOS channel resistance, MOS diode structure cell is complicated, and size is larger, while needing to adjust the threshold value electricity of MOS diode
Pressure, technique, structure is complicated.
Summary of the invention
The purpose of the present invention is overcoming the deficiencies in the prior art, a kind of VDMOS device in integrated resistor area is provided,
Its is compact-sized, and the conducting resistance of VDMOS can be effectively reduced, and reduces VDMOS body diode forward conduction voltage drop, improves two pole of body
The reverse recovery characteristic of pipe reduces the power consumption of VDMOS.
According to technical solution provided by the invention, the VDMOS device in the integrated resistor area, including semiconductor substrate and
Positioned at the cellular region at the semiconductor substrate center, the semiconductor substrate is including the first conduction type drift region and is located at institute
State second conductivity type body region on the first conduction type drift region top；
On the section of the VDMOS device, cellular region includes several cellulars, and the cellular includes two adjacent cellular ditches
Slot, cellular groove is located in the second conductivity type body region and the slot bottom of cellular groove protrudes into below second conductivity type body region
The first conduction type drift region in；Gate dielectric layer is set in the inner wall of cellular groove, in the cellular groove of setting gate dielectric layer
Interior filling Gate Electrode Conductive polysilicon；
First conduction type ohmic contact regions, the first conduction type Ohmic contact are set between the cellular groove
Area is contacted with the outer wall of cellular groove, above first conduction type ohmic contact regions and the first conduction type drift region
Source metal Ohmic contact, the insulating medium layer and Gate Electrode Conductive polysilicon that the source metal passes through cellular groove notch
It is dielectrically separated from；Charge is injected in the gate dielectric layer.
First conduction type source region and the second conduction type source region be set in second conductivity type body region, described the
One conduction type source region is contacted with the outer wall of cellular groove, and the first conduction type source region is located at cellular groove and the second conduction type
The two sides of source region, source metal and the first conduction type source region, the second conduction type source region Ohmic contact.
The first conductivity type body region, the first conductive-type are also set up immediately below first conduction type ohmic contact regions
The doping concentration in the area Xing Ti less than the doping concentration of the first conduction type ohmic contact regions, lead with first by the first conductivity type body region
Electric type ohmic contact regions contact, the first conductivity type body region is contacted with the outer wall of cellular groove.
The density of charge is 1e11/cm in the gate dielectric layer2~1e13/cm2。
At the back side of first conduction type drift region, the first conductivity type substrate, the first conduction type lining are set
Bottom and the first conduction type drift region are adjacent, and drain metal layer, the drain electrode gold are arranged in first conductivity type substrate
Belong to layer and the first conductivity type substrate Ohmic contact.
Super-junction structure is set in first conduction type drift region, and the super-junction structure includes several alternatively distributed
First conductivity type columns and the second conductivity type columns, the second conductivity type columns are located at the underface of cellular groove, and second leads
Electric type column is contacted with the slot bottom of cellular groove.
The material of the semiconductor substrate includes silicon.
In " first conduction type " and " the second conduction type " the two, N-type power VDMOSFET device, first is led
Electric type refers to N-type, and the second conduction type is p-type；For p-type power VDMOSFET device, the first conduction type and the second conduction type
Signified type and N-type semiconductor device is exactly the opposite.
Advantages of the present invention：First conduction type ohmic contact regions and the first conduction type are set between cellular groove
Body area, the first conduction type ohmic contact regions and source metal Ohmic contact, inject required charge in gate dielectric layer,
Under VDMOS forward conduction state, the gate dielectric layer of neighbouring first conductivity type body region forms accumulation layer, between cellular groove groove
There is no the second conductive-type body areas, therefore compared with existing VDMOS, no channel resistance.For low-voltage VDMOS and hyperconjugation VDMOS,
Conducting resistance will be greatly reduced.Under body diode on state, after a small amount of few charge of the electron of injection, the first conduction type Europe
Nurse contact zone and the first conductivity type body region can be connected, so that the forward conduction voltage drop of body diode is reduced, it is conductive at this time
Mechanism is based on monopole type, and minority carrier concentration is lower in the first conduction type drift region, greatly improves body diode
Reverse recovery characteristic.Under VDMOS blocking state, the charge in gate dielectric layer can form depletion region, tie with existing VDMOS
Structure is compared, and pressure resistance is constant, reduces the power consumption of VDMOS.
Detailed description of the invention
Fig. 1 is the structural diagram of the present invention.
Fig. 2 is pressure-resistant schematic diagram of the invention.
Fig. 3 is the comparison diagram of VDMOS device and existing groove-shaped VDMOS pressure resistance curve of the invention.
Fig. 4 is the comparison diagram of VDMOS device and existing groove-shaped VDMOS forward conduction curve of the invention.
Fig. 5 is the comparison diagram that curve is connected VDMOS device of the invention with existing groove-shaped VDMOS body diode.
Fig. 6 is the comparison diagram of VDMOS device and existing groove-shaped VDMOS body diode reverse recovery curve of the invention.
Fig. 7 is another structural schematic diagram of the invention.
Fig. 8 is the schematic diagram of the VDMOS device of superjunction of the present invention.
Fig. 9 is the pressure-resistant schematic diagram of VDMOS device in Fig. 8.
Description of symbols：1- source metal, 2- insulating medium layer, 3-P+ source region, the ohmic contact regions 4-P+, the source 5-N+
Area, the area 6-N Xing Ti, 7- gate dielectric layer, 8- Gate Electrode Conductive polysilicon, 9-P type drift region, 10-P+ substrate, 11- drain metal layer,
The area 12-P Xing Ti and 13-N column.
Specific embodiment
Below with reference to specific drawings and examples, the invention will be further described.
As shown in Figure 1, Figure 2 and Figure 7：In order to which the conducting resistance of VDMOS is effectively reduced, VDMOS body diode is being reduced just
To conduction voltage drop, improve the reverse recovery characteristic of body diode, reduces the power consumption of VDMOS, by taking p-type VDMOS device as an example, this hair
Bright includes semiconductor substrate and positioned at the cellular region at the semiconductor substrate center, and the semiconductor substrate includes P drift
Area 9 and the area NXing Ti 6 positioned at 9 top of P drift area；
On the section of the VDMOS device, cellular region includes several cellulars, and the cellular includes two adjacent cellular ditches
Slot, cellular groove is located in the area NXing Ti 6 and the slot bottom of cellular groove protrudes into the P drift area 9 of 6 lower section of the area NXing Ti；
Gate dielectric layer 7 is set in the inner wall of cellular groove, Gate Electrode Conductive polysilicon 8 is filled in the cellular groove of setting gate dielectric layer 7；
The ohmic contact regions P+ 4, the outer wall of the ohmic contact regions P+ 4 and cellular groove are set between the cellular groove
It contacts, 1 Ohmic contact of source metal of the ohmic contact regions P+ 4 and 9 top of P drift area, the source metal 1
It is dielectrically separated from by the insulating medium layer 2 and Gate Electrode Conductive polysilicon 8 of cellular groove notch；It is injected in the gate dielectric layer 7
There is charge.
Specifically, the material of the semiconductor substrate includes silicon, and certainly, semiconductor substrate can also be selected other common
Material, specifically can according to need and selected, details are not described herein again.Cellular region is located at the center of semiconductor substrate,
Terminal protection area is arranged in the outer ring of cellular region, can be protected to cellular region using terminal protection area, terminal protection area and cellular
The specific structure of specific matching relationship and terminal protection area between area, which can according to need, carries out selection setting, specially
Known to those skilled in the art, details are not described herein again.
For p-type VDMOS device, semiconductor substrate includes P drift area 9, and N-type is arranged in the top in P drift area 9
Body area 6, the thickness in the area NXing Ti 6 are less than the thickness in P drift area 9.It include several cellulars in cellular region, the cellular in cellular region
And it joins together.For each cellular, cellular includes two cellular grooves, and cellular groove is located in the area NXing Ti 6, cellular groove
Slot bottom be located in the P drift area 9 of the lower section of the area NXing Ti 6.Gate dielectric layer 7 is covered on the side wall and bottom wall of cellular groove, grid
Pole conductive polycrystalline silicon 8 is filled in cellular groove.In the gate dielectric layer (gate dielectric layer 7 can specifically use silica) 7
The density of charge is 1e11/cm2~1e13/cm2.When it is implemented, existing common technological means can be used to gate dielectric layer
Charge needed for 7 injections, the specific process for injecting charge is known to those skilled in the art, and details are not described herein again.
The doping concentration of the ohmic contact regions P+ 4 is greater than the doping concentration in P drift area 9, and the ohmic contact regions P+ 4 are located at two-spot
Between born of the same parents' groove, the ohmic contact regions P+ 4 are contacted with the lateral wall on cellular groove top, and the ohmic contact regions P+ 4 are in P drift area 9
Interior depth is less than the depth in the area NXing Ti 6.In the positive surface in P drift area 9, source metal 1, the source electrode gold are set
Belong to layer 1 and 4 Ohmic contact of the ohmic contact regions P+.Insulating medium layer 2 covers the notch of cellular groove, and source metal 1 passes through exhausted
Edge dielectric layer 2 is dielectrically separated from Gate Electrode Conductive polysilicon 8, and insulating medium layer 2 can use common insulating materials.
In addition, setting P+ source region 3 and N+ source region 5 in the area NXing Ti 6, the outer wall of the P+ source region 3 and cellular groove
Contact, P+ source region 3 are located at the two sides of cellular groove and N+ source region 5, and source metal 1 and P+ source region 3,5 ohm of N+ type source region connect
Touching.The depth of P+ source region 3, N+ source region 5 in the area NXing Ti 6 is consistent, the depth of P+ source region 3 and the depth of the ohmic contact regions P+ 4
It is consistent.The source electrode of VDMOS device can be formed using source metal 1.When it is implemented, P drift area 9 top also
Gate metal layer, the gate metal layer and 8 Ohmic contact of Gate Electrode Conductive polysilicon are set, can be formed using gate metal layer
The gate electrode of VDMOS device, gate metal layer are not shown in the figure, position etc. of the gate metal layer above P drift area 9
Existing common mode can be used, specially known to those skilled in the art, details are not described herein again.
Further, the area PXing Ti 12 is also set up in the underface of the ohmic contact regions P+ 4, the doping in the area PXing Ti 12 is dense
Degree is less than the doping concentration of the ohmic contact regions P+ 4, and the area PXing Ti 12 is contacted with the ohmic contact regions P+ 4, the area PXing Ti 12 and cellular ditch
The outer wall of slot contacts.
In the embodiment of the present invention, the area PXing Ti 12 is between two cellular grooves, the area PXing Ti 12 and two sides cellular groove
Lateral wall contact, the area PXing Ti 12 are located at the top of cellular groove slot bottom, and the doping concentration in the area PXing Ti 12 is less than P+ Ohmic contact
The doping concentration in area 4.
Further, P+ substrate 10, the P+ substrate 10 and P drift area 9 are set at the back side in the P drift area 9
It is adjacent, drain metal layer 11, the drain metal layer 11 and 10 Ohmic contact of P+ substrate are set on the P+ substrate 10.
In the embodiment of the present invention, the doping concentration of P+ substrate 10 is greater than the doping concentration in P drift area 9, P+ substrate 10 and P
Type drift region 9 is adjacent, and drain metal layer 11 and 10 Ohmic contact of P+ substrate can form VDMOS device using drain metal layer 11
Drain electrode.
As shown in Fig. 3, Fig. 4, Fig. 5 and Fig. 6, for the contrast simulation of VDMOS device and existing groove-shaped VDMOS of the invention
Schematic diagram, wherein in VDMOS device and existing trench VDMOS device of the invention, the size of cellular is 2 μm, P drift
Area 9 with a thickness of 6.5 μm, the depth of cellular groove is 2 μm, gate dielectric layer 7 with a thickness of 100nm, in VDMOS device of the present invention
The density of charge is 6e11/cm in gate dielectric layer 72.In simulations, specific voltage etc. with existing identical, specially this skill
Art field personnel are consistent, and details are not described herein again.Simulation result show VDMOS device of the invention with there is identical size, phase
Compared with the conventional trench gate VDMOS structure of device parameters, breakdown voltage is essentially identical, as shown in Figure 3.VDMOS device of the present invention
The conducting resistance RON of part is lower, as shown in Figure 4.Body diode conduction voltage drop of the present invention is lower, as shown in Figure 5.Body two of the present invention
Pole pipe reverse recovery time, reverse current peak value, reverse recovery charge is lower, as shown in Figure 6.
As shown in Figure 8 and Figure 9, super-junction structure is set in the P drift area 9, and the super-junction structure includes several friendships
For the P column and N column 13 of distribution, N column 13 is located at the underface of cellular groove, and N column 13 is contacted with the slot bottom of cellular groove.
In the embodiment of the present invention, P drift area 9 can also be arranged super-junction structure to get arrive superjunction VDMOS device,
Super-junction structure includes alternatively distributed P column and N column 13, and N column 13 is located at the underface of cellular groove, N column 13 and cellular groove
Slot bottom contact.For the VDMOS with super-junction structure, the specific structure of cellular region is same as described above, can specifically refer to upper
The explanation stated, details are not described herein again.
In the embodiment of the present invention, under VDMOS forward conduction state, the gate dielectric layer 7 in the neighbouring area PXing Ti 12 forms accumulation
Layer, the area NXing Ti 6 is not present between cellular groove groove, therefore compared with existing VDMOS, no channel resistance.For low pressure
VDMOS and hyperconjugation VDMOS, conducting resistance of the invention will be greatly reduced.Under body diode on state, a small amount of in injection
After few charge of the electron, the ohmic contact regions P+ 4 and the area PXing Ti 12 can be connected, so that the forward conduction voltage drop of body diode is reduced,
Conductive mechanism is based on monopole type at this time, and minority carrier concentration is lower in P drift area 9, greatly improves body diode
Reverse recovery characteristic.Under VDMOS blocking state, the charge in gate dielectric layer 7 can form depletion region, with existing VDMOS
Structure is compared, and pressure resistance is constant.
As shown in Figure 1, Figure 2, shown in Fig. 7, Fig. 8 and Fig. 9, region I is the cell region of groove-shaped VDMOS, and region II is this hair
The resistance region integrated in bright.When specific works, when making Gate Electrode Conductive polysilicon 8 and source metal by gate metal layer
1 connects zero point position, and drain metal layer 11 meets negative pressure, i.e. VGS=0V, VDS<When 0V, since there are positive charge, meetings in gate dielectric layer 7
The area PXing Ti 12 being clipped among cellular groove is exhausted, depletion layer is formed below the ohmic contact regions P+ 4 of region II, to hinder
Subchannel is powered off, as shown in Figure 2.With the increase of VDS negative voltage, depletion region is extended to 11 side of drain metal layer, Ke Yibao
Card pressure resistance is identical as existing VDMOS device.
When making Gate Electrode Conductive polysilicon 8 connect negative pressure by gate metal layer, and source metal 1 connects zero point position, drain electrode
Metal layer 11 connects negative pressure, i.e. VGS<0V, VDS<When 0V, when VGS negative pressure is smaller, the area NXing Ti 6 of VDMOS device can not transoid,
It can not be connected；For region II, VGS negative pressure is not enough to balance out the positive charge in gate dielectric layer 7,4 lower section of the ohmic contact regions P+
Depletion layer still remain, VDMOS can not be connected.With the increase , ∣ VGS ∣ of VGS negative pressure>The area NXing Ti 6 of ∣ VTH ∣, VDMOS
Transoid forms the hole channel from source metal 1 to drain metal layer 11, break-over of device；For region II, VGS negative pressure is supported
The positive charge to disappear in gate dielectric layer 7 forms hole accumulation layer, break-over of device, since ditch is not present in region II in trenched side-wall
Therefore road resistance, but the drift zone resistance of accumulation layer and one fixed width can reduce VDMOS device conducting resistance.
When making Gate Electrode Conductive polysilicon 8 by gate metal layer, and source metal 1 connects zero potential, drain metal layer 1
Meet positive pressure, i.e. VGS=0V, VDS>The Europe P+ in PIN diode and region II when 0V, when VDS positive pressure is smaller, in region I
Nurse contact zone 4, the area PXing Ti 12 can not all be connected.As VDS positive pressure incrementally increases, P is injected by drain metal layer 11 in a small amount of hole
Type drift region 9 compensates for the negative electrical charge in the II of region, and depletion region disappears, and region II forms golden from drain metal layer 11 to source electrode
Belong to layer 1 hole channel, VDMOS device conducting, at this point, in the I of region PIN diode (PIN diode be N-type
Body area 6 is formed with P drift area 9) it is not fully on, main conductive mechanism is that monopole is conductive.If VDS is further increased, area
PIN diode conducting in the I of domain, main conductive mechanism are bipolar conduction.
Claims (7)
1. a kind of VDMOS device in integrated resistor area, the member including semiconductor substrate and positioned at the semiconductor substrate center
Born of the same parents area, the semiconductor substrate include the first conduction type drift region and positioned at first conduction type drift region top
Second conductivity type body region；
On the section of the VDMOS device, cellular region includes several cellulars, and the cellular includes two adjacent cellular grooves,
Cellular groove is located in the second conductivity type body region and the slot bottom of cellular groove protrudes into below second conductivity type body region
In first conduction type drift region；Gate dielectric layer is set in the inner wall of cellular groove, in the cellular groove of setting gate dielectric layer
Fill Gate Electrode Conductive polysilicon；It is characterized in that：
First conduction type ohmic contact regions are set between the cellular groove, first conduction type ohmic contact regions with
The outer wall of cellular groove contacts, the source electrode above first conduction type ohmic contact regions and the first conduction type drift region
Metal layer Ohmic contact, the insulating medium layer and Gate Electrode Conductive polysilicon insulation that the source metal passes through cellular groove notch
Isolation；Charge is injected in the gate dielectric layer.
2. the VDMOS device in integrated resistor area according to claim 1, it is characterized in that：Second conductivity type body region
Outside the first conduction type source region of interior setting and the second conduction type source region, the first conduction type source region and cellular groove
Wall contact, the first conduction type source region are located at the two sides of cellular groove and the second conduction type source region, source metal and first
Conduction type source region, the second conduction type source region Ohmic contact.
3. the VDMOS device in integrated resistor area according to claim 1, it is characterized in that：In first conduction type Europe
The first conductivity type body region is also set up immediately below nurse contact zone, the doping concentration of the first conductivity type body region is less than the first conduction
The doping concentration of type ohmic contact regions, the first conductivity type body region are contacted with the first conduction type ohmic contact regions, and first leads
Electric type body region is contacted with the outer wall of cellular groove.
4. the VDMOS device in integrated resistor area according to claim 1, it is characterized in that：Charge in the gate dielectric layer
Density is 1e11/cm2~1e13/cm2。
5. the VDMOS device in integrated resistor area according to claim 1, it is characterized in that：It is floated in first conduction type
The first conductivity type substrate is arranged in the back side for moving area, and first conductivity type substrate and the first conduction type drift region are adjacent,
Drain metal layer is set in first conductivity type substrate, and the drain metal layer connects with first conductivity type substrate ohm
Touching.
6. the VDMOS device in integrated resistor area according to claim 1, it is characterized in that：It is floated in first conduction type
It moves and super-junction structure is set in area, the super-junction structure includes several alternatively distributed first conductivity type columns and the second conductive-type
Type column, the second conductivity type columns are located at the underface of cellular groove, and the second conductivity type columns are contacted with the slot bottom of cellular groove.
7. the VDMOS device in integrated resistor area according to claim 1, it is characterized in that：The material of the semiconductor substrate
Including silicon.
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| WO2020151088A1 (en) * | 2019-01-21 | 2020-07-30 | 东南大学 | Super-junction power vdmos having extremely low reverse recovery charge |
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