CN108899324A - Three-dimensional storage - Google Patents
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- CN108899324A CN108899324A CN201811092434.3A CN201811092434A CN108899324A CN 108899324 A CN108899324 A CN 108899324A CN 201811092434 A CN201811092434 A CN 201811092434A CN 108899324 A CN108899324 A CN 108899324A
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention relates to a kind of three-dimensional storage, the three-dimensional storage includes：Storage stack structure, the storage stack structure include the control grid and insulating layer being alternately stacked；Channel pore structure runs through the storage stack structure；The width of the control grid is less than the width of insulating layer, so that having groove between adjacent insulating layer, the part channel pore structure is located in the groove.The performance of above-mentioned three-dimensional storage is improved.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of three-dimensional storages.
Background technique
In recent years, the development of flash memory (Flash Memory) memory is especially rapid.Flash memories are mainly characterized by
It can keep the information of storage for a long time in the case where not powered, and have that integrated level is high, access speed is fast, is easy to wipe and rewrite
The advantages that, thus be widely used in the multinomial field such as microcomputer, automation control.In order to further increase flash memory storage
The bit density (Bit Density) of device, while a cost (Bit Cost) is reduced, three-dimensional flash memories (3D NAND) skill
Art is rapidly developed.
In 3D NAND flash memory structure, including memory array structure, the memory array structure include to multiple-level stack knot
Structure.With being continuously increased for the stacked structure composite dielectric film number of plies, (CH) of the high depth-to-width ratio channel in small channel hole
It is more difficult that function side wall is formed under critical size (CD) background, in channel hole.Further, since traditional rear grid method is needed in phosphorus
After sour wet process removes false grid SiN, first depositing TiN thin film and high K dielectric film fill out metal gates W again, this can to a certain extent
The space of filling metal gates is cut down, the technology difficulty for forming metal gates is increased.
Summary of the invention
The technical problem to be solved by the invention is to provide a kind of three-dimensional storages, improve the three-dimensional storage of formation
Performance.
Technical solution of the present invention also provides a kind of three-dimensional storage, including：Storage stack structure, the storage stack knot
Structure includes the control grid and insulating layer being alternately stacked；Channel pore structure runs through the storage stack structure；The control grid
Width be less than the width of insulating layer so that having groove between adjacent insulating layer, the part channel pore structure is located at described
In groove.
Optionally, further include：Gate dielectric layer, between the control gate terminal portion and the channel pore structure, at least
Cover the end of the control grid sidewall surfaces opposite with the channel pore structure.
Optionally, the width of the control grid is less than the width of insulating layer, so that there is groove between adjacent insulating layer,
The bottom portion of groove is the end face for controlling grid；The gate dielectric layer at least covers the bottom surface of the groove.
Optionally, the gate dielectric layer also covers the sidewall surfaces of the insulating layer around channel pore structure.
Optionally, the channel pore structure is formed in channel hole, including：The charge being at least partially disposed in the groove
Barrier layer；It covers the electric charge capture layer of channel hole side wall and charge barrier layer surface, cover the electric charge capture layer
The channel layer of tunnel layer and the covering tunnel layer；Channel positioned at the channel layer surface and the full channel hole of filling is situated between
Matter layer.
Optionally, the control grid include grid and be located at the grid and insulating layer, grid and gate dielectric layer it
Between diffusion barrier layer.
Optionally, the storage stack structure includes nucleus and the stepped area around the nucleus, described
Stepped area exposes the end of each layer of control grid；Dielectric layer is covered in the stepped area.
It optionally, further include the contact portion that gate terminal portion surface is controlled through the dielectric layer to each layer.
It optionally, further include the array common source for running through the storage stack structure.
Optionally, the three-dimensional storage is 3D nand memory.
The diffusion barrier layer of the channel pore structure of three-dimensional storage of the invention is formed in the groove between adjacent insulating layer
It is interior, space in channel hole is prevented take up, the difficulty for forming channel pore structure in channel hole can be reduced, improve channel pore structure
Quality, and then improve the performance of three-dimensional storage；The size in channel hole can also be reduced so that three-dimensional storage may further be improved
The integrated level of device.
Further, the gate dielectric layer of the three-dimensional storage be only formed in control grid end face and channel pore structure it
Between, it is not take up the formation space of control grid, to reduce the difficulty for forming control grid between adjacent insulating layer, improves control
The quality of grid processed, and then improve the performance of memory.
Detailed description of the invention
Fig. 1 to Fig. 8 is the structural schematic diagram of the forming process of the three-dimensional storage of the embodiment of the invention；
Fig. 9 to Figure 11 is the structural schematic diagram of the forming process of the three-dimensional storage of the embodiment of the invention；
Figure 12 is the structural schematic diagram of the three-dimensional storage of the embodiment of the invention.
Specific embodiment
The specific embodiment of three-dimensional storage provided by the invention and forming method thereof is done in detail with reference to the accompanying drawing
Explanation.
In the forming process of existing three-dimensional storage, after substrate surface forms stacked structure, need to etch described
Stacked structure forms channel hole, then forms function material layer in channel hole inner wall surface, then etches the function material
The bed of material exposes the substrate of channel hole bottom.
Inventors have found that the integrated level with memory is higher and higher, when the critical size in channel hole is too small, ditch will lead to
The function material layer that road hole bottom is formed can not be opened.
Channel pore structure and then removal sacrificial layer are formed in channel hole, are formed between the insulating layer of stacked structure
Opening, and it is initially formed gate dielectric layer in opening inner wall surface, then re-form the control grid of filling opening.Inventor is further
It was found that the part gate dielectric layer that the gate dielectric layer is only located between control gate terminal face and channel pore structure can play work
With, it is meant that the gate dielectric layer at remaining position is extra part, can occupy the space in opening, to the filling of control grid
Bring difficulty.
Also, since gate dielectric layer deposits after removal of the sacrificial layer, then the control of the stepped area in storage organization
Gate surface can also be covered with gate dielectric layer.In the contact hole being subsequently formed on stepped region, since the etching of contact hole needs
Control gate surface is stopped at through gate dielectric layer, will increase the difficulty of the etching selection ratio of contact hole in this way.
In view of the above-mentioned problems, inventor proposes a kind of forming method of new three-dimensional storage, Fig. 1 is specifically please referred to figure
8 be the structural schematic diagram of the forming process of the three-dimensional storage of a specific embodiment.
Referring to FIG. 1, providing substrate 100,100 surface of substrate is formed with stacked structure 110, the stacked structure
110 include the sacrificial layer 112 and insulating layer 111 being alternately stacked along 100 surface direction of vertical substrates；It is formed and is tied through the stacking
The channel hole 130 of structure 110.
The substrate 100 can be monocrystalline substrate, Ge substrate, SiGe substrate, SOI or GOI etc.；According to the reality of device
Demand can choose suitable semiconductor material as the substrate 100, be not limited thereto.In the specific embodiment, institute
Stating substrate 100 is monocrystalline silicon wafer crystal.
The stacked structure 110 includes the insulating layer 111 and sacrificial layer being stacked with along 100 surface direction of vertical substrates
112.In a specific embodiment, the material of the insulating layer 111 is silica, and the material of the sacrificial layer 112 is nitrogen
SiClx；In other specific embodiments, the insulating layer 111 and sacrificial layer 112 can also use other suitable materials.
In other specific embodiments, there can also be cap layer (not shown) at the top of the stacked structure 110,
For protecting the stacked structure 110, the mask layer that etching stacked structure 110 forms channel hole 130 can also be used as.
The stacked structure 110 is etched to 100 surface of substrate by dry etch process, forms channel hole 130.This is specific
In embodiment, the channel hole 130 has vertical sidewall.In other specific embodiments, the channel hole 130 can also be with
With sloped sidewall.The channel can be adjusted by adjusting etch process parameters or using high aspect ratio technique etc.
The gradient of 130 side wall of hole.
In the specific embodiment, after forming the channel hole 130, further include：In 130 bottom of channel hole
100 surface of substrate forms epitaxial semiconductor layer (not shown).It, can also be in subsequent step in other specific embodiments
In, form the epitaxial semiconductor layer for being located at 130 bottom of channel hole.
Referring to FIG. 2, for the enlarged diagram of partial structurtes 20 in Fig. 1, follow-up process will continue on the basis of Fig. 2 into
Row description.
Referring to FIG. 3, being etched back along 130 side wall of channel hole to the sacrificial layer 112, formed positioned at adjacent exhausted
Groove 301 between edge layer 111.
The sacrificial layer 112 can be etched back using dry etch process, under hyperbaric environment, be selected to described
There is sacrificial layer 112 etching gas compared with high etch selectivity to perform etching.In a specific embodiment, the dry method is carved
The etching gas that etching technique uses includes CH3F and CH2F2, etching gas flow is 80sccm~120sccm, and pressure is
25mtorr~35mtorr, bias voltage are 800V~1500V.
By controlling the technological parameter of etching process, the depth of the groove 301 can accurately be controlled.In the tool
In body embodiment, the depth of the groove 201 is the charge resistance in subsequent gate dielectric layer to be formed and channel pore structure
The sum of thickness of barrier.
Referring to FIG. 4, forming the gate dielectric layer 401 for covering the channel hole 130 and 301 inner wall surface of the groove.
It, should in order to improve the Step Coverage performance of the gate dielectric layer 401 since the depth in the channel hole 130 is larger
In specific embodiment, the gate dielectric layer 401 is formed using atom layer deposition process.Also, use atom layer deposition process
The thickness for the gate dielectric layer 401 to be formed can be accurately controlled.
The material of the gate dielectric layer 401 can be the insulating materials such as silica, silicon oxynitride.Preferably, the grid are situated between
The material of matter layer 401 can be at least one of high-k dielectric materials such as hafnium oxide, aluminium oxide, zirconium oxide and lanthana.It should
In specific embodiment, the gate dielectric layer 401 not only covers the inner wall surface in the channel hole 130, also covers the insulation
The inner wall surface of groove 301 between layer 111.
In another specific embodiment, 130 side of channel hole further can also be located at by etching technics removal
The gate dielectric layer of wall and bottom surface only retains the gate dielectric layer 401 for being located at 301 inner wall surface of groove, to avoid institute
It states gate dielectric layer 401 and occupies space in the channel hole 130.
Referring to FIG. 5, forming the charge resistance for covering 130 inner wall surface of channel hole and filling the full groove 301
Obstructing material layer 501.
The charge blocking material layer 501 can be formed using atom layer deposition process, to accurately control the blocking
The thickness of material layer 501.In other specific embodiments, it can also be formed using chemical vapor deposition or other techniques described
Charge blocking material layer 501.
In the specific embodiment, the material of the charge blocking material layer 501 is silica.The charge blocking material
501 covering of the layer gate dielectric layer 401 and the full groove 301 (please referring to Fig. 4) of filling.
Referring to FIG. 6, the charge blocking material layer 501 that removal is located at 130 inner wall surface of channel hole (please refers to figure
5), retain the barrier material layer in groove 301 (please referring to Fig. 4) as electric charge barrier layer 601.
The charge blocking material layer of 130 side wall of channel hole and bottom surface is removed, can be hindered to avoid the charge
Obstructing material layer occupies the space inside the channel hole 130.In the case where the characteristic size in the channel hole 130 is certain, institute
It states in the groove 301 that electric charge barrier layer 601 is formed between the insulating layer 111, prevents take up the space in channel hole 130, from
And it reduces the subsequent formation other materials layer in the channel hole 130 and performs etching the difficulty of technique.
The charge blocking material layer 501 can be performed etching using dry etch process, by controlling etching technics
Parameter, so that dry etching has isotropism, is located at institute for example, by using lower bias power etc. so as to removal simultaneously
The charge blocking material layer for stating 130 side wall of channel hole and bottom surface retains electric charge barrier layer 601 in groove 301.The tool
In body embodiment, etching the etching gas that the charge blocking material layer 501 uses includes C4F8And CO, etching gas flow
For 60sccm~120sccm, pressure is 35mtorr~45mtorr, and bias voltage is 800V~1500V.
In other specific embodiments, can also by wet-etching technology to the charge blocking material layer 501 into
Row etching.
In other specific embodiments, the charge blocking material layer of 130 inner wall surface of channel hole can also be retained
501, step shown in fig. 6 is not executed, to reduce processing step.
Referring to FIG. 7, sequentially forming covering channel hole side wall and electric charge barrier layer in the channel hole 130
The electric charge capture layer 602 on 601 surfaces, the tunnel layer 603 of the covering electric charge capture layer 602 and the covering tunnel layer 603
Channel layer 604；The channel dielectric layer 605 for filling the full channel hole is formed on 604 surface of channel layer.
It, can be after forming the electric charge barrier layer 601, first in the channel hole 130 in the specific embodiment
The substrate surface of bottom forms epitaxial semiconductor layer, then re-forms the electric charge capture layer 602, tunnel layer 603, channel layer
604 and channel dielectric layer 605.
The forming method of the electric charge capture layer 602, tunnel layer 603 and channel layer 604 includes：In the channel hole
After wall surface sequentially forms charge-trapping material layer, tunneling material layer and channel material, etching is located at the channel bottom hole
Charge-trapping material layer, tunneling material layer and the layer of channel material in portion, expose the epitaxial semiconductor of channel hole bottom
Layer surface；Then the layer of channel material for covering the epitaxial semiconductor layer surface is re-formed, so that the channel layer and described outer
Prolong the connection of semiconductor layer 131；Re-form the channel dielectric layer 605 for filling the full channel hole 130.
In other specific embodiments, the formation side of the electric charge capture layer 602, tunnel layer 603 and channel layer 604
Method can also include：In the channel hole, sidewall surfaces sequentially form charge-trapping material layer, tunneling material layer, etch the ditch
The charge-trapping material layer of road hole bottom, tunneling material layer expose epitaxial semiconductor layer, are formed and are located at channel hole sidewall surfaces
Electric charge capture layer 602 and tunnel layer 603, then form the ditch for covering the tunnel layer 603 and 131 surface of epitaxial semiconductor layer
Channel layer 604；Re-form the channel dielectric layer 605 for filling the full channel hole 130.
In the specific embodiment, the channel pore structure of the three-dimensional storage includes：Electric charge barrier layer 601, charge are caught
Obtain layer 602, tunnel layer 603, channel layer 604 and channel dielectric layer 605.
Since the electric charge barrier layer 601 is in the groove between insulating layer 111, the channel hole 130 is prevented take up
Inner space, therefore, deposition steps when can reduce to form above-mentioned electric charge capture layer 602, tunnel layer 603 and channel layer 604
Rapid and etch step difficulty is conducive to the performance for improving the channel pore structure formed.
Referring to FIG. 8, removing the sacrificial layer 112, the opening between adjacent insulating layer 111 is formed；Form filling
The control grid 800 of the opening.
In a specific embodiment, it is initially formed the grid line separate slot through the stacked structure；Then along the grid
Line separate slot side wall removes the sacrificial layer 112 (please referring to Fig. 7) using wet-etching technology.
The control grid 800 includes covering the diffusion barrier layer 801 of the opening inner wall surface and being located at the expansion
Dissipate the grid 802 that the full opening is filled on 801 surface of barrier layer.It is a in other specific embodiments, the control grid 800
It can also only include the grid 802.
The material of the diffusion barrier layer 801 is at least one of TiN, TaN, Ti or TiW, can stop the grid
802 material is to external diffusion.The diffusion barrier layer 801 can be formed, by atom layer deposition process accurately to control institute
The thickness of diffusion barrier layer 801 is stated, and makes the diffusion barrier layer 801 step coverage with higher.
The material of the grid 802 is at least one of polysilicon, aluminium, copper or tungsten.Atomic layer deposition work can be used
Skill or chemical vapor deposition process etc. form the grid 802.
In the specific embodiment, the material of the diffusion barrier layer 801 is TiN, is formed using atom layer deposition process
The diffusion barrier layer 801；The material of the grid 802 is W, forms the grid 802 using chemical vapor deposition process.
Due to after removal sacrificial layer 112 forms opening, no longer needing to shape in the opening in the specific embodiment
At gate dielectric layer, therefore the diffusion barrier layer 801 and grid 802 can occupy entire open space；Therefore, it can reduce shape
At the difficulty of the diffusion barrier layer 801 and grid 802.
Between the control grid 800 and channel pore structure, the grid as storage unit are situated between the gate dielectric layer 401
Matter layer.
Figure 12 is please referred to, in another embodiment of the present invention, (can be please referred to forming the groove 301
After Fig. 3), the electric charge barrier layer 601 is directly formed in the groove 301, without forming the gate dielectric layer 401；
It is subsequent to remove the sacrificial layer 112, it is formed after the opening between adjacent insulating layer 111, first in the opening
Inner wall surface forms gate dielectric layer 401', then forms the control gate of the filling opening on the surface the gate dielectric layer 401' again
Pole 800.In the specific embodiment, without changing the formation process and step of gate dielectric layer 401', it is easy to technique realization, it can be into
One step improves the space that channel pore structure is formed in channel hole 130.
The forming method of above-mentioned three-dimensional storage carve after forming channel hole, to the sacrificial layer of channel hole side wall
Erosion forms groove, then forms gate dielectric layer on groove inner wall surface, then re-forms channel pore structure, subsequent without sacrificial in removal
Gate dielectric layer is re-formed in the opening that domestic animal layer is formed, so as to improve the space for forming control grid in the opening, drop
The low difficulty for forming the control grid.
Further, the electric charge barrier layer of channel pore structure can also be formed in the groove, so that described
Electric charge barrier layer prevents take up channel hole space, improves the space for forming channel pore structure other materials layer, and reduction forms the ditch
The difficulty of road pore structure.
In the forming process of three-dimensional storage, the stacked structure includes nucleus and around the nucleus
Stepped area, above-mentioned Fig. 1 to Fig. 8 illustrate only structure at the nucleus of the stacked structure.
The structure for please referring to the forming process for the three-dimensional storage that Fig. 9 to Figure 11 is another specific embodiment of the present invention is shown
It is intended to.
Referring to FIG. 9, for the structural schematic diagram at the stepped area of the stacked structure.The stepped area exposes often
The end of one layer of sacrificial layer 212；100 surface of substrate is also formed with the dielectric layer 900 for covering the stepped area.
Referring to FIG. 10, removing the sacrificial layer 112 and being formed after control grid 800, is formed and run through the dielectric layer
900 to control 800 end surface of grid contact hole 901.
In the specific embodiment, controlled grid 800 includes the diffusion resistance of grid 802 and the covering grid 802
Barrier 801.Since 800 surface of control grid is just coated with the dielectric layer 900, the contact hole 901 is formed
In the process, it is only necessary to the dielectric layer 900 is etched, thus, it is only required to select to have the dielectric layer 900 with control grid 800
There is the etching technics compared with high selectivity ratio, the difficulty for etching the contact hole 901 can be reduced.
Figure 11 is please referred to, forms contact portion 902 in the contact hole 901.
Metal material is filled in the contact hole 901, forms contact portion 902, and the contact portion 902 is hindered with the diffusion
Barrier 801 and grid 802 form electrical connection.
In a specific embodiment of the invention, a kind of three-dimensional storage is also provided.
Referring to FIG. 8, the structural schematic diagram of the three-dimensional storage for the embodiment of the invention.
The three-dimensional storage, including：Storage stack structure, the storage stack structure include the control gate being alternately stacked
Pole 800 and insulating layer 111；Channel pore structure runs through the storage stack structure；Gate dielectric layer is located at the channel pore structure
Between side wall and the control grid 800, control 800 end of the grid side opposite with the channel pore structure is at least covered
Wall surface.
The partial schematic diagram of the storage stack structure of three-dimensional storage is illustrated only in Fig. 8.Actual three-dimensional storage packet
The control grid 800 and insulating layer 111 that multilayer is alternately stacked are included, such as can be 28 layers, 64 layers or 128 layers etc., the storage
Stacked structure is formed in a substrate surface.In Fig. 8, the substrate is not shown.
The control grid 800 includes：Grid 802 and it is located at the grid 802 and insulating layer 111, gate dielectric layer
Diffusion barrier layer 801 between 401.
The material of the diffusion barrier layer 801 is at least one of TiN, TaN, Ti or TiW, can stop the grid
802 material is to external diffusion.The material of the grid 802 is at least one of polysilicon, aluminium, copper or tungsten.
The insulating layer 111 can be silicon oxide layer or silicon nitride layer as the separation layer between adjacent control gates pole 800
Equal insulating dielectric materials layer.
The material of the gate dielectric layer 401 includes the insulating materials such as silica, silicon oxynitride；Preferably, the gate medium
The material of layer 401 can be at least one of high-k dielectric materials such as hafnium oxide, aluminium oxide, zirconium oxide and lanthana.
The channel pore structure is formed in channel hole, including：Electric charge barrier layer 601, electric charge capture layer 602, tunnel layer
603, channel layer 604 and the channel dielectric layer 605 in the full channel hole of filling.
The gate dielectric layer 401 is located between the end face and channel pore structure of the control grid 800, as storage unit
Gate dielectric layer.Due to not formed gate dielectric layer between the diffusion barrier layer 801 and insulating layer 111, it is thus possible to improve phase
The space that control grid is formed between adjacent insulating layer 111, also improves the integrated level of memory.
In the specific embodiment, the transverse width of the control grid 800 is less than the transverse width of insulating layer 111, makes
Obtaining has groove between adjacent insulating layer 111, the bottom portion of groove is control grid 800 towards the end face of channel pore structure, i.e.,
The diffusion barrier layer 801 is towards the surface of channel pore structure；The gate dielectric layer 401 covers the inner wall surface of the groove.
In the specific embodiment, the interior surface that the gate dielectric layer 401 not only covers groove also covers the side of the insulating layer 111
Wall surface.In other specific embodiments, the gate dielectric layer 401 only covers the inner wall surface of the groove, can be into one
Step improves the space for forming channel pore structure.
In the specific embodiment, the electric charge barrier layer 601 of the channel pore structure is located in the groove.Due to described
For electric charge barrier layer 601 in the groove between insulating layer 111, the inner space for preventing take up the channel hole 103 therefore can
Deposition step and etch step when forming above-mentioned electric charge capture layer 602, tunnel layer 603 and channel layer 604 to reduce
Difficulty is conducive to the performance for improving the channel pore structure formed.In other specific embodiments, the electric charge barrier layer 601
The side wall in channel hole can also be covered.
In the specific embodiment, the electric charge capture layer 602 covers channel hole side wall and electric charge barrier layer
601, the tunnel layer 603 covers the electric charge capture layer 602, and the channel layer 604 covers the tunnel layer 603；The electricity
Lotus barrier layer 601, electric charge capture layer 602, tunnel layer 603, channel layer 604 cover channel hole side wall, expose channel bottom hole
The substrate surface in portion；The channel dielectric layer 605 is located at 604 surface of channel layer and fills the full channel hole.
Figure 11 is please referred to, for the structural schematic diagram of the three-dimensional storage of another specific embodiment of the present invention.
In the specific embodiment, the stacked structure of the three-dimensional storage includes nucleus and around the core space
The stepped area in domain.The structural schematic diagram of the stepped area of the three-dimensional storage is shown in above-mentioned Figure 11.
The storage stack structure is formed in 100 surface of substrate, and the stepped area exposes each layer of control grid 800
End；The storage stack body structure surface has the dielectric layer 900 for covering the stepped area, and the dielectric layer 900 is located at
The end surface of the control grid 800.
900 have the contact portion through the dielectric layer 900 to each control 800 end surface of grid in the dielectric layer
902.In the specific embodiment, the contact portion 902 through the dielectric layer 900 to 801 surface of diffusion barrier layer, and it is described
It controls grid 800 and forms electrical connection.During forming the contact portion 902, needs to etch the formation of dielectric layer 900 and run through
To the contact hole of dielectric layer 900, then the filling conductive material formation contact portion 902 in contact hole.Due to the control grid 800
Surface is just coated with the dielectric layer 900, therefore when forming contact hole, it is only necessary to etch the dielectric layer 900, can reduce
The difficulty of the contact hole is formed, to improve finally formed contact portion 902 and control the electrical connectivity between grid 800
Energy.
Figure 12 is please referred to, in another embodiment of the present invention, is simply formed in the groove between insulating layer 111
Electric charge barrier layer 601.Gate dielectric layer 401 ' is located between control grid 800 and the insulating layer 111, electric charge barrier layer 601.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (10)
1. a kind of three-dimensional storage, which is characterized in that including：
Storage stack structure, the storage stack structure include the control grid and insulating layer being alternately stacked；
Channel pore structure runs through the storage stack structure；
The width of the control grid is less than the width of insulating layer, so that having groove, the part ditch between adjacent insulating layer
Road pore structure is located in the groove.
2. three-dimensional storage according to claim 1, which is characterized in that further include：Gate dielectric layer is located at the control gate
Between extreme portion and the channel pore structure, the end of the control grid side opposite with the channel pore structure is at least covered
Wall surface.
3. three-dimensional storage according to claim 2, which is characterized in that the bottom portion of groove is the end face for controlling grid；
The gate dielectric layer at least covers the bottom surface of the groove.
4. three-dimensional storage according to claim 3, which is characterized in that the gate dielectric layer is also covered to be tied around channel hole
The sidewall surfaces of the insulating layer of structure.
5. three-dimensional storage according to claim 1, which is characterized in that the channel pore structure is formed in channel hole,
Including：The electric charge barrier layer being at least partially disposed in the groove；Cover channel hole side wall and charge barrier layer surface
Electric charge capture layer, the tunnel layer of the covering electric charge capture layer and the channel layer of the covering tunnel layer；Positioned at the ditch
Road layer surface and the channel dielectric layer for filling the full channel hole.
6. three-dimensional storage according to claim 1, which is characterized in that the control grid includes grid and is located at
Diffusion barrier layer between the grid and insulating layer, grid and gate dielectric layer.
7. three-dimensional storage according to claim 1, which is characterized in that the storage stack structure include nucleus and
Around the stepped area of the nucleus, the stepped area exposes the end of each layer of control grid；The stepped region
Dielectric layer is covered on domain.
8. three-dimensional storage according to claim 7, which is characterized in that further include being controlled through the dielectric layer to each layer
The contact portion of grid end surface.
9. three-dimensional storage according to claim 7, which is characterized in that further include the battle array through the storage stack structure
Column common source.
10. three-dimensional storage according to claim 1, which is characterized in that the three-dimensional storage is 3D NAND storage
Device.
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