CN108899057B - Read DQS signal gate gating training method and device and data transmission system - Google Patents

Read DQS signal gate gating training method and device and data transmission system Download PDF

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CN108899057B
CN108899057B CN201810602252.XA CN201810602252A CN108899057B CN 108899057 B CN108899057 B CN 108899057B CN 201810602252 A CN201810602252 A CN 201810602252A CN 108899057 B CN108899057 B CN 108899057B
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dqs signal
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read dqs
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CN108899057A (en
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谢治中
吴卿乐
梁岩
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Omnivision Technologies Shanghai Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

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Abstract

The invention provides a read DQS signal gate gating training method, a device and a data transmission system, which are characterized in that a gate gating enabling signal with the width being BL/2-1 clock cycle width of read DQS signals is generated based on a read request, and then the gate gating enabling signal is controlled to move from left to right until the falling edge of the gate gating enabling signal just exceeds the 2 nd from last rising edge of the read DQS signals, so that the moved gate gating enabling signal is obtained; then delaying the moved gate gating enabling signal to obtain a delayed gate gating enabling signal; and then the rising edge of the delayed gate gating enable signal is used as the starting position of a gate gating window, and the position of the last falling edge of the read DQS signal is used as the ending position of the gate gating window to obtain the final gate gating window of the read DQS signal, so that the time sequence allowance of the gate gating training result of the read DQS signal can be greatly improved, and the working stability of the system is enhanced.

Description

Read DQS signal gate gating training method and device and data transmission system
Technical Field
The invention relates to the technical field of data access, in particular to a gate gating training method and device for a read DQS signal and a data transmission system.
Background
A DDR (Double Data Rate) system is a habitual abbreviation of a DDR SDRAM (Double Data Synchronous random Access Memory) system, and has the advantages of large storage capacity, low cost, mature interface, and high Access Rate during parallel burst Access.
Referring to fig. 1, in general, a DDR system mainly includes a controller DDRC, a physical layer DDR PHY, and a memory granule DRAM, and buses therebetween. The signals transmitted on the bus include, among other things, a clock signal CLK, a command signal CMD, an address signal ADDR, a data signal DQ, and a read strobe signal DQs (also referred to as a data sample signal, a data strobe signal, or a read DQs signal). Where the clock signal CLK, command signal CMD, and address signal ADDR are unidirectional signals from the DDR PHY to the DRAM, and the data signal DQ and read DQs signals are bidirectional signals.
The DDR system may transmit data in a Burst mode (Burst mode), specifically, when there is no data read/write operation, DQ and DQs are in a High impedance (High Z) state; in the read operation, referring to fig. 2, the DRAM first presets the DQS signal (i.e., read DQS signal) at a low level with a period width, which is called Preamble (indicated in the ideal DQS waveform in fig. 2), and is mainly used to prompt the controller DDRC to read data that is about to appear, and then the DRAM sends the read DQS signal (as shown in the real DQS waveform in fig. 2) to the receiving end of the DDR PHY (i.e., the front end receiver inside the DDR PHY for converting the bus signal into an internal digital logic signal) in a clock manner until a burst (burst signal) is ended, in which process the data signal DQ (as shown in the DQ waveform in fig. 2) is sent by the DRAM in alignment with the edge of the read DQS signal. When the read DQS signal sent by the DRAM changes from High impedance (High Z) to logic low level (0, logic low) or from low level (0) to High impedance (High Z), due to non-ideal factors such as parasitic inductance and capacitance, the signal may generate oscillations (glitch, as marked by the dashed circles at the beginning and end of the true DQS waveform in fig. 2), which may be converted into digital logic "1" by the DDR PHY front end receiver, resulting in glitches (glitches) being generated in the read DQS signal output by the DDR PHY front end receiver at positions of preamble and postamble (as marked by the dashed circles at the beginning and end of the read DQS signal output by the DDR PHY front end receiver in fig. 2), and the read DQS signal with glitches may cause erroneous data reception (i.e., DDR PHY read data errors). Therefore, it is necessary to perform Gate gating training on the read DQS signal output by the front-end receiver of the DDR PHY, and a proper read DQS signal Gate gating Window (DQS Gate Enable Window, as shown in fig. 2) can be found through a search algorithm, so as to filter the glitches of the read DQS signal at the beginning and end, obtain a clean read DQS signal, and then sample the data DQ with the clean read DQS signal, so as to obtain correct read data. The read DQS signal output by the DDR PHY front-end receiver is subjected to strobe search through a search algorithm (the read DQS waveform on the bus is not directly searched), so that the DDR PHY can correctly receive data sent by the DRAM.
Referring to fig. 3, a conventional gate strobe training method for reading a DQS signal includes the following steps:
first, a training controller will generate a gate strobe window (not shown) with a width of BL/2(BL: burst length, which refers to the length of one data read/write, and the burst length of the legend is equal to 8) clock cycles, which is left relative to the read DQS signal;
then, the gate strobe window is controlled to move right step by step (i.e., the gate strobe window is delayed step by step from left to right) until a left boundary is found (as shown by the read DQS signal gate strobe window left boundary in FIG. 3);
then, the gate strobe window is controlled to continue to move right step by step (i.e., the gate strobe window is delayed step by step from left to right) until the right boundary of the gate strobe window is found (as shown by the read DQS signal gate strobe window right boundary in fig. 3);
finally, an average position is calculated from the results of the left and right boundaries to obtain the position of the last gate strobe window (as shown by the position of the last read DQS signal gate strobe window in fig. 3).
In the method, the gate strobe window is 0.25 × T (T is one clock cycle of the read DQS signal) from the valid (i.e., correct) timing margin of the read DQS signal at the Preamble (Preamble) position and the Postamble (Postamble) position where the read DQS signal starts. When the operating speed of the DDR system is further increased, the timing margin of 0.25 × T is not sufficient in consideration of non-ideal factors such as voltage noise, ambient temperature variation, and signal reflection, so a new method is needed to increase the timing margin of the determined gate strobe window for reading the DQS signal, so as to lay a better foundation for stable operation of the DDR system.
Disclosure of Invention
The invention aims to provide a method, a device and a system for training gate selection of a read DQS signal gate, which can improve the time sequence allowance of the training result of the gate selection of the read DQS signal gate and enhance the working stability of the system.
In order to achieve the above object, the present invention provides a gate strobe training method for reading a DQS signal, comprising the following steps:
generating a gate gating enabling signal with the width of (BL/2-1) clock cycle width of reading DQS signals according to a reading request, wherein BL is burst length;
controlling the gate gating enabling signal to move from left to right relative to the read DQS signal until the falling edge of the gate gating enabling signal just exceeds the 2 nd last rising edge of the read DQS signal to obtain a moved gate gating enabling signal;
delaying the shifted gate strobe enable signal to obtain a delayed gate strobe enable signal, wherein a timing margin between a rising edge of the delayed gate strobe enable signal and a first rising edge of the read DQS signal is not less than 0.25T, and T is a read DQS signal clock period;
and taking the position of the rising edge of the delayed gate gating enable signal as the starting position of a gate gating window, and taking the position of the last falling edge of the read DQS signal as the ending position of the gate gating window to obtain the final gate gating window of the read DQS signal.
Optionally, after obtaining the shifted gate strobe enable signal and before obtaining the delayed gate strobe enable signal, the method for gate strobe training of the read DQS signal further includes: and taking the rising edge of the moved gate gating enable signal as the starting position of an initial gate gating window, and taking the position of the last falling edge of the read DQS signal as the ending position of the initial gate gating window to obtain the initial gate gating window.
Optionally, the position of the last falling edge of the read DQS signal is determined by automatically detecting the last rising and falling edge of the read DQS signal before or after delaying the shifted gate strobe enable signal.
Optionally, the falling edge of the delayed gate strobe enable signal does not lag the last rising edge of the read DQS signal or lead the second to last rising edge of the read DQS signal.
Optionally, the shifted gate enable signal is delayed by 0.5 × T to obtain a maximum timing margin.
The invention also provides a gate gating training device for reading the DQS signal, which comprises:
the training controller is used for generating a gate gating enabling signal with the width of (BL/2-1) clock cycle width of a reading DQS signal according to a reading request, controlling the gate gating enabling signal to move from left to right relative to the reading DQS signal until the falling edge of the gate gating enabling signal just exceeds the 2 nd last rising edge of the reading DQS signal to obtain a moved gate gating enabling signal, and delaying the moved gate gating enabling signal to obtain a delayed gate gating enabling signal, wherein the time sequence margin between the rising edge of the delayed gate gating enabling signal and the first rising edge of the reading DQS signal is not less than 0.25T, and T is a reading DQS signal clock cycle;
and the self-closing logic circuit is used for detecting the last rising edge and the last falling edge of the read DQS signal to obtain the position of the last falling edge of the read DQS signal, further taking the delayed rising edge of the gate strobe enable signal as the starting position of a gate strobe window, and taking the position of the last falling edge of the read DQS signal as the ending position of the gate strobe window to obtain the final gate strobe window of the read DQS signal.
Optionally, the falling edge of the delayed gate strobe enable signal does not lag the last rising edge of the read DQS signal or lead the second to last rising edge of the read DQS signal.
Optionally, the training controller delays the shifted gate strobe enable signal by 0.5 × T to obtain a delayed gate strobe enable signal, and a timing margin between a rising edge of the delayed gate strobe enable signal and a first rising edge of the read DQS signal is 0.5 × T to obtain a maximum timing margin.
Optionally, the self-shutdown logic circuit includes a delay unit, first to third flip-flops, first to third inverters, and first to second nor gates, where the first flip-flop and the second flip-flop are connected in series, an input terminal of the first flip-flop, an input terminal of the third flip-flop, and a clock terminal of the first flip-flop receive a same logic high level signal, a clock terminal of the first flip-flop and an input terminal of the first inverter receive the read DQS signal, an output terminal of the first inverter is connected to a clock terminal of the second flip-flop, clear terminals of the first flip-flop and the second flip-flop are both connected to an output terminal of the delay unit, an input terminal of the delay unit is connected to an output terminal of the first nor gate, an output terminal of the second flip-flop is connected to an input terminal of the second nor gate, and an output terminal of the second nor gate is connected to a set terminal of the third flip-flop, the zero clearing end of the third trigger is connected with the output end of the second phase inverter, the input end of the second phase inverter receives the delayed gate gating enabling signal, the output end of the third trigger is connected with the input end of the third phase inverter and the input end of the first NOR gate, and the output end of the third phase inverter outputs the final gate gating window of the read DQS signal.
Optionally, the first to third flip-flops are all D-type flip-flops; the first nor gate comprises three input ends and an output end, and the two input ends of the first nor gate respectively receive a reset signal and the delayed gate gating enable signal; the second nor gate is a nor gate with two input ends and one output end, and the other input end of the second nor gate receives the reset signal.
Optionally, the read DQS signal gate strobe training apparatus is applied to a DDR interface circuit, the training controller is a part of a controller in the DDR interface circuit, and the self-shutdown logic circuit is disposed on a physical layer in the DDR interface circuit.
The invention also provides a data transmission system which is characterized by comprising the DQS signal reading gate gating training device and memory particles used for sending the DQS signal reading gate gating training device.
Optionally, the data transmission system is a DDR system, the DQS signal gate strobe training device is applied to a DDR interface circuit, the training controller is a part of a controller in the DDR interface circuit, the self-shutdown logic circuit is disposed on a physical layer in the DDR interface circuit, and the memory granules are connected to the physical layer through a system bus.
Compared with the prior art, the technical scheme of the invention includes that a gate gating enabling signal with the width of (BL/2-1) clock cycle width of reading DQS signals is generated based on a reading request, and then the gate gating enabling signal is controlled to move from left to right relative to the reading DQS signals until the falling edge of the gate gating enabling signal just exceeds the 2 nd-from-last rising edge of the reading DQS signals, so that the moved gate gating enabling signal is obtained; then delaying the shifted gate strobe enable signal to obtain a delayed gate strobe enable signal, wherein the interval between the rising edge of the delayed gate strobe enable signal and the first rising edge of the read DQS signal is not less than 0.25T, and T is a read DQS signal clock period; and then taking the rising edge of the delayed gate strobe enable signal as the starting position of a gate strobe window, and taking the position of the last falling edge of the read DQS signal as the ending position of the gate strobe window to obtain the final gate strobe window of the read DQS signal, wherein the final gate strobe window of the read DQS signal has a margin larger than 0.25 clock cycle at the Preamble position at the beginning of the read DQS signal, and has a margin larger than 0.25 clock cycle at the ending position of the read DQS signal, therefore, compared with the traditional method, the timing sequence margin of the gate strobe training result of the read DQS signal is improved, and a better basis is laid for the stable work of the system.
Drawings
FIG. 1 is a block diagram of a DDR system;
FIG. 2 is a timing diagram for a read operation in the DDR system of FIG. 1;
FIG. 3 is a signal waveform diagram of a read DQS signal gate strobe training method;
FIG. 4 is a flow diagram of a read DQS signal gate strobe training method in accordance with an embodiment of the present invention;
FIG. 5 is a signal waveform diagram of a read DQS signal gate strobe training method in accordance with an embodiment of the present invention;
FIG. 6 is a block diagram of a read DQS signal gate strobe training apparatus in accordance with an embodiment of the present invention;
FIG. 7 is a schematic diagram of a self-shutdown logic circuit in accordance with an embodiment of the present invention;
FIG. 8 is a control timing diagram of the self-shutdown logic circuit in accordance with an embodiment of the present invention.
Detailed Description
The present invention will be described in more detail with reference to the accompanying drawings, which are included to illustrate embodiments of the present invention.
Referring to fig. 4, the present invention provides a gate strobe training method for reading DQS signal, including the following steps:
s1, generating a gate strobe enable signal with a width of (BL/2-1) clock cycle width of the read DQS signal according to a read request, wherein BL is burst length;
s2, controlling the gate strobe enabling signal to move from left to right relative to the read DQS signal until the falling edge of the gate strobe enabling signal just exceeds the 2 nd last rising edge of the read DQS signal, and obtaining the moved gate strobe enabling signal;
s3, delaying the shifted gate strobe enable signal to obtain a delayed gate strobe enable signal, wherein a timing margin between a rising edge of the delayed gate strobe enable signal and a first rising edge of the read DQS signal is not less than 0.25 × T, T being a read DQS signal clock period;
and S4, taking the position of the rising edge of the delayed gate gating enable signal as the starting position of a gate gating window, and taking the position of the last falling edge of the read DQS signal as the ending position of the gate gating window to obtain the final gate gating window of the read DQS signal.
Referring to fig. 1, 5 and 6, when data in the DRAM needs to be read, a read request is usually initiated first, further, the DRAM receives the information including the command CMD and the address ADDR corresponding to the read request, and the DRAM synchronously transmits the data signal DQ and the read DQs signal to the front-end receiver of the DDR PHY according to the information (ideally, the signal is as shown by an ideal DQs in fig. 5, but in a real case, when the read DQs signal transitions from a High level to a low level and from the low level to the High level, the signal is affected by parasitic inductance capacitance and the like on a transmission channel to generate glitches, as shown by a real DQs in fig. 5), at this time, the read DQs signal output by the front-end receiver of the DDR PHY also has glitches, and data read errors are easily generated, therefore, in order to avoid read data errors, the read DQS signal output by the front-end receiver of the DDR PHY needs to be gate-gated. Specifically, in step S1, the training controller 11 generates a Gate strobe Enable Signal (dqgate Enable Signal, not shown) with a width of (BL/2-1) read DQS Signal clock cycle width according to the read request, where BL is a burst length, which refers to a length of one data read/write, the burst length in fig. 5 is equal to 8, and the read DQS Signal is a read DQS Signal output by the DDR PHY front-end receiver, so that the generated Gate strobe Enable Signal has a width of 3 read DQS Signal clock cycles, which is also substantially a Gate strobe window; then, in step S2, first, the training controller 11 controls the gate strobe enable signal to move from left to right, and during the moving process, the search algorithm in the training controller 11 will determine whether the position of the current gate strobe enable signal is correct according to whether the received data signal (DQ) is correct (generally, by comparing whether the written/read data is consistent), until the falling edge of the moved gate strobe enable signal just exceeds the second last rising edge of the read DQs signal, so as to obtain the correct moved gate strobe enable signal, as shown in position 1 of fig. 5; after each shift of the gate strobe enable signal, taking the rising edge of the shifted gate strobe enable signal as the starting position of the current initial gate strobe window, and starting to detect the last rising edge and falling edge of the read DQS signal through a Self-closing logic circuit 12, when the last falling edge (as the ending position of the current initial gate strobe window) is detected, closing the current initial gate strobe window from the closing logic circuit 12 to obtain the current initial gate strobe window, as shown in position 2 of fig. 5, which is used for detecting whether the position of the gate strobe enable signal after the current shift is correct, specifically, gating the read DQS signal based on the current initial gate strobe window, so that the corresponding data signal DQ (data D0-D7 are received when the position of the gate strobe enable signal after the shift is correct), the search algorithm in the training controller 11 determines whether the position of the gate strobe enable signal (i.e., position 1) after the current movement is correct according to whether the received data is correct, and when the position is incorrect, the gate strobe enable signal continues to be controlled to move until the falling edge of the gate strobe enable signal just exceeds the penultimate rising edge of the read DQS signal, and at this time, the position of the gate strobe enable signal after the correct movement is found (i.e., position 1 in fig. 5); then, in step S3, training controller 11 delays the gate strobe enable signal by half the clock cycle (i.e., 0.5 × T) of the read DQS signal to position 3 in fig. 5 based on the shifted gate strobe enable signal (i.e., position 1 in fig. 5) in step S2, i.e., obtains the delayed gate strobe enable signal; next, in step S4, the last rising and falling edge of the read DQS signal is again detected by beginning to detect from shutdown logic 12, when the last falling edge is detected, self-close logic 12 closes the gate strobe window, resulting in a final gate strobe window (i.e., the final gate strobe training result) as shown at position 4 of FIG. 5, whose starting position (i.e., starting time) is the starting position (i.e., starting time) of the delayed gate strobe enable signal shown at position 3 of FIG. 5, or the rising edge position of the final gate strobe window is the rising edge position of the delayed gate strobe enable signal), whose ending position (i.e., ending time) is controlled by self-close logic 12, always closing at the last falling edge of the read DQS signal, i.e., the position of the falling edge of the final gate strobe window, i.e., the position of the last falling edge of the read DQS signal.
Therefore, the training method for gate strobe of read DQS signal of this embodiment can make the final gate strobe window of read DQS signal have a timing margin of 0.5 × T at the position of Preamble (Preamble) where it starts, which is 2 times of the training method shown in fig. 3; meanwhile, at the place where the read DQS signal ends, because of the self-shutdown control, the condition for determining the timing margin is changed to that as long as the falling edge of the delayed gate strobe enable signal shown in position 3 in fig. 5 does not lag behind the last rising edge of the read DQS signal or lead ahead of the second last rising edge of the read DQS signal, the self-shutdown logic circuit can work correctly, and in particular, as mentioned above, when the delayed gate strobe enable signal is 0.5T, the falling edge of the delayed gate strobe enable signal is in the middle position of the last rising edge and the second last rising edge of the read DQS signal, the timing margin of 0.5T at maximum can be obtained, which is 2 times of the training method shown in fig. 3. From the above analysis, the method of the present invention can greatly improve the timing sequence margin of the gate gating training result of the read DQS signal, and lay a better foundation for the stable work of the DDR system.
It should be noted that, in the above embodiment, the shifted gate strobe enable signal (i.e. position 1 in fig. 5) is delayed by 0.5 × T, and a timing margin of 0.5 × T can be obtained at both the beginning and the end of the last gate strobe window, which is the most preferable embodiment of the technical solution of the present invention, but in other embodiments of the present invention, if the requirement for the timing margin is not too high, for example, the timing margin at the beginning and the end of the last gate strobe window can be allowed to be unequal, then in step S3, as long as the time for delaying the shifted gate strobe enable signal can make the timing margin between the rising edge of the delayed gate strobe enable signal and the first rising edge of the read DQS signal greater than 0.25 × T, and the falling edge of the delayed gate strobe enable signal does not lag behind the last rising edge of the read DQS signal or lead the second rising edge of the read DQS signal, the requirements may be met, such as delaying by 0.25 or 0.6 read DQS signal clock cycles. In addition, in other embodiments of the present invention, the method for determining whether position 1 in fig. 5 is correct is not limited to determining by using the initial gate strobe window of the present invention (i.e., the gate strobe window whose start position is the rising edge of the shifted gate strobe enable signal and end position is the last falling edge of the read DQS signal), but may also use the shifted gate strobe enable signal as the current gate strobe window directly, and the search algorithm in the training controller 11 may determine whether the position of the current shifted gate strobe enable signal is correct according to whether the received data signal (DQ) is correct (e.g., by comparing whether the received data is consistent with the front fraction data D0-D3 in the write data) (i.e., determining whether the falling edge of the current shifted gate strobe enable signal just exceeds the second last rising edge of the read DQS signal), it can be seen that the step of obtaining the initial gate strobe window in the above embodiment may also be omitted, that is, only the gate strobe enable signal after the delay shift is completed is the last rising edge and falling edge of the read DQS signal detected.
Referring to fig. 6, the present invention further provides a gate strobe training apparatus for reading DQS signals, which includes a training controller 11 and a self-shutdown logic circuit 12, wherein the training controller 11 and the self-shutdown logic circuit 12 both receive the reading DQS signals, and an output terminal of the training controller 11 is connected to an input terminal of the self-shutdown logic circuit 12.
The training controller 11 is configured to generate a gate strobe enable signal having a width of (BL/2-1) a clock cycle width of a read DQS signal according to a read request (i.e., a read request corresponding to the read DQS signal), and control the gate strobe enable signal to move from left to right relative to the read DQS signal until a falling edge of the gate strobe enable signal just exceeds a 2 nd from a last rising edge of the read DQS signal, so as to obtain a moved gate strobe enable signal, and delay the moved gate strobe enable signal, so as to obtain a delayed gate strobe enable signal, where a timing margin between the rising edge of the delayed gate strobe enable signal and a first rising edge of the read DQS signal is not less than 0.25T, where T is a read DQS signal clock cycle, and a falling edge of the delayed gate strobe enable signal does not lag behind a last rising edge of the read DQS signal or lead a second last rising edge of the read DQS signal For example, training controller 11 delays the shifted gate strobe enable signal by 0.5 read DQS signal clock cycles (i.e., 0.5 × T). The training controller 11 is further configured to send the delayed gate enable signal to the self-shutdown logic circuit 12.
The self-turn-off logic circuit 12 is configured to detect a last rising edge and a last falling edge of the read DQS signal to obtain a position of the last falling edge of the read DQS signal, further use the delayed gate strobe enable signal as a start position of a gate strobe window, and use a position of the last falling edge of the read DQS signal as an end position of the gate strobe window to obtain a final gate strobe window of the read DQS signal. In this embodiment, referring to fig. 7, the self-shutdown logic circuit 12 includes a delay unit 120, first to third flip-flops DFF0 to DFF2, first to third inverters U1 to U3, and first to second logic gates G1 to G2, wherein the first to third flip-flops DFF0 to DFF2 are all D-type flip-flops, the first logic gate is a NOR gate (NOR) having three input terminals and one output terminal, and the second logic gate is a NOR gate (NOR) having two input terminals and one output terminal; the first flip-flop DFF0 and the second flip-flop DFF1 are connected in series (i.e. the output terminal of the first flip-flop DFF0 is connected to the input terminal D of the second flip-flop DFF 1), the input terminal (D) of the first flip-flop DFF0, the input terminal (D) of the third flip-flop DFF2 and the clock terminal (CP) receive a same logic high level signal tie _ hi (i.e. the level is "1"), the clock terminal (CP) of the first flip-flop DFF0 and the input terminal of the first inverter U1 receive the read DQS signal corresponding to the read request (substantially, the read DQS signal after the output of the DDR front-end receiver, and at the time, the read DQS signal has been converted into a digital logic level inside the circuit by a bus level, if no special assertion is made, the gate training on the read DQS signal in this embodiment refers to gate on the read DQS signal after the output of the DDR front-end PHY), the output terminal of the first inverter U1 is connected to the clock terminal (CP) of the second flip-flop DFF1, the clear terminals (CDN) of the first flip-flop DFF0 and the second flip-flop DFF1 are both connected to the output terminal of the delay unit 120, the input terminal of the delay unit 120 is connected to the output terminal of the first logic gate G1, the output terminal (Q) of the second flip-flop DFF1 is connected to one input terminal of a second logic gate G2, the other input terminal of the second logic gate receives the reset signal rst, the output terminal of the second logic gate G2 is connected to the reset terminal (SDN) of the third flip-flop DFF2, the clear terminal (CDN) of the third flip-flop DFF2 is connected to the output terminal of the second inverter U2, the input terminal of the second inverter U2 receives the delayed gate enable signal dqsg en _ i transmitted by the training controller 11, and the output terminal (Q) of the third flip-flop DFF2 is connected to the input terminal of a third inverter U3 and one input terminal of the first logic gate G1, the other two input terminals of the first logic gate G1 receive the delayed gate strobe enable signal dqsg _ en _ i and the reset signal rst, respectively, and the output terminal of the third inverter U3 outputs the final gate strobe window dqsg _ en _ o of the read DQS signal. The second logic gate G2 is used to provide a set 1 signal dqs _ sdn to the third flip-flop DFF2, the delay unit 120 is used to provide a clear signal cdn to the first flip-flop DFF0 and the second flip-flop DFF1, the third flip-flop DFF2 is used to provide an input signal dqs _ falling to the first logic gate G1 and the third inverter U3, the first logic gate G1 is used to provide a delay unit 120, and the second inverter U2 is used to provide a clear signal dqs _ cdn to the third flip-flop DFF 2. The first and second flip-flops DFF0 and DFF1 are used to detect the last rising edge and the last falling edge of the read DQS signal, the third flip-flop DFF2 has a clear 0 control and a set 1 control, the output (Q) of the third flip-flop DFF2 is low 0 when the clear signal DQS _ cdn is 0, and the output (Q) of the third flip-flop DFF2 is high 1 when the set 1 signal DQS _ sdn is 0. Fig. 8 is a control timing diagram of the self-shutdown logic circuit 12 shown in fig. 7, and it can be seen how the self-shutdown logic circuit detects the last rising edge and falling edge of the read DQS signal and closes the gate strobe window, where dqsg _ en _ i is the delayed gate strobe enable signal (delayed by 0.5 × T clock cycles) sent by the training controller 11, the output signal dqsg _ en _ o is the final gate strobe window of the read DQS signal, specifically, when dqsg _ en _ i changes from low to high (i.e. at the rising edge position), the clear signal DQS _ cdn changes from 1 to 0 (i.e. at the rising edge position), the output signal DQS _ falling of the third flip-flop DFF2 changes to 0, at this time, the output signal of the third inverter U3 changes to 1, which is the start time of the gate window (i.e. the rising edge of the gate strobe window dqsg _ en _ o), in the time width of maintaining high level of dqsg _ en _ i, the clear signal dqs _ cdn is maintained at zero, the reset signal rst is maintained at zero, the generated cdn signal is maintained at zero, and the output signal dqs _ falling of the third flip-flop DDF2 is maintained at zero; when dqsg _ en _ i changes from 1 to 0 (i.e. falling edge position), the clear signal DQS _ cdn changes to 1, because both DQS _ falling and rst signals are still 0, the signal output by the first logic gate G1 changes from 0 to 1, i.e. cdn changes to 1, the first flip-flop DFF0 and the second flip-flop DFF1 detect the last rising edge and falling edge of the read DQS signal and output a 1 signal by the second flip-flop DFF1, the 1 set signal DQS _ sdn output by the second logic gate G2 at this time changes to 0, which results in the output signal DQS _ falling of the third flip-flop DFF2 changing from 0 to 1, the signal output by the third inverter U3 changes from high level (1) to low level (0), which is the end time of the gate window dqsg _ en _ o, that is the time when the gate window dqsg _ en _ o ends, that the first falling edge of the gate window dqsg _ en _ o changes from 0 to 0, the corresponding delayed gate signal 734, which is delayed by the corresponding 0, so that the outputs of the first and second flip-flops DFF0 and DFF1 are cleared to zero, and the set-1 signal dqs _ sdn becomes 1 again.
The training device for the read DQS signal gate gating of the present invention can achieve automatic training of the read DQS signal gate gating window, and can obtain a gate gating window with a large timing margin (for example, 0.5 × T), can enhance the stability of system operation, and avoid read operation errors caused by non-ideal factors such as voltage noise, environmental temperature variation, and signal reflection.
Therefore, the invention also provides a data transmission system, which comprises the read DQS signal gate gating training device and the memory particles used for sending the read DQS signal to the read DQS signal gate gating training device. Referring to fig. 1 and 6, the data transmission system may be a DDR system, the read DQS signal gate strobe training apparatus is applied to a DDR interface circuit, the training controller 11 is a part of a controller of the DDR interface, the self-shutdown logic circuit 12 is disposed on a physical layer (DDR PHY) in the DDR interface circuit, the memory granule may be a DRAM and may be connected to the physical layer DDR PHY in the DDR interface circuit through a system bus, and the system bus mainly includes a line for transmitting a clock signal CLK, a line for transmitting a command signal CMD and an address signal ADDR, a line for transmitting a data signal DQ, and a line for transmitting a read DQS signal. The data transmission system of the invention adopts the DQS signal reading gate gating training device, so the working stability is improved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (13)

1. A gate strobe training method for reading a DQS signal is characterized by comprising the following steps:
generating a gate gating enable signal with the width of (BL/2-1) clock cycle width of the read DQS signal according to a read request, wherein BL is the burst length;
controlling the gate gating enabling signal to move from left to right relative to the read DQS signal until the falling edge of the gate gating enabling signal just exceeds the 2 nd last rising edge of the read DQS signal to obtain a moved gate gating enabling signal;
delaying the shifted gate strobe enable signal to obtain a delayed gate strobe enable signal, wherein a timing margin between a rising edge of the delayed gate strobe enable signal and a first rising edge of the read DQS signal is not less than 0.25T, and T is a read DQS signal clock period;
and taking the position of the rising edge of the delayed gate gating enable signal as the starting position of a gate gating window, and taking the position of the last falling edge of the read DQS signal as the ending position of the gate gating window to obtain the final gate gating window of the read DQS signal.
2. The method of claim 1 wherein after obtaining the shifted gate strobe enable signal and before obtaining the delayed gate strobe enable signal, the method further comprises: and taking the rising edge of the moved gate gating enable signal as the starting position of an initial gate gating window, and taking the position of the last falling edge of the read DQS signal as the ending position of the initial gate gating window to obtain the initial gate gating window.
3. The read DQS signal gate strobe training method of claim 1 or claim 2 in which the location of the last falling edge of the read DQS signal is determined by automatically detecting the last rising and falling edge of the read DQS signal.
4. The method of claim 1 wherein the delayed gate strobe enable signal does not lag the last rising edge of the read DQS signal or lead the second last rising edge of the read DQS signal.
5. The method of claim 1 wherein the shifted gate strobe enable signal is delayed by 0.5 x T to obtain a maximum timing margin.
6. A training apparatus for gate gating of a read DQS signal, comprising:
the training controller is used for generating a gate gating enabling signal with the width of (BL/2-1) clock cycle width of a reading DQS signal according to a reading request, controlling the gate gating enabling signal to move from left to right relative to the reading DQS signal until the falling edge of the gate gating enabling signal just exceeds the 2 nd last rising edge of the reading DQS signal to obtain a moved gate gating enabling signal, and delaying the moved gate gating enabling signal to obtain a delayed gate gating enabling signal, wherein the time sequence margin between the rising edge of the delayed gate gating enabling signal and the first rising edge of the reading DQS signal is not less than 0.25T, and T is a reading DQS signal clock cycle;
and the self-closing logic circuit is used for detecting the last rising edge and the last falling edge of the read DQS signal to obtain the position of the last falling edge of the read DQS signal, further taking the delayed rising edge of the gate strobe enable signal as the starting position of a gate strobe window, and taking the position of the last falling edge of the read DQS signal as the ending position of the gate strobe window to obtain the final gate strobe window of the read DQS signal.
7. The read DQS signal gate strobe training apparatus of claim 6, wherein a falling edge of the delayed gate strobe enable signal does not lag a last rising edge of the read DQS signal or lead a second last rising edge of the read DQS signal.
8. The read DQS signal gate strobe training apparatus of claim 6, wherein the training controller delays the shifted gate strobe enable signal by 0.5 × T to obtain a delayed gate strobe enable signal, a timing margin between a rising edge of the delayed gate strobe enable signal and a first rising edge of the read DQS signal is 0.5 × T to obtain a maximum timing margin.
9. The apparatus of claim 6, wherein the self-turn-off logic circuit comprises a delay unit, first to third flip-flops, first to third inverters, and first to second NOR gates, wherein the first flip-flop and the second flip-flop are connected in series, an input terminal of the first flip-flop, an input terminal of the third flip-flop, and a clock terminal of the third flip-flop receive a same logic high signal, a clock terminal of the first flip-flop and an input terminal of the first inverter receive the DQS signal, an output terminal of the first inverter is connected to a clock terminal of the second flip-flop, clear terminals of the first flip-flop and the second flip-flop are both connected to an output terminal of the delay unit, an input terminal of the delay unit is connected to an output terminal of the first NOR gate, and an output terminal of the second flip-flop is connected to an input terminal of the second NOR gate, the output end of the second nor gate is connected to the set end of the third flip-flop, the clear end of the third flip-flop is connected to the output end of the second inverter, the input end of the second inverter receives the delayed gate gating enable signal, the output end of the third flip-flop is connected to the input end of the third inverter and the input end of the first nor gate, and the output end of the third inverter outputs the final gate gating window of the read DQS signal.
10. The read DQS signal gate strobe training apparatus of claim 9 wherein the first through third flip-flops are all class D flip-flops; the first nor gate comprises three input ends and an output end, and the two input ends of the first nor gate respectively receive a reset signal and the delayed gate gating enable signal; the second nor gate is a nor gate with two input ends and one output end, and the other input end of the second nor gate receives the reset signal.
11. The training apparatus of claim 6 to 10, wherein the training apparatus is applied in a DDR interface circuit, the training controller is a part of a controller in the DDR interface circuit, and the self-shutdown logic circuit is disposed on a physical layer in the DDR interface circuit.
12. A data transmission system comprising a read DQS signal gate training apparatus as claimed in any one of claims 6 to 11 and a memory granule for sending a read DQS signal to the read DQS signal gate training apparatus.
13. The data transmission system as claimed in claim 12, wherein the data transmission system is a DDR system, the read DQS signal gate training apparatus is applied to a DDR interface circuit, the training controller is a part of a controller in the DDR interface circuit, the self-shutdown logic circuit is disposed on a physical layer in the DDR interface circuit, and the memory granule is connected to the physical layer through a system bus.
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