CN108880533A - Phase alignment and relevant phase-locked loop circuit - Google Patents

Phase alignment and relevant phase-locked loop circuit Download PDF

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Publication number
CN108880533A
CN108880533A CN201710316418.7A CN201710316418A CN108880533A CN 108880533 A CN108880533 A CN 108880533A CN 201710316418 A CN201710316418 A CN 201710316418A CN 108880533 A CN108880533 A CN 108880533A
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phase error
phase
guiding
error
header
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卓庭楠
郑凯文
童泰来
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MediaTek Inc
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MStar Semiconductor Inc Taiwan
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal

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Abstract

A method of processing phase alignment, for a phase-locked loop circuit in a wireless communication apparatus, a guiding phase error comprising a guiding subframe in a header phase error of a header subframe of a frame in one input signal of calculating and the frame, wherein the header subframe and the guiding subframe are given data；According to the relationship between the header phase error and the guiding phase error, a predicted phase error is generated；According to the predicted phase error and a filtering signal, a phase compensation signal is generated；According to the phase compensation signal, the input signal is adjusted, to generate a compensated input signal；It detects in the compensated input signal corresponding to the phase error between the pilot data subframe and a reference signal of the guiding subframe；And according to the phase error, the filtering signal is generated.

Description

Phase alignment and relevant phase-locked loop circuit
Technical field
The present invention refers to a kind of phase alignment and relevant phase-locked loop circuit, and espespecially one kind can be believed according to input Given data calculates the relationship between resulting phase error in number, the phase of the phase error of unknown data in predicted input signal Calibration method and relevant phase-locked loop circuit.
Background technique
Phase-locked loop (Phase Locked-Loop) circuit is to generate a periodic output signal, and this is periodically defeated There is between anticipated signal and a periodic input signal fixed phase relation out.Phase-locked loop circuit is widely used in respectively In the circuit system of formula various kinds, such as data and clock recovery circuitry (the Clock and Data of wireless telecommunication system Recovery), transceiver module (Transceiver) or clock pulse generator (Frequency Synthesizer), and be not limited to This.
Referring to FIG. 1, Fig. 1 be known technology in a phase-locked loop circuit 10 schematic diagram.Phase-locked loop circuit 10 is used to Calibrate the phase error between an input signal IN and a reference signal (not being illustrated in Fig. 1).As shown in Figure 1, phase-locked loop circuit 10 include a multiplier 100, a phase error detection unit 102, a filter 104, an oscillator 106 and a phase error Prediction module 108.The phase for the phase compensation signal PC adjustment input signal IN that multiplier 100 is used to generate according to oscillator 106 Position, to generate compensated input signal CIN to phase error detection unit 102.Phase error detection unit 102 is used to calculate compensation A phase error Φ between input signal CIN and a reference signal and output phase error Φ are to filter 204.Filter 104 According to phase compensation signal PC caused by phase error Φ adjustment oscillator 106.By multiplier 100, phase error detection The circuit that unit 102, filter 104 and oscillator 106 are formed, 10 adjustable compensated input signal CIN of phase-locked loop circuit with Phase error Φ between reference signal.
In Fig. 1, phase error prediction module 108 is used to calculate the phase error of given data in input signal IN, makees For the predicted phase error Φ for being input to oscillator 106ES.Predicted phase error ΦESIt is used as phase-locked loop circuit 10 Initial value in calibration input signal IN when the phase error Φ of unknown data, to increase calibration speed.However, when being used to produce Raw predicted phase error ΦESKnown data length deficiency when, predicted phase error ΦESTrue phase error may be deviateed, Reduce the calibration speed of phase-locked loop circuit 10.Therefore, how in the insufficient situation of known data length, predicted phase is avoided Error ΦESDeviate true phase error, becomes and want the subject under discussion inquired into for industry.
Summary of the invention
In order to solve the problem above-mentioned, the present invention provides one kind can be resulting according to given data calculating in input signal Relationship between phase error, the phase alignment of the phase error of unknown data and relevant and locking phase in predicted input signal Loop circuit.
On the one hand, the invention discloses a kind of methods for handling phase alignment, for a locking phase in a wireless communication apparatus Loop circuit.The method includes to calculate the header phase error and the frame of a header subframe of a frame in an input signal In a guiding subframe a guiding phase error, wherein the header subframe and the guiding subframe are given data；According to the header Relationship between phase error and the guiding phase error generates a predicted phase error；It is filtered according to the predicted phase error and one Wave signal generates a phase compensation signal；According to the phase compensation signal, the input signal is adjusted, to generate a compensation input Signal；It detects in the compensated input signal corresponding to a pilot data subframe of the guiding subframe and the phase between a reference signal Position error；And according to the phase error, the filtering signal is generated.
On the other hand, the invention discloses a kind of phase-locked loop circuits for a wireless telecommunication system.The locking phase is returned Road circuit includes a phase error prediction module, for calculate a frame in an input signal a header subframe a header phase A guiding phase error of a guiding subframe in position error and the frame, wherein the header subframe and the guiding subframe are datum According to；One phase error adjusts module, for it is pre- to generate one according to the relationship between the header phase error and the guiding phase error Survey phase error；One oscillator is used to generate a phase compensation signal according to the predicted phase error and a filtering signal；One Multiplication unit is used to the input signal be adjusted, to generate a compensated input signal according to the phase compensation signal；One phase is missed Poor detection unit is believed for detecting in the compensated input signal corresponding to a pilot data subframe of the guiding subframe and a reference A phase error between number；And a filter, it is used to generate the filtering signal according to the phase error.
Detailed description of the invention
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention Body embodiment elaborates, wherein：
Fig. 1 is known technology the schematic diagram of a phase-locked loop circuit.
Fig. 2 is the schematic diagram of a phase-locked loop circuit in the embodiment of the present invention.
Fig. 3 is the flow chart of one process of the embodiment of the present invention.
Fig. 4 is the schematic diagram of a frame.
Fig. 5 is the schematic diagram that a phase error adjusts module in the embodiment of the present invention.
Fig. 6 is the schematic diagram that another phase error adjusts module in the embodiment of the present invention.
Fig. 7 is that another phase error adjusts module diagram again in the embodiment of the present invention.
Component label instructions are as follows in figure：
10,20 phase-locked loop circuit
100,20 multiplication unit
102,202 phase error detection unit
104,204 filter
106,206 oscillator
108,208 phase error prediction module
210,50,60,70 phase errors adjust module
30 processes
300~318 steps
500,600,700 control unit
502,602,702 arithmetic element
504,706 multiplier
506,606,608,708,710,712,714 selector
604,706 storage element
CIN compensated input signal
CON, CON1, CON2 control signal
DAT_1~DAT_n data burst
FRA frame
HEA header subframe
IN input signal
NF noise indication signal
PC phase compensation signal
PIL_1~PIL_n guides subframe
Φ、ΦML、ΦES_1、ΦES_2Phase error
ΦML HHeader phase error
ΦML PGuide phase error
ΦESPredicted phase error
ΦES PREPrevious prediction phase error
Specific embodiment
Referring to FIG. 2, Fig. 2 is the schematic diagram of a phase-locked loop circuit 20 in the embodiment of the present invention.Phase-locked loop circuit 20 For calibrating the phase error between an input signal IN and a reference signal (not being illustrated in Fig. 2).Phase-locked loop electricity as shown in Figure 2 Road 20 includes a multiplier 200, a phase error detection unit 202, a filter 204, an oscillator 206, phase mistake Poor prediction module 208 and a phase error adjust module 210.Significantly, since multiplier in phase-locked loop circuit 20 200, multiplication in phase error detection unit 202, the function mode of filter 204 and oscillator 206 and phase-locked loop circuit 10 Device 100, phase error detection unit 102, filter 104 and oscillator 106 are identical, for the sake of clarity in this description will be omitted.
It is worth noting that, phase error prediction module 208 can calculate the header phase of given data in input signal IN Error ΦML_HAnd guiding phase error ΦML_P, but header phase error ΦML_HAnd guiding phase error ΦML_PIt can't be direct As the predicted phase error Φ for being input to oscillator 206ES.Header phase error ΦML_HAnd guiding phase error ΦML_PMeeting Phase error adjustment module 210 is first input to be adjusted.Phase error adjusts module 210 then can be according to header phase error ΦML_HAnd guiding phase error ΦML_PBetween relationship, to generate predicted phase error ΦESAs in calibration input signal IN not The initial value of primary data.Predicted phase compared to phase-locked loop circuit 10, after being adjusted through phase error adjustment module 210 Error ΦESIt can be more close to the phase error of unknown data in input signal IN, to promote the calibration of phase-locked loop circuit 20 Speed.
About the Detailed Operation mode of phase-locked loop circuit 20, it is illustrated below.Please collective reference the 3rd, 4 figures, wherein Fig. 3 is the flow chart of a process 30 of phase-locked loop 20, and Fig. 4 is the schematic diagram of a frame FRA in input signal IN.Such as Fig. 4 institute Show, frame FRA includes a header subframe HEA, multiple guiding subframe PIL_1~PIL_n, corresponding to the data of header subframe HEA Subframe DAT_0 and corresponding to guiding subframe PIL_1~PIL_n data burst DAT_1~DAT_n, wherein header subframe HEA, Guiding subframe PIL_1~PIL_n is given data, and the Baud Length of header subframe HEA is greater than guiding subframe PIL_1~PIL_ The Baud Length of n.For example, when wireless communication apparatus operates on second generation digital satellite broadcasting (Digital Video Broadcasting Satellite Second Generation, DVB-S2) when, header subframe includes 90 symbols, and Guiding subframe then includes 36 symbols.
According to process 30, phase-locked loop circuit 20 receive first include frame FRA input signal IN (step 302).By In header subframe HEA, by given data, (i.e. phase error prediction module 208 has learnt the number that header subframe HEA includes in advance According to), therefore phase error prediction module 208 can directly calculate the phase error of header subframe HEA as header phase error ΦML_H, to predict to be connected in the phase error (step 304) of the data burst DAT_0 of header subframe HEA.For example, phase Error prediction module 208 can be used most probably calculates header phase mistake like estimation (Maximum likelihood, ML) method Poor ΦML_H.It is worth noting that, being less susceptible to because the Baud Length of header subframe HEA is longer by noise (such as additivity height This white noise (Additive White Gaussian Noise, AWGN)) it influences, header phase error ΦML_HIt does not deviate by true Real phase error is too far.Therefore, phase error adjustment module 210 can directly export header phase error ΦML_HAs prediction phase Position error ΦES。
Utilize predicted phase error ΦES, the phase error of the beginning of phase-locked loop circuit 20 calibration data subframe DAT_0.In detail For thin, oscillator 206 is according to predicted phase error ΦESA phase compensation signal PC is generated, so that the adjustment input of multiplier 206 Compensated input signal CIN is generated after the phase of signal IN.Next, phase error detection unit 202 detects compensated input signal Phase error Φ in CIN between data burst DAT_0 and reference signal, so that filter 204 generates corresponding filtering signal (-Φ).Then, oscillator 206 can compensate input letter according to filtering signal (- Φ) adjustment phase place thermal compensation signal PC to reduce Phase error Φ in number CIN between data burst DAT_0 and reference signal.
Similarly, since guiding subframe PIL_1 is also given data, phase error prediction module 208 can be counted directly The phase error of guiding subframe PIL_1 is calculated as guiding phase error ΦML_P, to predict to be connected in the number of guiding subframe PIL_1 According to the phase error (step 306) of subframe DAT_1 (i.e. pilot data subframe).It is worth noting that, because guiding subframe PIL_1 Baud Length it is shorter, so be easier to it is affected by noise, cause guide phase error ΦML_PIt is too many to deviate true phase error, Reduce the calibration speed of phase-locked loop circuit.
To solve the above-mentioned problems, phase error adjustment module 210 can be according to header phase error ΦML_HWith guiding phase Error ΦML_PBetween relationship, generate predicted phase error ΦES(step 308).In one embodiment, when header phase error ΦML_HWith guiding phase error ΦML_PBetween gap less than an error threshold γ when (| ΦML_P1|-|ΦML_H| < γ, γ < 0), Phase error adjusts the judgement guiding of module 210 phase error ΦML_PIt is too many without departing from true phase error, and direct output steering Phase error ΦML_PAs predicted phase error ΦES.And work as header phase error ΦML_HWith guiding phase error ΦML_PBetween When gap is more than error threshold γ (| ΦML_P1|-|ΦML_H| > γ, γ < 0), phase error adjusts the judgement guiding phase of module 210 Position error ΦML_PIt is too many to deviate true phase error.In this situation, phase error adjustment module 210 can adjust guiding phase Error ΦML_P, then the guiding phase error Φ after output adjustmentML_PAs predicted phase error ΦES。
In one embodiment, phase error adjustment module 210 calculates guiding phase error ΦML_PWith a penalty coefficient CC's Product is as predicted phase error ΦES, wherein penalty coefficient CC is greater than 0 and less than 1, too many to weaken deviation true phase error Guiding phase error ΦML_PInfluence to the phase error Φ of calibration data subframe DAT_1 promotes phase-locked loop circuit 20 Calibration speed.
Referring to FIG. 5, Fig. 5 is the signal that a phase error according to depicted in one embodiment of the invention adjusts module 50 Figure.As shown in figure 5, phase error adjustment module 50 includes a control unit 500 and an arithmetic element 502.Control unit 500 For according to header phase error ΦML_HAnd guiding phase error ΦML_PBetween relationship generate control signal CON, arithmetic element 502 generate predicted phase error Φ according to control signal CONES.In this embodiment, arithmetic element 502 includes a multiplication Device 504 and a selector 506.Multiplier 504 is used to output steering phase error ΦML_PIt is extremely selected with the product of penalty coefficient CC Device 506, selector 506 is according to control signal CON output steering phase error ΦML_POr guiding phase error ΦML_PIt is with compensation The product of number CC is as predicted phase error ΦES.In one embodiment, control unit 500 includes for storing header phase Error ΦML_HStorage element, and in acquirement one guide phase error ΦML_PWhen, according to header phase error in same frame ΦML_HAnd guiding phase error ΦML_PBetween gap come generate control signal CON.Specifically, if judging header in same frame Phase error ΦML_HAnd guiding phase error ΦML_PBetween gap be less than error threshold γ when, control unit 500 generate control letter Number CON is so that 506 output steering phase error Φ of selectorML_PAs predicted phase error ΦES；If judging header in same frame Phase error ΦML_HAnd guiding phase error ΦML_PBetween gap be greater than error threshold γ when, control unit 500 adjustment control letter Number CON is so that 506 output steering phase error Φ of selectorML_PProduct between penalty coefficient CC is as predicted phase error ΦES。
In another embodiment, the predicted phase error Φ once exported before the directly output of phase error adjustment module 210ES (i.e. previous prediction phase error ΦES_PRE) it is used as predicted phase error ΦES.This is because data burst in same frame FRA Lead time between DAT_0~DAT_n is small, therefore the phase error of data burst DAT_0~DAT_n answers phase in same frame FRA Closely.It is worth noting that, in this embodiment, phase error adjustment module 210 can be in judging header phase error ΦML_HWith lead Draw phase error ΦML_PBetween gap be less than error threshold γ when, will guide phase error ΦML_PIt is stored as previous prediction phase Error ΦES_PRE。
Referring to FIG. 6, Fig. 6 is the signal that a phase error according to depicted in one embodiment of the invention adjusts module 60 Figure.As shown in fig. 6, phase error adjustment module 60 includes a control unit 600 and an arithmetic element 602.Control unit 600 For according to header phase error ΦML_HGuide phase error ΦML_PBetween relationship generate control signal CON, arithmetic element 602 Predicted phase error Φ is then generated according to control signal CONES.In this embodiment, arithmetic element 602 includes a storage element 604 and selector 606,608.Storage element 604 is used to store previous prediction phase error ΦES_PRE.Selector 606 is according to control Signal CON selection guiding phase error Φ processedML_PAnd previous prediction phase error ΦES_PREOne of them is missed as predicted phase Poor ΦES, selector 608 then according to control signal CON decide whether predicted phase error ΦESIt stores to storage element 604.
Specifically, if judging header phase error Φ in same frameML_HAnd guiding phase error ΦML_PBetween gap it is small When error threshold γ, control unit 600 generates control signal CON so that 606 output steering phase error Φ of selectorML_PMake For predicted phase error ΦES, and selector 608 is made to export predicted phase error ΦESTo storage element 604, to store at this time Predicted phase error ΦESAs previous prediction phase error ΦES_PRE；If judging header phase error Φ in same frameML_HAnd it leads Draw phase error ΦML_PBetween gap be greater than error threshold γ when, control unit 600 generate control signal CON so that selector The previous prediction phase error Φ that 606 outputs are stored in storage element 604ES_PREAs predicted phase error ΦES, and make to select It selects device 608 and stops output predicted phase error ΦESTo storage element 604.
Referring to FIG. 7, Fig. 7 is the signal that a phase error according to depicted in one embodiment of the invention adjusts module 70 Figure.As shown in fig. 7, phase error prediction module 70 includes a control unit 700 and an arithmetic element 702.Control unit 700 For according to header phase error ΦML_HAnd guiding phase error ΦML_PBetween relationship generate control signal CON1, arithmetic element 702 generate predicted phase error Φ according to control signal CON1ES.In this embodiment, arithmetic element 702 includes a multiplication Device 704, a storage element 706 and selector 708,710,712,714.In this embodiment, control unit 700, multiplier 704 And the operation principles of selector 708 are similar to control unit 500 shown in fig. 5, multiplier 504 and selector 506, and control single The operation principles of member 700, storage element 706 and selector 710,712 are similar to control unit 600 shown in fig. 6, storage element 604 and selector 606,608, for the sake of clarity, this will not be repeated here.
In this embodiment, control unit 700 is separately used to generate a control signal CON2 according to a noise indication signal NF, So that selector 714 selects output phase error Φ according to control signal CON2ES_1、ΦES_2One of them is missed as predicted phase Poor ΦES.Specifically, control unit 700 is in judging that noise in a specific time section becomes according to noise indication signal NF When dynamic value is less than a movement threshold, control 714 output phase error Φ of signal CON2 control selections device is generatedES_1As prediction phase Position error ΦES；Control unit 700 and in judging the noise change value in the specific time section according to noise indication signal NF When greater than the movement threshold, control 714 output phase error Φ of signal CON2 control selections device is generatedES_2It is missed as predicted phase Poor ΦES。
According to header phase error ΦML_HWith guiding phase error ΦML_PBetween relationship generate predicted phase error ΦES Afterwards, oscillator 206 is according to predicted phase error ΦESPhase compensation signal PC (step 310) is generated, so that multiplier 206 adjusts Compensated input signal CIN (step 312) is generated in input signal IN after the phase of pilot data subframe DAT_1.Next, phase Error detection unit 202 detects the phase error Φ in compensated input signal CIN between data burst DAT_1 and reference signal, with Filter 204 is set to generate corresponding filtering signal (- Φ) (step 314).Then, oscillator 206 can be according to filtering signal (- Φ) generates phase compensation signal PC (step 316), to reduce data burst DAT_1 and reference in compensated input signal CIN Phase error Φ between signal.
Through step 306~316 are repeated, phase-locked loop circuit 20 can be according to the phase error Φ of header subframe HEAMLWith lead Relationship between introduction frame PIL_1~PIL_n, to adjust separately the phase error as calibration data subframe DAT_1~DAT_n The predicted phase error Φ of initial valueES, missed with promoting the phase of 20 calibration data subframe DAT_1~DAT_n of phase-locked loop circuit The speed of difference.
Although the present invention is disclosed as above with preferred embodiment, however, it is not to limit the invention, any this field skill Art personnel, without departing from the spirit and scope of the present invention, when can make a little modification and perfect therefore of the invention protection model It encloses to work as and subject to the definition of the claims.

Claims (13)

1. a kind of method for handling phase alignment includes for a phase-locked loop circuit in a wireless communication apparatus：
Calculate a guiding subframe in a header phase error and the frame for a header subframe of a frame in an input signal one leads Draw phase error, wherein the header subframe and the guiding subframe are given data；
According to the relationship between the header phase error and the guiding phase error, a predicted phase error is generated；
According to the predicted phase error and a filtering signal, a phase compensation signal is generated；
According to the phase compensation signal, the input signal is adjusted, to generate a compensated input signal；
It detects in the compensated input signal corresponding to a pilot data subframe of the guiding subframe and the phase between a reference signal Position error；And
According to the phase error, the filtering signal is generated.
2. the method as described in claim 1, which is characterized in that according between the header phase error and the guiding phase error Relationship, the step of generating the predicted phase error include：
When the gap between the header phase error and the guiding phase error is less than an error threshold, guiding phase mistake is exported Difference is used as the predicted phase error.
3. the method as described in claim 1, which is characterized in that according between the header phase error and the guiding phase error Relationship, the step of generating the predicted phase error include：
When the gap between the header phase error and the guiding phase error is greater than an error threshold, guiding phase mistake is adjusted Difference generates the predicted phase error.
4. method as claimed in claim 3, which is characterized in that according between the header phase error and the guiding phase error Gap be greater than the error threshold between gap be greater than the error threshold when, adjust the predicted phase error to generate the prediction phase Position error the step of include：
It is greater than a judgement of the error threshold according to the gap between the header phase error and the guiding phase error, calculates this and lead Draw the product between phase error and a penalty coefficient as the predicted phase error, wherein the penalty coefficient is greater than 0 and is less than 1。
5. method as claimed in claim 4, which is characterized in that according between the header phase error and the guiding phase error Gap is greater than the judgement of the error threshold, calculates the product between the guiding phase error and the penalty coefficient as the prediction The step of phase error includes：
It is greater than the error threshold according to the gap between the absolute value of the header phase error and the absolute value of the guiding phase error The judgement and a phase noise change less than a movement threshold a judgement, calculate the guiding phase error and the penalty coefficient Between the product as the predicted phase error.
6. the method as described in claim 1, which is characterized in that according between the header phase error and the guiding phase error Relationship, the step of generating the predicted phase error include：
It is greater than a judgement of an error threshold according to the gap between the header phase error and the guiding phase error, previously with one Predicted phase error is as the predicted phase error.
7. method as claimed in claim 6, which is characterized in that according between the header phase error and the guiding phase error Gap is greater than the judgement of an error threshold, includes using the previous prediction phase error as the step of predicted phase error Have：
It is greater than the error threshold according to the gap between the absolute value of the header phase error and the absolute value error of the guiding phase The judgement and a phase noise change be greater than a movement threshold a judgement, using the previous prediction phase error as the prediction Phase error.
8. method as claimed in claim 6, also including：
It is less than the error threshold according to the gap between the absolute value of the header phase error and the absolute value of the guiding phase error A judgement, store the guiding phase error as the previous prediction phase error.
9. a kind of phase-locked loop circuit is used for a wireless telecommunication system, includes：
One phase error prediction module, for calculate a frame in an input signal a header subframe a header phase error and A guiding phase error of a guiding subframe in the frame, which is characterized in that the header subframe and the guiding subframe are given data；
One phase error adjusts module, for generating one according to the relationship between the header phase error and the guiding phase error Predicted phase error；
One oscillator is used to generate a phase compensation signal according to the predicted phase error and a filtering signal；
One multiplication unit is used to the input signal be adjusted, to generate a compensated input signal according to the phase compensation signal；
One phase error detection unit, for detecting the pilot data in the compensated input signal corresponding to the guiding subframe A phase error between frame and a reference signal；And
One filter is used to generate the filtering signal according to the phase error.
10. phase-locked loop circuit as claimed in claim 9, which is characterized in that the phase error adjusts module and includes：
One control unit is used to generate a first control signal according to the header phase error and the guiding phase error；
One arithmetic element is used to generate the predicted phase error according to the first control signal.
11. phase-locked loop circuit as claimed in claim 10, which is characterized in that the arithmetic element includes：
One multiplier, for calculating the product of the guiding phase error and a penalty coefficient as an adjustment guiding phase error； And
One selector, be used to according to the first control signal, export the guiding phase error and the adjustment guiding phase error its Middle one is as the predicted phase error.
12. phase-locked loop circuit as claimed in claim 10, which is characterized in that the arithmetic element includes：
One storage element, for storing a previous prediction phase error；
One first selector is used to export the guiding phase error according to the first control signal and the previous prediction phase is missed Poor one of them is as the predicted phase error；And
One second selector is used to be stored the predicted phase error to the storage element according to the first control signal.
13. phase-locked loop circuit as claimed in claim 10, which is characterized in that the control unit indicates to believe further accordance with a noise Number a second control signal is generated, and the arithmetic element includes：
One multiplier, for calculating the product of the guiding phase error and a penalty coefficient as an adjustment guiding phase error； And
One storage element, for storing a previous prediction phase error；
One first selector is used to export the guiding phase error according to the first control signal and adjustment guiding phase is missed Poor one of them is as a first phase error；
One second selector is used to export the guiding phase error according to the first control signal and the previous prediction phase is missed Poor one of them is as a second phase error；
One third selector is used to be stored the predicted phase error to the storage element according to the first control signal；And
One the 4th selector, is used to according to the second control signal, export the first phase error and the second phase error its Middle one is as the predicted phase error.
CN201710316418.7A 2017-05-08 2017-05-08 Phase alignment and relevant phase-locked loop circuit Withdrawn CN108880533A (en)

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