CN108879605B - Over-temperature protection circuit - Google Patents

Over-temperature protection circuit Download PDF

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Publication number
CN108879605B
CN108879605B CN201810937698.8A CN201810937698A CN108879605B CN 108879605 B CN108879605 B CN 108879605B CN 201810937698 A CN201810937698 A CN 201810937698A CN 108879605 B CN108879605 B CN 108879605B
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voltage
nmos tube
unit
power supply
output end
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CN108879605A (en
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黄富俊
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Xiamen Yuanshun Microelectronics Technology Co ltd
Unisonic Technologies Co Ltd
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Xiamen Yuanshun Microelectronics Technology Co ltd
Unisonic Technologies Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H5/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection
    • H02H5/04—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection responsive to abnormal temperature
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/02—Details
    • H02H3/05—Details with means for increasing reliability, e.g. redundancy arrangements

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Abstract

An over-temperature protection circuit, comprising: an internal power supply generating unit for supplying a first voltage as a voltage source; an internal current generating unit for providing a rated current as a rated current source; the voltage input end of the comparison judging unit is connected with the output end of the internal power supply generating unit, and the current input end of the comparison judging unit is connected with the output end of the internal current generating unit; the comparison judging unit is used for generating a corresponding output signal according to the temperature, so as to realize the output of the enabled digital signal. The over-temperature protection circuit is simple in structure, and can save power consumption when being used for over-temperature protection.

Description

Over-temperature protection circuit
Technical Field
The invention relates to the technical field of electronics, in particular to an over-temperature protection circuit.
Background
With the rapid development of semiconductor technology and microelectronic technology, the over-temperature protection technology has been widely applied to various fields such as consumer electronics, communication equipment, industrial application, aerospace and the like. In order to facilitate the over-temperature protection of the chip by the electronic system, temperature monitoring is usually arranged in the chip for controlling the over-temperature shutdown of the chip, so that an over-temperature protection circuit is usually required to be designed in the chip.
In general application, the built-in circuit of the chip converts the temperature information into related voltage or current information, so that the over-temperature protection circuit can obtain the temperature and generate a turn-off signal when the temperature reaches a critical temperature, thereby protecting the corresponding components from damage.
However, the existing over-temperature protection circuit generally brings about a loss in power consumption or affects the stability of bandgap voltage in the chip.
For example, in the over-temperature protection circuit shown in fig. 1, an NPN tube 11 and a buffer 13 are included, a collector of the NPN tube 11 is connected to a current source 12, and a collector of the NPN tube 11 is used as a signal output terminal of the over-temperature protection circuit. In the over-temperature protection circuit shown in fig. 1, the buffer 13 may not be used, but when the buffer 13 is not used, the NPN tube 11 pulls down the reference voltage connected to the base (i.e., the reference voltage is disturbed), and the reference voltage is pulled down, which easily affects other elements to supply power, and if the buffer 13 is added at present, the buffer 13 itself needs to consume a certain current, resulting in a loss of power.
The over-temperature protection circuit shown in fig. 2 is further improved on the basis of the circuit shown in fig. 1, and also comprises an NPN tube 11 and a current source 12 connected to one end of the collector of the NPN tube 11. However, in fig. 2, a buffer is not needed, but a voltage dividing circuit and a feedback circuit are added, the voltage dividing circuit includes a resistor 14 and a resistor 15 connected in series, the other end of the resistor 14 is connected to a current source 17, the other end of the resistor 15 is grounded, the base of the NPN tube 11 is connected between the resistor 14 and the current source 17, meanwhile, a MOS tube 16 is further provided in the circuit, the drain electrode of the MOS tube 16 is connected between the resistor 14 and the resistor 15, the source electrode is connected between the resistor 15 and the ground (i.e., grounded), and the gate electrode of the MOS tube 16 is connected to the signal output end of the over-temperature protection circuit, i.e., connected between the current source 12 and the collector electrode of the NPN tube 11. In the configuration of fig. 2, at any time (i.e. whether or not a protected state is entered), additional current consumption is required (this current is provided by the current source 17), resulting in a loss of power consumption.
Disclosure of Invention
The invention solves the problem of providing an over-temperature protection circuit, which can realize good over-temperature protection and save power consumption.
In order to solve the above problems, the present invention provides an over-temperature protection circuit, comprising: an internal power supply generating unit for supplying a first voltage as a voltage source; an internal current generating unit for providing a rated current as a rated current source; the voltage input end of the comparison judging unit is connected with the output end of the internal power supply generating unit, and the current input end of the comparison judging unit is connected with the output end of the internal current generating unit; the comparison judging unit is used for generating a corresponding output signal according to the temperature, so as to realize the output of the enabled digital signal.
Optionally, the over-temperature protection circuit further comprises a hysteresis conversion unit, and the hysteresis conversion unit is located between the comparison judging unit and the digital signal output end of the circuit.
Optionally, the power input end of the internal power supply generating unit is connected with a high-voltage power supply and is used for converting the high-voltage power supply into a low-voltage power supply, and is used for providing the first voltage for the comparison judging unit, and the power output end of the internal power supply generating unit is used as a comparison voltage point of the comparison judging unit; the power input end of the internal current generating unit is connected with the high-voltage power supply, is used for converting the high-voltage power supply into a rated current power supply and is used for providing the rated current for the comparison and judgment unit.
Optionally, the comparison judging unit includes a first NMOS tube, a second NMOS tube, and n NPN tubes, where n is an integer greater than 2; the drain electrode of the first NMOS tube is connected with the output end of the internal current generation unit, and the grid electrode of the first NMOS tube is connected with the output end of the internal power supply generation unit; the collector electrode of the 1 st NPN tube is connected with the source electrode of the first NMOS tube; the collector of the latter NPN tube is connected with the emitter of the former NPN tube, and the respective collectors and bases of the n NPN tubes are connected; the second NMOS tube is a depletion type NMOS tube, the drain electrode of the second NMOS tube is connected with the emitter electrode of the n NPN tube, the grid electrode of the second NMOS tube is connected with the source electrode, and the source electrode of the second NMOS tube is grounded.
Optionally, the hysteresis conversion unit includes an inverter and a third NMOS tube; the input end of the inverter is connected with the output end of the internal current generating unit; the grid electrode of the third NMOS tube is connected with the output end of the inverter, the drain electrode of the third NMOS tube is connected with the collector electrode and the base electrode of the nth NPN tube, and the source electrode of the third NMOS tube is connected with the emitter electrode of the nth NPN tube.
Optionally, n is equal to 5.
Optionally, the comparison judging unit includes a first NMOS tube, a second NMOS tube, and m NPN tubes, where m is an integer greater than 1; the comparison judging unit further comprises a voltage dividing element, wherein the voltage dividing element is a resistor or a diode; the drain electrode of the first NMOS tube is connected with the output end of the internal current generation unit, and the grid electrode of the first NMOS tube is connected with the output end of the internal power supply generation unit; the collector electrode of the 1 st NPN tube is connected with the source electrode of the first NMOS tube; the collector of the latter NPN tube in the m NPN tubes is connected with the emitter of the former NPN tube, and the respective collectors and base electrodes of the m NPN tubes are connected; the first end of the voltage dividing element is connected with the emitter of the mth NPN tube; the second NMOS tube is a depletion type NMOS tube, the drain electrode of the second NMOS tube is connected with the second end of the voltage dividing element, the grid electrode of the second NMOS tube is connected with the source electrode, and the source electrode of the second NMOS tube is grounded.
Alternatively, m is equal to 4.
Optionally, the hysteresis conversion unit includes an inverter and a third NMOS tube; the input end of the inverter is connected with the output end of the internal current generating unit; the grid electrode of the third NMOS tube is connected with the output end of the inverter, the drain electrode of the third NMOS tube is connected with the first end of the voltage dividing element, and the source electrode of the third NMOS tube is connected with the second end of the voltage dividing element.
Optionally, the comparison judging unit includes a first NMOS tube, a second NMOS tube, and k diodes, where k is an integer greater than 1; the comparison judging unit further comprises a voltage dividing element, wherein the voltage dividing element is a resistor or a diode; the drain electrode of the first NMOS tube is connected with the output end of the internal current generation unit, and the grid electrode of the first NMOS tube is connected with the output end of the internal power supply generation unit; the anode of the 1 st diode is connected with the source electrode of the first NMOS tube; the anode of the latter diode in the k diodes is connected with the cathode of the former diode; the first end of the voltage dividing element is connected with the cathode of the kth diode; the second NMOS tube is a depletion type NMOS tube, the drain electrode of the second NMOS tube is connected with the second end of the voltage dividing element, the grid electrode of the second NMOS tube is connected with the source electrode, and the source electrode of the second NMOS tube is grounded.
Optionally, the internal power supply generating unit includes a voltage reducing unit and a buffer, an output end of the voltage reducing unit is connected with an input end of the buffer, and the internal power supply generating unit further includes a first resistor and a second resistor connected with an output end of the buffer.
Optionally, the first resistor is connected with the second resistor, and a voltage division end between the first resistor and the second resistor is used as an output end of the internal power supply generating unit.
In one aspect of the technical scheme of the invention, the whole circuit has a simple structure, is suitable for an over-temperature protection circuit with low power consumption, and does not have power consumption loss before the temperature is not protected. Only after entering the over-temperature protection state will there be a corresponding current consumption.
In another aspect of the technical scheme of the invention, the over-temperature protection circuit can avoid disturbance influence on the reference voltage.
Drawings
FIG. 1 is a diagram of a prior art over-temperature protection circuit;
FIG. 2 is a diagram of a prior art over-temperature protection circuit;
FIG. 3 is a schematic diagram of an over-temperature protection circuit according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of the over-temperature protection circuit schematic shown in FIG. 3;
Fig. 5 is a circuit diagram of an over-temperature protection circuit according to another embodiment of the present invention.
Detailed Description
As described in the background art, the existing over-temperature protection circuit has large power consumption and cannot give consideration to factors which affect disturbance on the reference voltage. Therefore, the invention provides a novel over-temperature protection circuit to solve the defects.
The present invention will be described in detail with reference to the accompanying drawings for more clear illustration.
The embodiment of the invention provides an over-temperature protection circuit, please refer to fig. 3.
The over-temperature protection circuit includes an internal power generation unit 310, an internal current generation unit 320, and a comparison judgment unit 330.
The internal power generation unit 310 is used to supply a first voltage as a voltage source. The first voltage is typically a low voltage, the circuit input power VCC may be a high voltage, typically 12V to 40V, and the first voltage may be a low voltage of 1.2V (the low voltage may range from 0.6V to 5V). It can be seen that in this embodiment, the high voltage and the low voltage are for the chip circuit.
The internal current generating unit 320 is configured to provide a rated current I31 as a rated current source (not labeled).
The voltage input end of the comparison and judgment unit 330 is connected with the output end of the internal power supply generating unit 310, and the current input end of the comparison and judgment unit 330 is connected with the output end of the internal current generating unit 320. The comparison and judgment unit 330 is used for generating a corresponding output signal according to the temperature, so as to realize the output of the enabled digital signal. Specifically, the comparing and judging unit 330 is configured to jump the output of each element when the temperature changes to a certain value, so as to realize digital signal output and achieve an over-temperature protection effect.
When the comparison and judgment unit 330 accesses the first voltage, only the corresponding voltage is required, and the driver function is not required, that is, the corresponding driving capability is not required. Therefore, the first voltage connection at this time does not consume current, i.e. does not cause loss of power consumption. That is, the comparison and judgment unit 330 provided in this embodiment does not consume current when the circuit does not enter the over-temperature protection state, thereby saving power consumption.
In this embodiment, the over-temperature protection circuit further includes a hysteresis conversion unit 340, and the hysteresis conversion unit 340 is located between the comparison and judgment unit 330 and a digital signal output end (not labeled, may be an output end of the inverter in fig. 4) of the circuit. The hysteresis conversion unit 340 has a signal interaction with the comparison judgment unit 330, and thus such a relationship is indicated by a corresponding arrow in fig. 3. The hysteresis conversion unit 340 is configured to ensure that there is a temperature difference hysteresis after the signal output that enables the over-temperature protection is achieved, so that the system is continuously stopped, and the corresponding protection is not released until the temperature is lower than the safe temperature difference, thereby preventing the over-temperature protection circuit from frequently outputting different signals (i.e., avoiding frequent switching of the protection circuit), and optimizing the corresponding over-temperature protection effect.
In this embodiment, the power input terminal of the internal power generating unit 310 is connected to a circuit high voltage power supply (circuit input power VCC), and is used for converting the high voltage power supply into a low voltage power supply, for providing the first voltage to the comparing and judging unit 330, and the power output terminal of the internal power generating unit 310 is used as the comparing voltage point of the comparing and judging unit 330. The power input terminal of the internal current generating unit 320 is connected to an input high-voltage power supply (circuit input power VCC), and is used for converting the high-voltage power supply into a rated current power supply for providing the rated current to the comparison judging unit 330.
In this embodiment, as shown in fig. 4, a specific circuit structure of the comparison and judgment unit 330 corresponding to fig. 3 is shown in fig. 4, and the comparison and judgment unit 330 includes a first NMOS transistor N31, a second NMOS transistor N32, a first NPN transistor 331, a second NPN transistor 332, a third NPN transistor 333, a fourth NPN transistor 334, and a fifth NPN transistor 335.
The drain of the first NMOS transistor N31 is connected to the output terminal of the internal current generating unit 320, and the gate of the first NMOS transistor N31 is connected to the output terminal of the internal power generating unit 310.
The collector and the base of the first NPN tube 331 are connected, and the collector of the first NPN tube 331 is connected with the source of the first NMOS tube N31.
The collector of the second NPN tube 332 is connected to the base, and the collector of the second NPN tube 332 is connected to the emitter of the first NPN tube 331.
The collector and base of the third NPN tube 333 are connected, and the collector of the third NPN tube 333 is connected to the emitter of the second NPN tube 332.
The collector and base of the fourth NPN tube 334 are connected, and the collector of the fourth NPN tube 334 is connected to the emitter of the third NPN tube 333.
The collector and base of fifth NPN tube 335 are connected, and the collector of fifth NPN tube 335 is connected to the emitter of fourth NPN tube 334.
The second NMOS transistor N32 is a depletion NMOS transistor, the drain electrode of the second NMOS transistor N32 is connected to the emitter electrode of the fifth NPN transistor 335, the gate electrode of the second NMOS transistor N32 is connected to the source electrode, and the source electrode of the second NMOS transistor N32 is grounded.
In the above circuit structure, when the gate and the source of the second NMOS transistor N32 are equipotential, a current may flow through the second NMOS transistor N32. That is, the second NMOS transistor N32 ensures that current flows to ground.
In other embodiments, the comparing and judging unit may include a first NMOS transistor, a second NMOS transistor, and n NPN transistors, where n is an integer greater than 3. The drain electrode of the first NMOS tube is connected with the output end of the internal current generating unit, and the grid electrode of the first NMOS tube is connected with the output end of the internal power supply generating unit. The collector of the 1 st NPN tube is connected with the source of the first NMOS tube. The collector of the latter NPN tube is connected with the emitter of the former NPN tube, and the respective collectors and bases of the n NPN tubes are connected. The second NMOS tube is a depletion type NMOS tube, the drain electrode of the second NMOS tube is connected with the emitter electrode of the n-th NPN tube, the grid electrode of the second NMOS tube is connected with the source electrode, and the source electrode of the second NMOS tube is grounded. Correspondingly, the hysteresis conversion unit comprises an inverter and a third NMOS tube. The input end of the inverter is connected with the output end of the internal current generating unit. The grid electrode of the third NMOS tube is connected with the output end of the inverter, the drain electrode of the third NMOS tube is connected with the collector electrode and the base electrode of the nth NPN tube, and the source electrode of the third NMOS tube is connected with the emitter electrode of the nth NPN tube. That is, the specific circuit shown in fig. 4 is a case where n is equal to 5.
In a specific circuit structure of the hysteresis conversion unit 340, as shown In fig. 4, the hysteresis conversion unit 340 includes an inverter In31 and a third NMOS transistor N33. The input terminal of the inverter In31 is connected to the output terminal of the internal current generation unit 320. The gate of the third NMOS transistor N33 is connected to the output end of the inverter In31, the drain of the third NMOS transistor N33 is connected to the base of the fifth NPN transistor 335, and the source of the third NMOS transistor N33 is connected to the emitter of the fifth NPN transistor 335.
The internal power generation unit 310 includes a step-down unit 311 and a buffer B31, and an output terminal of the step-down unit 311 is connected to an input terminal of the buffer B31. The step-down unit 311 may convert the circuit input power VCC into the reference voltage VBG. In the circuit of this embodiment, since the reference voltage VBG is connected to the gate of the NMOS transistor, even if the buffer B31 is not used, the reference voltage VBG is directly connected to the gate of the first NMOS transistor N31, and the whole circuit can avoid disturbance influence on the reference voltage VBG while ensuring over-temperature protection (otherwise, in the case of fig. 1, since the voltage is connected to the base of the NPN transistor, if the buffer is not connected during over-temperature protection, the reference voltage is significantly affected).
The internal power generation unit 310 further includes a first resistor R31 and a second resistor R32 connected to the output terminal of the buffer B31. It should be noted that, in the over-temperature protection circuit provided in this embodiment, the buffer B31, the first resistor R31 and the second resistor R32 may be omitted, so that the corresponding power consumption is smaller, and meanwhile, due to the effect of the corresponding NPN tube, when the circuit enters the protection state, the circuit will not cause obvious pull-down of the input end reference voltage, that is, will not cause adverse effect on the reference voltage, so that power supply of other elements will not be adversely affected.
The first resistor R31 is connected to the second resistor R32, and a voltage division end between the first resistor R31 and the second resistor R32 is used as an output end of the internal power generation unit 310. In this embodiment, the output end of the buffer B31 is connected to an end of the first resistor R31 away from the second resistor R32.
It should be noted that, the first NMOS transistor N31 may be various types of NMOS transistors, but when the first NMOS transistor N31 and the second NMOS transistor N32 are depletion type NMOS transistors, the turn-off voltage Vgs (off) of the first NMOS transistor N31 and the second NMOS transistor N32 is about-0.6V (different turn-off voltage values in different processes, generally, the turn-off voltage is negative), and the first NMOS transistor N31 and the second NMOS transistor N32 may be matched (matching) so that the circuit is more stable and reliable.
In the circuit shown in fig. 4, the overall power consumption is very small, and basically no current is consumed when the over-temperature protection state is not entered (particularly when the corresponding buffer B31 is not used), but only a small current is consumed when the over-temperature protection state is entered, that is, when the over-temperature protection signal output is generated (this current is supplied by the rated current).
The over-temperature protection circuit provided in this embodiment is applicable to an over-temperature protection circuit with low power consumption, and before the temperature is not protected, the internal current generating unit 320, the comparison judging unit 330, and the hysteresis converting unit 340 (except for the current consumption when the buffer B31 exists, but at the same time the buffer B31 may be omitted) will not have power consumption loss. Only after entering the over-temperature protection state, the corresponding current consumption exists, and meanwhile, the over-temperature protection circuit can avoid the disturbance influence on the reference voltage.
In addition, in the over-temperature protection circuit provided in this embodiment, the added hysteresis conversion unit 340, the hysteresis conversion unit 340 will release protection after cooling the system according to the hysteresis temperature difference, so as to prevent the corresponding circuit from being frequently turned off and on, and further optimize the corresponding over-temperature protection effect.
When the grid electrode of the depletion type NMOS tube is connected with the source electrode, current can be generated as long as the drain voltage is higher than the source voltage. Meanwhile, the turn-off voltage Vgs (off) of the depletion type NMOS is negative, usually about-0.6V (i.e., the emitter junction voltage Vbe), so that the depletion type NMOS is turned off and not turned on when the potential of the gate is lower than the potential of the source to a certain value. (for example, if the turn-off voltage is-0.6V, if the gate potential is 2V, the source voltage needs to be above 2.6V before the depletion NMOS transistor turns off.
Therefore, in fig. 4, when the gate of the first NMOS transistor N31 is connected to 1.2V (i.e., in a specific case, the gate of the first NMOS transistor N31 is connected to 1.2V), if the source voltage of the first NMOS transistor N31 is greater than 1.8V, the first NMOS transistor N31 is turned off, and if the source voltage of the first NMOS transistor N31 is less than 1.8V, the first NMOS transistor N31 is turned on. When the first NMOS transistor N31 is turned on, the NPN transistors and the second NMOS transistor N32 all have currents flowing therethrough, and the current that the second NMOS transistor N32 can pass through may be set to be larger than the rated current I31 at the beginning.
At this time, considering that the natural voltage (natural voltage drop, that is, the emitter junction voltage Vbe, which is usually 0.6V at normal temperature) of each NPN tube is higher, after they are connected into the series structure shown in fig. 4, the source potential of the first NMOS tube N31 can be raised, so that the source potential is higher than the gate potential by more than 0.6V, that is, the first NMOS tube N31 is ensured to be turned off, so that the corresponding rated current I31 cannot flow through the first NMOS tube N31, so that the drain potential of the first NMOS tube N31 is ensured to be kept higher (or so that each NPN tube is pulled up by the drain potential of the first NMOS tube N31), and the drain high potential of the first NMOS tube N31 is outputted as a low level signal after passing through the inverter, at this time, that is, the whole circuit does not enter the over-temperature protection state.
When the temperature rises, due to the negative temperature effect of the NPN transistors, their natural voltage drops, i.e. the emitter junction voltage Vbe drops. The effect of temperature on the emitter junction voltage Vbe is typically: the temperature rises by 1 deg.c and Vbe will drop by about 2mV. When the emitter junction of the NPN tube is forward biased, the voltage difference Vbe is about 0.6V at normal temperature. From this, it can be seen that when the temperature rises to 150 ℃, vbe will drop to 0.35V, and at this time, as shown in fig. 4, the 5 NPN transistors make the voltage about 1.75V in total (since the second NMOS transistor N32 is a depletion NMOS transistor, the drop of its drain-source voltage Vds is extremely small, which may not be considered). Therefore, at 150 ℃, the gate-source voltage Vgs of the first NMOS transistor N31 as depletion type can be changed from off voltage to on voltage, that is, when the temperature rises to 150 ℃, the first NMOS transistor N31 can be turned on.
Once the first NMOS transistor N31 is turned on, the rated current I31 can flow to each NPN transistor and the second NMOS transistor N32, and since the rated current I31 is small, the drain potential of the first NMOS transistor N31 is pulled down (Vds is not required to be large, and a current flows through it), that is, the output voltage connected to the drain of the first NMOS transistor N31 is pulled down to a relatively low voltage. This low voltage signal is converted into a high level output signal after passing through the inverter In 31. When the whole circuit generates a high-level output signal, an over-temperature protection enabling signal is generated, so that the circuit is correspondingly in an over-temperature protection state.
As can be seen from the above process, when the temperature increases, the Vbe of the NPN transistor decreases, and when the first NMOS transistor N31 is turned on due to the decrease, the current flows through the first NMOS transistor N31, and when the current flowing through the first NMOS transistor N31 is greater than the rated current I31 provided by the internal current generating unit 320, the corresponding voltage decreases (the output voltage connected to the drain of the first NMOS transistor N31 decreases).
In summary, in the present embodiment, the voltage of the gate electrode of the first NMOS transistor N31 is the first pass, which determines how much voltage the source electrode of the first NMOS transistor N31 has, and the corresponding first NMOS transistor N31 is turned on and off. The source voltage of the first NMOS transistor N31 is derived from NPN transistors, which are clamp circuits, clamping and fixing the potential at corresponding values. The source potential is affected by temperature, and when the temperature is not high enough, the NPN transistors and the second NMOS transistor N32 cannot be turned on, so that no current can flow, at this time, the comparing and judging unit 340 does not consume current, and only when the temperature is too high and the first NMOS transistor N31 is turned on to generate current, a current larger than the current I31 flows (the amplifying effect of the first NMOS transistor N31), at this time, the drain voltage of the first NMOS transistor N31 drops due to the fact that the current flowing through the first NMOS transistor N31 and the second NMOS transistor N32 can be larger than the current I31, and the circuit outputs a high voltage enabling signal after passing through the inverter In 31.
For the hysteresis conversion unit 340, when a high level signal is output in the circuit, four effective NPN guaranteed voltage drops remain, and at this time, it is generally necessary to wait until the temperature drops to about 100 ℃, that is, when the Vbe of each NPN tube increases to about 0.45V, to turn off the first NMOS tube N31 again (at this time, the Vbe of the four NPN tubes increases the source voltage of the first NMOS tube N31 to more than 1.8V again), so that the circuit exits the over-temperature protection state. Therefore, the embodiment can ensure that the over-temperature protection state is exited after the temperature is reduced from 150 ℃ to 100 ℃, thereby realizing the hysteresis protection function and preventing the circuit from frequently entering and exiting the over-temperature protection state.
It should be noted that, in other embodiments, in the circuit shown in fig. 4, each NPN tube may be replaced by a diode. That is, in other embodiments of the present invention, the comparison and judgment unit may include a first NMOS transistor, a second NMOS transistor, and k diodes, where k is an integer of 1 or more; the comparison judging unit further comprises a voltage dividing element, wherein the voltage dividing element is a resistor or a diode; the drain electrode of the first NMOS tube is connected with the output end of the internal current generation unit, and the grid electrode of the first NMOS tube is connected with the output end of the internal power supply generation unit; the anode of the 1 st diode is connected with the source electrode of the first NMOS tube; the anode of the latter diode in the k diodes is connected with the cathode of the former diode; the first end of the voltage dividing element is connected with the cathode of the kth diode; the second NMOS tube is a depletion type NMOS tube, the drain electrode of the second NMOS tube is connected with the second end of the voltage dividing element, the grid electrode of the second NMOS tube is connected with the source electrode, and the source electrode of the second NMOS tube is grounded. Since the diode has the same negative temperature coefficient as the NPN tube, both can be replaced.
An embodiment of the present invention provides another over-temperature protection circuit, please refer to fig. 5.
The over-temperature protection circuit includes an internal power generation unit 410, an internal current generation unit 420, and a comparison judgment unit 430.
The internal power generation unit 410 is used to provide a first voltage as a voltage source. The first voltage is typically a low voltage, the circuit input power VCC may be a high voltage, typically 12V to 40V, and the first voltage may be a low voltage of 1.2V (the low voltage may range from 0.6V to 5V). It can be seen that in this embodiment, the high voltage and the low voltage are for the chip circuit.
The internal current generating unit 420 is configured to provide a rated current I41 as a rated current source (not labeled).
The voltage input end of the comparison and judgment unit 430 is connected with the output end of the internal power supply generating unit 410, and the current input end of the comparison and judgment unit 430 is connected with the output end of the internal current generating unit 420. The comparison and judgment unit 430 is used for generating a corresponding output signal according to the temperature, so as to realize the output of an enabled digital signal and the over-temperature protection.
In this embodiment, the over-temperature protection circuit further includes a hysteresis conversion unit 440, and the hysteresis conversion unit 440 is located between the comparison and judgment unit 430 and a digital signal output end (not labeled, may be an output end of the inverter in fig. 5) of the circuit.
In this embodiment, a specific circuit structure of the comparison and judgment unit 430 corresponding to fig. 5 is shown in fig. 5, and the comparison and judgment unit 430 includes a first NMOS transistor N41, a second NMOS transistor N42, a first NPN transistor 431, a second NPN transistor 432, a third NPN transistor 433, a fourth NPN transistor 434, and a diode D435.
The drain of the first NMOS transistor N41 is connected to the output terminal of the internal current generating unit 420, and the gate of the first NMOS transistor N41 is connected to the output terminal of the internal power generating unit 410.
The collector and the base of first NPN pipe 431 link to each other, and the collector of first NPN pipe 431 connects the source of first NMOS pipe N41.
The collector and base of second NPN tube 432 are connected, and the collector of second NPN tube 432 is connected with the emitter of first NPN tube 431.
The collector of the third NPN tube 433 is connected with the base, and the collector of the third NPN tube 433 is connected with the emitter of the second NPN tube 432.
The collector of the fourth NPN tube 434 is connected to the base, and the collector of the fourth NPN tube 434 is connected to the emitter of the third NPN tube 433.
One end (positive electrode) of the diode D435 is connected to the emitter of the fourth NPN tube 434.
The second NMOS transistor N42 is a depletion NMOS transistor, the drain electrode of the second NMOS transistor N42 is connected to the other end (negative electrode) of the diode D435, the gate electrode of the second NMOS transistor N42 is connected to the source electrode, and the source electrode of the second NMOS transistor N42 is grounded.
In other embodiments, the comparison and judgment unit may also include a first NMOS tube, a second NMOS tube, and m NPN tubes, where m is an integer greater than 2; the comparison judging unit also comprises a voltage dividing element which is a resistor or a diode; the drain electrode of the first NMOS tube is connected with the output end of the internal current generating unit, and the grid electrode of the first NMOS tube is connected with the output end of the internal power supply generating unit; the collector of the 1 st NPN tube is connected with the source of the first NMOS tube; the collector of the latter NPN tube in the m NPN tubes is connected with the emitter of the former NPN tube, and the respective collectors and base electrodes of the m NPN tubes are connected; the first end of the voltage dividing element is connected with the emitter of the mth NPN tube; the second NMOS tube is a depletion type NMOS tube, the drain electrode of the second NMOS tube is connected with the second end of the voltage dividing element, the grid electrode of the second NMOS tube is connected with the source electrode of the second NMOS tube, and the source electrode of the second NMOS tube is grounded. Fig. 5 is a case where m is equal to 4, and the voltage dividing element is a diode.
In a specific circuit structure of the hysteresis conversion unit 440, as shown In fig. 5, the hysteresis conversion unit 440 includes an inverter In41 and a third NMOS transistor N43. An input terminal of the inverter In41 is connected to an output terminal of the internal current generating unit 420. The gate of the third NMOS transistor N43 is connected to the output terminal of the inverter In41, the drain of the third NMOS transistor N43 is connected to one end (positive electrode) of the diode D435, and the source of the third NMOS transistor N43 is connected to the other end (negative electrode) of the diode D435.
In other embodiments, the hysteresis conversion unit may include an inverter and a third NMOS transistor; the input end of the inverter is connected with the output end of the internal current generating unit; the grid electrode of the third NMOS tube is connected with the output end of the inverter, the drain electrode of the third NMOS tube is connected with the first end of the voltage dividing element, and the source electrode of the third NMOS tube is connected with the second end of the voltage dividing element. The voltage dividing element is used for adjusting the hysteresis.
The internal power generation unit 410 includes a step-down unit 411 and a buffer B41, and an output terminal of the step-down unit 411 is connected to an input terminal of the buffer B41. The step-down unit 411 may convert the circuit input power VCC into the reference voltage VBG. The circuit of the embodiment can reduce the influence on the reference voltage VBG while ensuring over-temperature protection.
The internal power generating unit 410 further includes a fourth NMOS transistor N44, a first resistor R41, and a second resistor R42 connected to the output terminal of the buffer B41. It should be noted that, in the over-temperature protection circuit provided in this embodiment, the buffer B41, the first resistor R41, the second resistor R42 and the fourth NMOS transistor N44 may be omitted, so that the corresponding power consumption is smaller, and meanwhile, even if the corresponding buffer B41 is omitted, due to the effect of the corresponding NPN transistor, when the circuit enters the protection state, no obvious pull-down of the reference voltage of the input end is caused, that is, no adverse effect is caused on the reference voltage, so that no adverse effect is caused on the power supply of other elements.
In this embodiment, the first resistor R41 is connected to the second resistor R42, the voltage division end between the first resistor R41 and the second resistor R42 is used as a feedback point, and the sources of the first resistor R41 and the fourth NMOS transistor N44 are connected to the output end of the internal power supply generating unit 410. In this embodiment, the output end of the buffer B41 is connected to the gate of the fourth NMOS transistor N44, and the drain of the fourth NMOS transistor N44 is connected to another power source (not labeled).
It should be noted that, in other embodiments, the fourth NMOS transistor N44 may be directly integrated in the buffer B41, and the corresponding circuit of the integrated internal power generation unit is close to the internal power generation unit 310 shown in fig. 4, except that the internal power generation unit connects the corresponding feedback point between the first resistor and the second resistor, that is, the connection of the feedback point is similar to fig. 5.
The over-temperature protection circuit provided in this embodiment is applicable to an over-temperature protection circuit with low power consumption, and the internal current generating unit 420, the comparison judging unit 430, the hysteresis converting unit 440 (except for the current consumption when the buffer B41 exists) will not have power consumption loss before the temperature is not protected. Only after entering the over-temperature protection state, the corresponding current consumption exists, and meanwhile, the over-temperature protection circuit can avoid the disturbance influence on the reference voltage.
In addition, in the over-temperature protection circuit provided in this embodiment, the added hysteresis conversion unit 440, the hysteresis conversion unit 440 will release protection after the system is cooled according to the hysteresis temperature difference, so as to prevent the corresponding circuit from being frequently turned off and on, and further optimize the corresponding over-temperature protection effect.
Meanwhile, in this embodiment, the corresponding hysteresis is adjusted by the diode D435 to control the magnitude of the hysteresis (the length of the hysteresis time, or the magnitude of the cooling range).
In other embodiments, the diode D435 may be replaced by a resistor, that is, the voltage dividing element may be a resistor, so as to achieve the purpose of controlling the hysteresis by controlling the size of the resistor.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (7)

1. An over-temperature protection circuit, comprising:
An internal power supply generating unit for supplying a first voltage as a voltage source;
an internal current generating unit for providing a rated current as a rated current source;
The voltage input end of the comparison judging unit is connected with the output end of the internal power supply generating unit, and the current input end of the comparison judging unit is connected with the output end of the internal current generating unit; the comparison judging unit is used for generating a corresponding output signal according to the temperature, so as to realize the output of an enabled digital signal;
The circuit also comprises a hysteresis conversion unit, wherein the hysteresis conversion unit is positioned between the comparison judging unit and the digital signal output end of the circuit;
The comparison judging unit comprises a first NMOS tube, a second NMOS tube and n NPN tubes, wherein n is an integer more than 2;
the drain electrode of the first NMOS tube is connected with the output end of the internal current generation unit, and the grid electrode of the first NMOS tube is connected with the output end of the internal power supply generation unit;
The collector electrode of the 1 st NPN tube is connected with the source electrode of the first NMOS tube;
The collector of the latter NPN tube is connected with the emitter of the former NPN tube, and the respective collectors and bases of the n NPN tubes are connected;
The second NMOS tube is a depletion type NMOS tube, the drain electrode of the second NMOS tube is connected with the emitter electrode of the n NPN tube, the grid electrode of the second NMOS tube is connected with the source electrode, and the source electrode of the second NMOS tube is grounded;
The internal power supply generating unit comprises a voltage reducing unit and a buffer, wherein the output end of the voltage reducing unit is connected with the input end of the buffer, and the internal power supply generating unit further comprises a first resistor and a second resistor which are connected with the output end of the buffer; the first resistor is connected with the second resistor, and a voltage division end between the first resistor and the second resistor is used as an output end of the internal power supply generating unit.
2. The over-temperature protection circuit of claim 1, wherein the hysteresis conversion unit comprises an inverter and a third NMOS transistor;
The input end of the inverter is connected with the output end of the internal current generating unit;
The grid electrode of the third NMOS tube is connected with the output end of the inverter, the drain electrode of the third NMOS tube is connected with the collector electrode and the base electrode of the nth NPN tube, and the source electrode of the third NMOS tube is connected with the emitter electrode of the nth NPN tube.
3. The over-temperature protection circuit of claim 2, wherein n is equal to 5.
4. An over-temperature protection circuit, comprising:
An internal power supply generating unit for supplying a first voltage as a voltage source;
an internal current generating unit for providing a rated current as a rated current source;
The voltage input end of the comparison judging unit is connected with the output end of the internal power supply generating unit, and the current input end of the comparison judging unit is connected with the output end of the internal current generating unit; the comparison judging unit is used for generating a corresponding output signal according to the temperature, so as to realize the output of an enabled digital signal;
The circuit also comprises a hysteresis conversion unit, wherein the hysteresis conversion unit is positioned between the comparison judging unit and the digital signal output end of the circuit;
The comparison judging unit comprises a first NMOS tube, a second NMOS tube and m NPN tubes, wherein m is an integer more than 1;
The comparison judging unit further comprises a voltage dividing element, wherein the voltage dividing element is a resistor or a diode;
the drain electrode of the first NMOS tube is connected with the output end of the internal current generation unit, and the grid electrode of the first NMOS tube is connected with the output end of the internal power supply generation unit;
The collector electrode of the 1 st NPN tube is connected with the source electrode of the first NMOS tube;
The collector of the latter NPN tube in the m NPN tubes is connected with the emitter of the former NPN tube, and the respective collectors and base electrodes of the m NPN tubes are connected;
The first end of the voltage dividing element is connected with the emitter of the mth NPN tube;
The second NMOS tube is a depletion type NMOS tube, the drain electrode of the second NMOS tube is connected with the second end of the voltage dividing element, the grid electrode of the second NMOS tube is connected with the source electrode, and the source electrode of the second NMOS tube is grounded;
The internal power supply generating unit comprises a voltage reducing unit and a buffer, wherein the output end of the voltage reducing unit is connected with the input end of the buffer, and the internal power supply generating unit further comprises a first resistor and a second resistor which are connected with the output end of the buffer; the first resistor is connected with the second resistor, and a voltage division end between the first resistor and the second resistor is used as an output end of the internal power supply generating unit.
5. The over-temperature protection circuit of claim 4, wherein the hysteresis conversion unit comprises an inverter and a third NMOS transistor;
The input end of the inverter is connected with the output end of the internal current generating unit;
The grid electrode of the third NMOS tube is connected with the output end of the inverter, the drain electrode of the third NMOS tube is connected with the first end of the voltage dividing element, and the source electrode of the third NMOS tube is connected with the second end of the voltage dividing element.
6. An over-temperature protection circuit, comprising:
An internal power supply generating unit for supplying a first voltage as a voltage source;
an internal current generating unit for providing a rated current as a rated current source;
The voltage input end of the comparison judging unit is connected with the output end of the internal power supply generating unit, and the current input end of the comparison judging unit is connected with the output end of the internal current generating unit; the comparison judging unit is used for generating a corresponding output signal according to the temperature, so as to realize the output of an enabled digital signal;
The circuit also comprises a hysteresis conversion unit, wherein the hysteresis conversion unit is positioned between the comparison judging unit and the digital signal output end of the circuit;
the comparison judging unit comprises a first NMOS tube, a second NMOS tube and k diodes, wherein k is an integer more than 1;
The comparison judging unit further comprises a voltage dividing element, wherein the voltage dividing element is a resistor or a diode;
the drain electrode of the first NMOS tube is connected with the output end of the internal current generation unit, and the grid electrode of the first NMOS tube is connected with the output end of the internal power supply generation unit;
the anode of the 1 st diode is connected with the source electrode of the first NMOS tube;
The anode of the latter diode in the k diodes is connected with the cathode of the former diode;
the first end of the voltage dividing element is connected with the cathode of the kth diode;
The second NMOS tube is a depletion type NMOS tube, the drain electrode of the second NMOS tube is connected with the second end of the voltage dividing element, the grid electrode of the second NMOS tube is connected with the source electrode, and the source electrode of the second NMOS tube is grounded;
The internal power supply generating unit comprises a voltage reducing unit and a buffer, wherein the output end of the voltage reducing unit is connected with the input end of the buffer, and the internal power supply generating unit further comprises a first resistor and a second resistor which are connected with the output end of the buffer; the first resistor is connected with the second resistor, and a voltage division end between the first resistor and the second resistor is used as an output end of the internal power supply generating unit.
7. The overheat protection circuit of claim 1, 4 or 6, wherein a power input terminal of the internal power supply generating unit is connected to a high voltage power supply, and is used for converting the high voltage power supply into a low voltage power supply, and is used for providing the first voltage to the comparison judging unit, and a power output terminal of the internal power supply generating unit is used as a comparison voltage point of the comparison judging unit; the power input end of the internal current generating unit is connected with the high-voltage power supply, is used for converting the high-voltage power supply into a rated current power supply and is used for providing the rated current for the comparison and judgment unit.
CN201810937698.8A 2018-08-16 2018-08-16 Over-temperature protection circuit Active CN108879605B (en)

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CN112362180B (en) * 2020-10-15 2022-08-12 国网思极紫光(青岛)微电子科技有限公司 Temperature difference detection circuit for over-temperature protection

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CN102055167A (en) * 2009-10-28 2011-05-11 中国科学院微电子研究所 Process deviation influence resisting over-temperature protection circuit
CN104993454A (en) * 2015-06-29 2015-10-21 中国电子科技集团公司第五十八研究所 Over-temperature protection circuit
CN204790660U (en) * 2015-06-09 2015-11-18 厦门元顺微电子技术有限公司 Controllable temperature coefficient's circuit for generating a reference voltage
CN208923814U (en) * 2018-08-16 2019-05-31 厦门元顺微电子技术有限公司 Thermal-shutdown circuit

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5698887A (en) * 1995-04-26 1997-12-16 Rohm Co., Ltd. Semiconductor protection circuit
CN102055167A (en) * 2009-10-28 2011-05-11 中国科学院微电子研究所 Process deviation influence resisting over-temperature protection circuit
CN204790660U (en) * 2015-06-09 2015-11-18 厦门元顺微电子技术有限公司 Controllable temperature coefficient's circuit for generating a reference voltage
CN104993454A (en) * 2015-06-29 2015-10-21 中国电子科技集团公司第五十八研究所 Over-temperature protection circuit
CN208923814U (en) * 2018-08-16 2019-05-31 厦门元顺微电子技术有限公司 Thermal-shutdown circuit

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