CN108878614A - A kind of capacitor combined type DBR flip-chip and preparation method thereof - Google Patents
A kind of capacitor combined type DBR flip-chip and preparation method thereof Download PDFInfo
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- CN108878614A CN108878614A CN201810744377.6A CN201810744377A CN108878614A CN 108878614 A CN108878614 A CN 108878614A CN 201810744377 A CN201810744377 A CN 201810744377A CN 108878614 A CN108878614 A CN 108878614A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 65
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 262
- 239000002184 metal Substances 0.000 claims abstract description 262
- 239000000758 substrate Substances 0.000 claims abstract description 115
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 238000009413 insulation Methods 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 27
- 238000004519 manufacturing process Methods 0.000 claims description 20
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 14
- 239000010931 gold Substances 0.000 claims description 14
- 229910052737 gold Inorganic materials 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910001020 Au alloy Inorganic materials 0.000 claims description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910001297 Zn alloy Inorganic materials 0.000 claims description 3
- 239000011701 zinc Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000007788 roughening Methods 0.000 claims description 2
- 239000012141 concentrate Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 229910001635 magnesium fluoride Inorganic materials 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910002059 quaternary alloy Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 3
- ORUIBWPALBXDOA-UHFFFAOYSA-L magnesium fluoride Chemical compound [F-].[F-].[Mg+2] ORUIBWPALBXDOA-UHFFFAOYSA-L 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 241001025261 Neoraja caerulea Species 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000011900 installation process Methods 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Device Packages (AREA)
Abstract
The application discloses a kind of capacitor combined type DBR flip-chip and preparation method thereof, including：More metal layers form capacitor, so that chip has the IV state of linear component well, cause capacitive sensing to charge when i.e. electric current moment fills and has reverse charging voltage, therefore the voltage that LED chip itself receives is smaller, electric current is also smaller, so LED luminance will be slow variation, when electric current is sharp cut-off, capacitor will do it electric discharge, so that LED chip brightness is slowly varying until closing.In addition, being electrically connected between bonded layer and the first type semiconductor layer by third metal layer；The projection of third metal layer on conductive substrates surrounds the projection of the first metal layer and second metal layer.So that electric current is circulated by the surrounding of LED chip, electric current is more dispersed, no longer concentrates, and also reduces LED chip to the susceptibility of electric current.
Description
Technical field
The present invention relates to semiconductor devices manufacture technology field more particularly to a kind of capacitor combined type DBR flip-chip and
Its production method.
Background technique
With last century the nineties, the birth of first blue-ray LED, light emitting diode (Light emitting
Diode, abbreviation LED) technology has development at full speed, and so that LED chip is widely used in illumination, instruction, display and backlight etc.
In all kinds of occasions, especially blue chip emerges, so that manufacturing a kind of high-power, low energy consumption, service life long white-light illuminating light
Source becomes a reality.
With the optimization and improvement of growth technology, the internal quantum efficiency of LED chip can reach 80% or more, because
This improves the optical property of chip, more to be solved from external quantum efficiency, as far as possible raising light extraction efficiency.Mesh
The technology of preparing for improving light extraction efficiency of preceding mainstream is metallic mirror or the preparation of DBR, wherein through frequently with gold
Belonging to reflecting mirror has Al mirror and Ag mirror, as DBR (Distributed Bragg Reflector, i.e. Distributed Bragg Reflection
Mirror) preparation that the refractive index such as silica, titanium dioxide, tantalum pentoxide, aluminium nitride, silicon nitride are then commonly used is larger
Oxide or nitride material.
Since positive cartridge chip has metal electrode blocking and absorb to light out, there are also the thermal conductivities of Sapphire Substrate
Heat dissipation problem caused by rate (35W/ (mK)) is smaller, therefore for preparing powerful blue chip, using reverse installation process
Prepare especially suitable.
But quaternary system flip-chip in the prior art is very sensitive to curent change, and the brightness of LED chip is caused to become
Change larger.
Summary of the invention
In view of this, the present invention provides a kind of capacitor combined type DBR flip-chip and preparation method thereof, to solve existing skill
LED flip chip is easy to appear the larger problem of brightness change to current sense in art.
To achieve the above object, the present invention provides the following technical solutions：
A kind of capacitor combined type DBR flip-chip, including：
Conductive substrates, the conductive substrates include the first surface and second surface being oppositely arranged；
Positioned at the first electrode of the conductive substrates first surface；
Positioned at the bonded layer of the conductive substrates second surface；
Deviate from the first metal layer of the conductive substrates side positioned at the bonded layer；
Deviate from the second metal layer of the conductive substrates side positioned at the first metal layer；
Deviate from the epitaxial structure of the conductive substrates side positioned at the second metal layer, the epitaxial structure is along away from institute
Stating conductive substrates direction successively includes the first type semiconductor layer, active layer, the second type semiconductor layer；
Deviate from the second electrode on the conductive substrates surface positioned at the epitaxial structure；
Wherein, the second metal layer and the first metal layer insulation set, the projection tool in the conductive substrates
There is lap；
And it is electrically connected between the first metal layer and first type semiconductor layer by third metal layer；
Projection of the third metal layer in the conductive substrates surrounds the projection of the second metal layer.
Preferably, first medium layer is provided between the first metal layer and the second metal layer.
Preferably, second dielectric layer is provided between the second metal layer and the epitaxial structure.
It preferably, further include the 4th metal layer between the first metal layer and the second metal layer, the 4th gold medal
Belong to layer and the first metal layer and the equal insulation set of the second metal layer.
Preferably, the bonded layer is identical as the material of the first metal layer, the 4th metal layer, is gold；
The material of the second metal layer is the alloy of gold and zinc.
Preferably, transparency conducting layer is additionally provided on the surface of the first type semiconductor layer towards the conductive substrates.
Preferably, the conductive substrates are silicon substrate.
The present invention also provides a kind of capacitor combined type DBR flip-chip production methods, are formed for production above-mentioned any one
Capacitor combined type DBR flip-chip described in, the capacitor combined type DBR flip-chip production method include：
Temporary substrates are provided；
Epitaxial structure is formed, the epitaxial structure covers the temporary substrates, and the epitaxial structure includes that the first type is partly led
Body layer, active layer and the second type semiconductor layer；
Second metal layer is formed on the epitaxial structure, the second metal layer includes the first son positioned at intermediate region
Metal layer and surround the described first sub- metal layer, and the second sub- metal layer of the first sub- metal layer insulation set；
The second metal layer away from the epitaxial structure side formed the first metal layer, the first metal layer with
The first sub- metal layer insulation set, and cover the second metal layer；
Conductive substrates are provided；
Bonded layer is formed on a surface of the conductive substrates；
Bonded layer in the conductive substrates is bonded with the first metal layer；
Remove the temporary substrates；
First electrode is formed away from the surface of bonded layer in the conductive substrates, forms second on the epitaxial structure surface
Electrode.
It preferably, further include thick to epitaxial structure surface progress surface after the removal temporary substrates
Change processing.
It is preferably, described before the second metal layer forms the first metal layer away from the side of the epitaxial structure,
Further include：
The 4th metal layer, the 4th metal layer packet are formed away from the side of the epitaxial structure in the second metal layer
It includes positioned at the sub- metal layer of third of intermediate region and around the sub- metal layer of the third, and is set with the sub- metal layer insulation of the third
The 4th sub- metal layer set, wherein the 4th sub- metal layer and the sub- metal layer insulation set of the third, and described interim
Projection on substrate has lap, and the second sub- metal layer and the 4th sub- metal layer are in electrical contact.
Preferably, further include after the formation epitaxial structure：
Transparency conducting layer is formed on the epitaxial structure surface.
It can be seen via above technical scheme that capacitor combined type DBR flip-chip provided by the invention, including：Conductive liner
Bottom, positioned at the first electrode of conductive substrates first surface；And set gradually bonded layer, the first metal on conductive substrates
Layer, second metal layer, epitaxial structure and second electrode；Wherein, the second metal layer and the first metal layer insulation set,
There is lap namely the first metal layer and second metal layer to be capable of forming capacitor for projection in the conductive substrates, by
Capacitor is formed in more metal layers, so that chip has the IV state of linear component well, i.e., is led when electric current moment fills
It sends a telegraph and holds induction charging and have reverse charging voltage, therefore the voltage that LED chip itself receives is smaller, electric current is also smaller, so
LED luminance will be slow variation, and when electric current is sharp cut-off, capacitor will do it electric discharge, so that LED chip brightness is slowly varying
Until closing.
That is, due to the presence of capacitor so that LED no longer sensitive to the variation of electric current, so as to avoid LED chip because
There is biggish brightness change in curent change.
In addition, electrically being connected between the bonded layer and first type semiconductor layer by third metal layer in the present invention
It connects；Projection of the third metal layer in the conductive substrates surrounds the throwing of the first metal layer and the second metal layer
Shadow.So that electric current is circulated by the surrounding of LED chip, electric current is more dispersed, no longer concentrates, and also reduces LED chip to electric current
Susceptibility.
The present invention also provides a kind of capacitor combined type DBR flip-chip production methods, are used to form capacitor recited above
Combined type DBR flip-chip.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the structural schematic diagram of quaternary system flip-chip in the prior art；
Fig. 2 is a kind of structural schematic diagram of capacitor combined type DBR flip-chip provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of another capacitor combined type DBR flip-chip provided in an embodiment of the present invention；
Fig. 4 is a kind of capacitor combined type DBR flip-chip production method flow chart provided in an embodiment of the present invention；
Fig. 5-Figure 15 is each making step of capacitor combined type DBR flip-chip production method provided in an embodiment of the present invention
Corresponding process schematic representation.
Specific embodiment
Just as described in the background section, flip LED chips in the prior art are very sensitive to curent change, cause
The brightness change of LED chip is larger.
Inventors have found that the reason of above-mentioned phenomenon occur is, as shown in FIG. 1, FIG. 1 is quaternary system upside-down mounting cores in the prior art
The structural schematic diagram of piece；The quaternary system flip-chip includes：Si substrate 102, the back gold positioned at 102 1 surfaces of Si substrate
101, the bonded layer 103 positioned at 102 another surface of Si substrate, bonded layer 103 is bonded with specular layer 104, mirror-reflection
It is provided with deielectric-coating on layer 104, medium holes 105 are provided in deielectric-coating, GaP layer 106 and epitaxial layer are provided on deielectric-coating
107, electrode pad 108 is provided on epitaxial layer 107.
Wherein, since above-mentioned LED chip is vertical structure, and current direction is along the vertically direction of electrode pad 108, side
To single and concentration, it is easy to cause chip very sensitive for curent change around medium sky 105.
Based on this, the present invention provides a kind of capacitor combined type DBR flip-chip, including：
Conductive substrates, the conductive substrates include the first surface and second surface being oppositely arranged；
Positioned at the first electrode of the conductive substrates first surface；
Positioned at the bonded layer of the conductive substrates second surface；
Deviate from the first metal layer of the conductive substrates side positioned at the bonded layer；
Deviate from the second metal layer of the conductive substrates side positioned at the first metal layer；
Deviate from the epitaxial structure of the conductive substrates side positioned at the second metal layer, the epitaxial structure is along away from institute
Stating conductive substrates direction successively includes the first type semiconductor layer, active layer, the second type semiconductor layer；
Deviate from the second electrode on the conductive substrates surface positioned at the epitaxial structure；
Wherein, the second metal layer and the first metal layer insulation set, the projection tool in the conductive substrates
There is lap；
And it is electrically connected between the bonded layer and first type semiconductor layer by third metal layer；
Projection of the third metal layer in the conductive substrates surrounds the first metal layer and second metal
The projection of layer.
Capacitor combined type DBR flip-chip provided by the invention, including：Conductive substrates are located at conductive substrates first surface
First electrode；And set gradually bonded layer on conductive substrates, the first metal layer, second metal layer, epitaxial structure and
Second electrode；Wherein, the second metal layer and the first metal layer insulation set, the projection tool in the conductive substrates
There are lap namely the first metal layer and second metal layer to be capable of forming capacitor, since more metal layers form capacitor, so that
Chip has the IV state of linear component well, i.e., causes capacitive sensing to charge when electric current moment fills and have reverse charging
Voltage, therefore the voltage that LED chip itself receives is smaller, electric current is also smaller, so LED luminance will be slow variation, when electric current is prominent
So when cut-off, capacitor will do it electric discharge, so that LED chip brightness is slowly varying until closing.
That is, due to the presence of capacitor so that LED no longer sensitive to the variation of electric current, so as to avoid LED chip because
There is biggish brightness change in curent change.
In addition, electrically being connected between the bonded layer and first type semiconductor layer by third metal layer in the present invention
It connects；Projection of the third metal layer in the conductive substrates surrounds the throwing of the first metal layer and the second metal layer
Shadow.So that electric current is circulated by the surrounding of LED chip, electric current is more dispersed, no longer concentrates, and also reduces LED chip to electric current
Susceptibility.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Fig. 2 is referred to, Fig. 2 is a kind of structural representation of capacitor combined type DBR flip-chip provided in an embodiment of the present invention
Figure；The capacitor combined type DBR flip-chip includes：
Conductive substrates 210, conductive substrates 210 include the first surface and second surface being oppositely arranged；
Positioned at the first electrode 212 of 210 first surface of conductive substrates；
Positioned at the bonded layer 209 ' of 210 second surface of conductive substrates；
Deviate from the first metal layer 209 of 210 side of conductive substrates positioned at bonded layer 209 '；
Deviate from the second metal layer 205 of 210 side of conductive substrates positioned at the first metal layer 209；
Deviate from the epitaxial structure 202 of 210 side of conductive substrates positioned at second metal layer 205, epitaxial structure 202 is along away from leading
Electric 210 direction of substrate successively includes the first type semiconductor layer, active layer, the second type semiconductor layer；
Deviate from the second electrode 211 on conductive substrates surface positioned at epitaxial structure 202；
Wherein, 209 insulation set of second metal layer 205 and the first metal layer, the projection in conductive substrates 210 have weight
Folded part；
And it is electrically connected between the first metal layer 209 and the first type semiconductor layer by third metal layer 208；
Projection of the third metal layer 208 in conductive substrates 210 surrounds the projection of second metal layer 205.
The insulation set mode between the first metal layer 209 and second metal layer 205 is not limited in the embodiment of the present invention, it can
Choosing, first medium layer 2061 is provided between the first metal layer 209 and second metal layer 205.Is not limited in the present embodiment
The material of one dielectric layer 2061, optionally, first medium layer 2061 can be the insulation materials such as magnesium fluoride, silicon oxide or silicon nitride
Matter.
In addition, between second metal layer 205 and epitaxial structure 202 being also insulation set in the present embodiment, such as institute in Fig. 2
Show, second dielectric layer 204 is additionally provided between second metal layer 205 and epitaxial structure 202, does not also limit in the present embodiment
The material of second medium layer 204, optionally, second dielectric layer 204 can be the isolation materials such as magnesium fluoride, silicon oxide or silicon nitride,
More optional in the present embodiment, the second dielectric layer 204 is MgF2。
It should be noted that in the present embodiment without limitation to the thickness of each layer metal layer, it can be according to LED flip chip
The wavelength of the reflection of light and transmitting light is configured in real process.
Since third metal layer 208 is located at the surrounding of LED chip in the present embodiment, so that the first electricity of LED flip chip
Electric current between pole 212 and second electrode 211 passes through from the surrounding of LED flip chip, and makes electric current more dispersed, without collecting
In, LED chip is also reduced to a certain extent to the sensitivity of electric current.
The concrete kind of the first type semiconductor layer in epitaxial structure 202, the second type semiconductor layer is not limited in the present embodiment
Type, optionally, first type semiconductor layer can be n type semiconductor layer, corresponding, and second type semiconductor layer is p-type
Semiconductor layer；First type semiconductor layer may be p type semiconductor layer；Corresponding, second type semiconductor layer is N-type
Semiconductor layer.Optional in the present embodiment, first type semiconductor layer is p type semiconductor layer；It is corresponding, the second type half
Conductor layer is n type semiconductor layer.In other embodiments of the invention, in order to enable the electric current on p type semiconductor layer is expanded
Transparency conducting layer 203 can also be arranged, such as so that electric current is extended from surrounding in exhibition on p type semiconductor layer in the present embodiment
Shown in Fig. 2, the surface of the first type semiconductor layer towards conductive substrates 210 is additionally provided with transparency conducting layer 203.Transparency conducting layer
203 play the role of current expansion, do not limit the specific material of transparency conducting layer 203, optionally, transparency conducting layer in the present embodiment
203 can be ITO (tin indium oxide) or IZO (indium zinc oxide).
It should be noted that in the present embodiment without limitation to the material of each layer metal layer, as long as can be in LED upside-down mounting core
The metal that capacitor is formed inside piece can be used.It is contemplated that electric conductivity and work function, in the present embodiment optionally, key
It is identical as 209 material of the first metal layer to close layer 209 ', it is preferably to be golden, since gold is common metal in LED chip at present, and
The work function of gold is larger, and electric conductivity is preferable, and therefore, the material of metal layer can be preferably golden in the embodiment of the present invention.Separately
Outside, the material of second metal layer 205 can also be the alloy of gold and zinc in the present embodiment, not limit this in the present embodiment.
First electrode and second electrode can also preferably golden materials.
In addition, it is necessary to illustrate, the specific material of conductive substrates is not limited in the present embodiment, as long as can be by the first electricity
It realizes and is electrically connected between pole and third metal layer, form complete LED structure, it is optional in the present embodiment, it is described to lead
Electric substrate is silicon substrate.
Capacitor is formed between the first metal layer 209 and second metal layer 205 in the present embodiment, since the pole plate of capacitor has
The characteristic of slow-absorbing charge and release charge, can reduce LED chip to the sensitivity of electric current.
In another embodiment of the present invention, as shown in figure 3, it is compound for another capacitor provided in an embodiment of the present invention
The structural schematic diagram of formula DBR flip-chip；Unlike the flip-chip in embodiment illustrated in fig. 2, described in the present embodiment
Capacitor combined type DBR flip-chip further includes the 4th metal layer 207 between the first metal layer 209 and second metal layer 205, the
Equal insulation set between four metal layers 207 and the first metal layer 209 and second metal layer 205, thus the 4th metal layer 207
First capacitor is formed between the first metal layer 209, while is also formed between the 4th metal layer 207 and second metal layer 205
Two capacitors.
Similarly, the insulation set side between the first metal layer 209 and the 4th metal layer 207 is not limited in the present embodiment yet
Formula is optionally provided with third dielectric layer 2062 between the first metal layer 209 and the 4th metal layer 207.It is unlimited in the present embodiment
Determine the material of third dielectric layer 2062, optionally, third dielectric layer 2062 can be the insulation such as magnesium fluoride, silicon oxide or silicon nitride
Material.
The material of the 4th metal layer is not limited in the present embodiment equally, optionally, the 4th metal layer material is gold.
The capacitor combined type DBR flip-chip provided in the present embodiment, including more metal layers, shape between more metal layers
At capacitor, so that flip-chip reduces the susceptibility of electric current.In addition, more metal layers are also used as DBR layer, thus
Improve the light extraction efficiency of flip-chip.Namely one layer of metal layer can be used as a pole plate of capacitor simultaneously in the embodiment of the present invention
And DBR layer, metal layer is multiplexed, capacitor combined type DBR flip-chip has been obtained.
The embodiment of the present invention also provides a kind of capacitor combined type DBR flip-chip production method, refers to Fig. 4, and Fig. 4 is this
A kind of capacitor combined type DBR flip-chip production method flow chart that inventive embodiments provide；It is shown in figure 15 each in conjunction with Fig. 5-
The capacitor combined type DBR flip-chip production method is described in detail in the corresponding process schematic representation of making step, described
Production method includes：
S101：Temporary substrates are provided；
Do not limit the specific material of temporary substrates in the present embodiment, the temporary substrates be used only as in production epitaxial structure and
Therefore support when other subsequent metal-layer structures as long as the substrate that can be played a supporting role, can adopt in the present embodiment
With.
S102：Epitaxial structure is formed, the epitaxial structure covers the temporary substrates, and the epitaxial structure includes the first type
Semiconductor layer, active layer and the second type semiconductor layer；
As shown in figure 5, forming epitaxial structure 202 on a surface of temporary substrates 201.
It should be noted that can also be made on epitaxial structure 202 for capacitor combined type DBR flip-chip shown in Fig. 3
Current extending 203 is formed, current extending 203 is transparency conducting layer, and optionally, the material of current extending 203 is ITO
Or IZO.
S103：Second metal layer is formed on the epitaxial structure, the second metal layer includes being located at intermediate region
First sub- metal layer and surround the described first sub- metal layer, and the second sub- metal layer of the first sub- metal layer insulation set；
Fig. 7 and Fig. 8 are referred to, forms second metal layer on epitaxial structure 202, since the second metal layer is used for shape
Forming second metal layer at capacitor, in the present embodiment further includes before forming dielectric layer 204, and the present embodiment dielectric layer 204 can
To be MgF2Material.It should be noted that the metal layer being subsequently formed also needs and epitaxial structure 202 and transparency conducting layer 203
Between form Ohmic contact, therefore, in the present embodiment by evaporation process formed flood dielectric layer after, then pass through figure chemical industry
Skill is patterned dielectric layer, so that its dielectric layer for only retaining intermediate region, the electrically conducting transparent in exposure edge region
Layer 203.
Then second metal layer is re-formed, it should be noted that second metal layer described in the present embodiment and device junction
Second metal layer in structure embodiment not fully corresponds to, and second metal layer includes positioned at the first of intermediate region in the present embodiment
Sub- metal layer 205 and surround the first sub- metal layer 205, and the second sub- metal layer 208A of the first sub- 205 insulation set of metal layer.
Wherein the first sub- metal layer 205 forms the second metal layer 205 in LED flip chip, and the second sub- metal layer 208A forms LED
A part of third metal layer 208 in flip-chip.
The size of the first sub- metal layer 205 is not limited in the present embodiment, as long as can be with the metal layer that is subsequently formed
Form capacitor.The material and thickness of second metal layer are not limited in the present embodiment, material is chosen as gold, and thickness is according to reality yet
Border demand is configured.
The method that second metal layer is formed in the present embodiment can be the second metal layer that first vapor deposition forms flood, then lead to
Patterning process is crossed, the second metal layer between intermediate region and fringe region is removed, to form the first sub- metal layer 205
With the second sub- metal layer 208A.
S104：The first metal layer, first gold medal are formed away from the side of the epitaxial structure in the second metal layer
Belong to layer and the described first sub- metal layer insulation set, and covers the second metal layer；
It should be noted that being illustrated by taking structure shown in Fig. 3 as an example in the present embodiment, namely forming the first metal
Before layer, it is also necessary to be initially formed the 4th metal layer 207.
Specifically, the process for forming the 4th metal layer 207 includes：
The 4th metal layer, the 4th metal layer packet are formed away from the side of the epitaxial structure in the second metal layer
It includes positioned at the sub- metal layer of third of intermediate region and around the sub- metal layer of the third, and is set with the sub- metal layer insulation of the third
The 4th sub- metal layer set, wherein the 4th sub- metal layer and the sub- metal layer insulation set of the third, and described interim
Projection on substrate has lap, and the second sub- metal layer and the 4th sub- metal layer are in electrical contact；
Fig. 9 and Figure 10 are referred to, dielectric layer 2061 is initially formed in second metal layer, then re-forms the 4th gold medal of flood
Belong to layer, the 4th metal layer is patterned, form the sub- metal layer 207 of third for being located at intermediate region and surrounds third interest category
Layer 207, and the 4th sub- metal layer 208B with sub- 207 insulation set of metal layer of third.
It should be noted that the 4th metal layer described in the present embodiment and the 4th metal layer in device architecture embodiment
It not fully corresponds to, the 4th metal layer in the present embodiment includes third to form the 4th metal layer 207 in LED flip chip
Metal layer 207, and form the 4th sub- metal layer 208B of third metal layer 208 in LED flip chip.
In conjunction with Figure 10, the second sub- sub- metal layer 208B of metal layer 208A and the 4th ultimately forms LED upside-down mounting in the present embodiment
Third metal layer 208 in chip.
In the present embodiment, as is illustrated by figs. 11 and 12, first is formed away from the side of temporary substrates 201 in the 4th metal layer
Metal layer 209, the first metal layer 209 and sub- 207 insulation set of metal layer of third, it is in electrical contact with the 4th sub- metal layer 208B.
When forming the first metal layer 209, due to insulation set between the first metal layer 209 and the sub- metal layer 207 of third, composition electricity
Hold, it is optional in the present embodiment, dielectric layer 2062 is first formed on the sub- metal layer 207 of third, described in the dielectric layer only covers
The sub- metal layer 207 of third, and the 4th sub- metal layer 208B in exposed edge region, so that subsequent 4th sub- metal layer 208B
With other metal layer Ohmic contacts.
S105：Conductive substrates are provided；
The material of conductive substrates is not limited in the present embodiment, optionally, the conductive substrates are silicon substrate.
S106：Bonded layer is formed on a surface of the conductive substrates；
Referring to Figure 13, in order to which conductive substrates are pressed with the half-finished semiconductor products formed, this implementation
Vapor deposition forms bonded layer 209 ' in conductive substrates 210 in example, and bonded layer 209 ' is used to conductive substrates 210 being bonded to the first gold medal
Belong on layer 209.When due to bonding, two surfaces for needing to be bonded are smooth and the identical structure of material can be bonded to
Function, therefore there are also planarizations to act on for the first metal layer 209 in the present embodiment, optionally, the first metal layer 209 and bonded layer 209 '
It is golden material.
S107：Bonded layer in the conductive substrates is bonded with the first metal layer；
As shown in figure 14, the bonded layer 209 ' in conductive substrates 210 is bonded with the structure sheaf on temporary substrates.Nothing
By structure shown in Fig. 2 or structure shown in Fig. 3, the structure outermost layer on temporary substrates described in the present embodiment is the first gold medal
Belong to layer 209, is then bonded the first metal layer 209 with bonded layer 209 '.
It should be noted that it is flat surface that bonded layer 209 ', which in realizing bonding process, needs bonding surface,.Therefore,
Further include the steps that planarizing the surface that the first metal layer 209 deviates from temporary substrates 201 in the present embodiment.
S108：Remove the temporary substrates；
Referring to Figure 15, after being bonded conductive substrates 210, due to the supporting role of conductive substrates 210, will can temporarily it serve as a contrast
Remove at bottom 201.The concrete technology for removing temporary substrates 201 is not limited in the present embodiment.
S109：First electrode is formed away from the surface of bonded layer in the conductive substrates, in epitaxial structure surface shape
At second electrode.
Finally, conductive substrates 210 are clean away from the surface clean of bonded layer 209 ', and by the table of epitaxial structure 202
Face cleans up, and then is deposited to form one layer of metal layer on the surface of conductive substrates 210, first electrode is formed, in epitaxial structure
202 surface evaporation metal forms second electrode.Final structure is shown in Figure 3.
LED chip light emission direction is direction up and down in the present embodiment, and wherein LED active layer issues downward
Light is reflected by the more metal layers of lower section, is emitted from the upper surface of LED chip.In order to prevent in the upper table of LED chip
Face is totally reflected, and reduces the light emission rate of LED chip, optional in the present embodiment, after removing temporary substrates 201, is also wrapped
It includes and surface roughening treatment is carried out to 202 surface of epitaxial structure being exposed, optionally, by chemical solution to epitaxial structure
202 surface is roughened.
The capacitor combined type DBR flip-chip production method provided in the present embodiment, is used to form capacitor combined type DBR and falls
Cartridge chip, since more metal layers form capacitor, so that chip has the IV state of linear component well, i.e. electric current moment
Cause capacitive sensing to charge when filling and have reverse charging voltage, therefore the voltage that LED chip itself receives is smaller, electric current also compared with
Small, so LED luminance will be slow variation, when electric current is sharp cut-off, capacitor will do it electric discharge, so that LED chip brightness
It is slowly varying until close.That is, due to the presence of capacitor, so that LED no longer sensitive to the variation of electric current, so as to avoid
LED chip is because biggish brightness change occurs in curent change.
It should be noted that all the embodiments in this specification are described in a progressive manner, each embodiment weight
Point explanation is the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
It should also be noted that, herein, relational terms such as first and second and the like are used merely to one
Entity or operation are distinguished with another entity or operation, without necessarily requiring or implying between these entities or operation
There are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to contain
Lid non-exclusive inclusion, so that article or equipment including a series of elements not only include those elements, but also
It including other elements that are not explicitly listed, or further include for this article or the intrinsic element of equipment.Do not having
In the case where more limitations, the element that is limited by sentence "including a ...", it is not excluded that in the article including above-mentioned element
Or there is also other identical elements in equipment.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (11)
1. a kind of capacitor combined type DBR flip-chip, which is characterized in that including：
Conductive substrates, the conductive substrates include the first surface and second surface being oppositely arranged；
Positioned at the first electrode of the conductive substrates first surface；
Positioned at the bonded layer of the conductive substrates second surface；
Deviate from the first metal layer of the conductive substrates side positioned at the bonded layer；
Deviate from the second metal layer of the conductive substrates side positioned at the first metal layer；
Deviate from the epitaxial structure of the conductive substrates side positioned at the second metal layer, the epitaxial structure is led along away from described
Electric substrate direction successively includes the first type semiconductor layer, active layer, the second type semiconductor layer；
Deviate from the second electrode on the conductive substrates surface positioned at the epitaxial structure；
Wherein, the second metal layer and the first metal layer insulation set, the projection in the conductive substrates have weight
Folded part；
And it is electrically connected between the first metal layer and first type semiconductor layer by third metal layer；
Projection of the third metal layer in the conductive substrates surrounds the projection of the second metal layer.
2. capacitor combined type DBR flip-chip according to claim 1, which is characterized in that the first metal layer and institute
It states and is provided with first medium layer between second metal layer.
3. capacitor combined type DBR flip-chip according to claim 2, which is characterized in that the second metal layer and institute
It states and is provided with second dielectric layer between epitaxial structure.
4. capacitor combined type DBR flip-chip according to claim 3, which is characterized in that the first metal layer and institute
Stating further includes the 4th metal layer between second metal layer layer, the 4th metal layer and the first metal layer and second gold medal
Belong to the equal insulation set of layer.
5. capacitor combined type DBR flip-chip according to claim 4, which is characterized in that the bonded layer and described the
One metal layer, the material of the 4th metal layer are identical, are gold；
The material of the second metal layer is the alloy of gold and zinc.
6. capacitor combined type DBR flip-chip according to claim 1, which is characterized in that in the first type semiconductor
Layer is additionally provided with transparency conducting layer towards the surface of the conductive substrates.
7. capacitor combined type DBR flip-chip described in -6 any one according to claim 1, which is characterized in that the conduction
Substrate is silicon substrate.
8. a kind of capacitor combined type DBR flip-chip production method, which is characterized in that form claim 1-7 for making
Capacitor combined type DBR flip-chip described in meaning one, the capacitor combined type DBR flip-chip production method include：
Temporary substrates are provided；
Form epitaxial structure, the epitaxial structure covers the temporary substrates, the epitaxial structure include the first type semiconductor layer,
Active layer and the second type semiconductor layer；
Second metal layer is formed on the epitaxial structure, the second metal layer includes the first interest category positioned at intermediate region
Layer and surround the described first sub- metal layer, and the second sub- metal layer of the first sub- metal layer insulation set；
The second metal layer away from the epitaxial structure side formed the first metal layer, the first metal layer with it is described
First sub- metal layer insulation set, and cover the second metal layer；
Conductive substrates are provided；
Bonded layer is formed on a surface of the conductive substrates；
Bonded layer in the conductive substrates is bonded with the first metal layer；
Remove the temporary substrates；
First electrode is formed away from the surface of bonded layer in the conductive substrates, forms the second electricity on the epitaxial structure surface
Pole.
9. capacitor combined type DBR flip-chip production method according to claim 8, which is characterized in that in the removal
It further include that surface roughening treatment is carried out to the epitaxial structure surface after the temporary substrates.
10. capacitor combined type DBR flip-chip production method according to claim 8, which is characterized in that described described
Before second metal layer forms the first metal layer away from the side of the epitaxial structure, further include：
The 4th metal layer is formed away from the side of the epitaxial structure in the second metal layer, the 4th metal layer includes position
The sub- metal layer of third in intermediate region and surround the sub- metal layer of the third, and with the sub- metal layer insulation set of the third
4th sub- metal layer, wherein the 4th sub- metal layer and the sub- metal layer insulation set of the third, and in the temporary substrates
On projection have lap, the second sub- metal layer and the 4th sub- metal layer are in electrical contact.
11. capacitor combined type DBR flip-chip production method according to claim 8, which is characterized in that in the formation
Further include after epitaxial structure：
Transparency conducting layer is formed on the epitaxial structure surface.
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| US20130032847A1 (en) * | 2011-08-04 | 2013-02-07 | Bridgelux, Inc. | Distributed current blocking structures for light emitting diodes |
| CN203218308U (en) * | 2013-03-14 | 2013-09-25 | 天津三安光电有限公司 | Light-Emitting Diode LED chip |
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| EP3131130A1 (en) * | 2015-08-13 | 2017-02-15 | Lextar Electronics Corp. | Semiconductor light emitting structure |
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| US20130032847A1 (en) * | 2011-08-04 | 2013-02-07 | Bridgelux, Inc. | Distributed current blocking structures for light emitting diodes |
| CN203218308U (en) * | 2013-03-14 | 2013-09-25 | 天津三安光电有限公司 | Light-Emitting Diode LED chip |
| CN105374916A (en) * | 2014-09-01 | 2016-03-02 | 山东浪潮华光光电子股份有限公司 | N-surface electrode-sinking reversed polarity AlGaInP light emitting diode chip |
| EP3131130A1 (en) * | 2015-08-13 | 2017-02-15 | Lextar Electronics Corp. | Semiconductor light emitting structure |
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