CN108832809A - It is a kind of for generating the DC-DC circuit of negative pressure - Google Patents

It is a kind of for generating the DC-DC circuit of negative pressure Download PDF

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Publication number
CN108832809A
CN108832809A CN201810723701.6A CN201810723701A CN108832809A CN 108832809 A CN108832809 A CN 108832809A CN 201810723701 A CN201810723701 A CN 201810723701A CN 108832809 A CN108832809 A CN 108832809A
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China
Prior art keywords
tube
connects
clock signal
pmos tube
module
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Withdrawn
Application number
CN201810723701.6A
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Chinese (zh)
Inventor
李泽宏
张成发
赵念
胡任任
庞仁江
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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Priority to CN201810723701.6A priority Critical patent/CN108832809A/en
Publication of CN108832809A publication Critical patent/CN108832809A/en
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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/071—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps adapted to generate a negative voltage output from a positive voltage source
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H02M3/075—Charge pumps of the Schenkel-type including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

It is a kind of for generating the DC-DC circuit of negative pressure, belong to electronic circuit technology field.Clock signal is generated under the control of enable signal including oscillator module, drive module, non-overlapping clock generation module and switching capacity module, oscillator module；Drive module generates inverting clock signal according to clock signal, and clock signal and inverting clock signal by the just non-overlapping clock generating unit in non-overlapping clock generation module and bear the switching tube in non-overlapping clock generating unit control switch capacitance module respectively；Switching capacity module generates negative voltage using the electric charge transfer of capacitor, and negative voltage feeds back to drive module adjustment inverting clock signal, the negative voltage that a successive step of going forward side by side generates；Can also guarantee negative voltage in some embodiments using clamper module and output module stablizes output.The present invention has the characteristics that output is reliable and stable, the response time is short and low in energy consumption, solves the problems, such as that the moment of electrifying startup is easy to cause circuit malfunction locked.

Description

It is a kind of for generating the DC-DC circuit of negative pressure
Technical field
The invention belongs to electronic circuit technology fields, are related to a kind of for generating the DC-DC circuit of negative pressure.
Background technique
During the utilization of integrated circuit, it usually needs different voltage, and the input voltage of circuit is usually single Be perhaps limited therefore positive input voltage just needed to be converted in circuit design different forward voltage or The circuit of negative voltage.For example, being also required to provide negative power supply in power supply design in a portable device.
Currently, the method for generating negative voltage has very much, but the DC-DC circuit that tradition generates negative pressure is mostly more complicated, And power consumption is higher, and output voltage is unstable, especially in the moment of circuit electrifying startup, negative voltage generating circuit is easy to cause to fail It is locked.
Summary of the invention
For it is above-mentioned tradition generate negative pressure DC-DC circuit existing for structure is complicated, output voltage is unstable, power consumption it is high with And in the problem that the moment of circuit electrifying startup is easy to cause circuit malfunction locked, the present invention proposes a kind of DC-DC circuit, is used for Negative voltage is generated, generate negative voltage using switching capacity module 50 and ensure that negative voltage is defeated by feeding back to drive module 30 Reliability out accelerates the response time of circuit simultaneously, is also protected by clamper module 10 and output module 60 in some embodiments That has demonstrate,proved negative voltage VDDN stablizes output.
The technical scheme is that：
It is a kind of for generating the DC-DC circuit of negative pressure, including oscillator module 20, drive module 30, non-overlapping clock produce Raw module 40 and switching capacity module 50,
The enable end of the oscillator module 20 connects enable signal EN, and power end connects supply voltage VDD, ground connection End connection ground voltage VSS, output end export clock signal clk；
The input terminal of the drive module 30 connects the clock signal clk, and output end exports inverting clock signal CLK_N；
The non-overlapping clock generation module 40 is including just non-overlapping clock generating unit and bears non-overlapping clock generation list Member, the input terminal of the just non-overlapping clock generating unit connect the clock signal clk, output end output each other reverse phase and The just non-overlapping clock signal clk _ P2 of the just non-overlapping clock signal clk _ P1 and second of non-overlapping first；It is described when bearing non-overlapping The input terminal that clock generates unit connects the inverting clock signal CLK_N, output end output reverse phase and non-overlapping each other The one negative non-overlapping negative non-overlapping clock signal clk _ N2 of clock signal clk _ N1 and second；
The switching capacity module 50 includes first capacitor C1, the second capacitor C2, first switch tube S1, second switch S2, third switching tube S3 and the 4th switching tube S4,
One end of first switch tube S1 connects supply voltage VDD, and the other end connects one end and first of second switch S2 One end of capacitor C1, control signal are described first just non-overlapping clock signal clk _ P1；
The other end of second switch S2 connects one end of the second capacitor C2 and connects ground voltage VSS, and control signal is Described second just non-overlapping clock signal clk _ P2；
One end of third switching tube S3 connects ground voltage VSS, and the other end connects one end and the first electricity of the 4th switching tube S4 Hold the other end of C1, control signal is described first negative non-overlapping clock signal clk _ N1；
The other end of 4th switching tube S4 connects the other end of the second capacitor C2 and exports negative voltage VDDN as the DC- The output signal of DC circuit, control signal are described second negative non-overlapping clock signal clk _ N2；
The negative voltage VDDN is used to adjust the negative voltage VDDN as the feedback signal of the drive module 30.
Specifically, the drive module 30 includes the first NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3, the Four NMOS tube MN4, the 5th NMOS tube MN5 and the first PMOS tube MP1,
The grid of 5th NMOS tube MN5 connects the grid of the first PMOS tube MP1 and third NMOS tube MN3 and as the drive The input terminal of dynamic model block 30, the drain electrode of the first PMOS tube MP1 of drain electrode connection and the grid of the 4th NMOS tube MN4, source electrode connect Ground voltage VSS；
The source electrode of first PMOS tube MP1 connects supply voltage VDD；
The grid of first NMOS tube MN1 connects the drain electrode of the second NMOS tube MN2 and source electrode and the conduct of third NMOS tube MN3 The output end of the drive module 30, the grid of the second NMOS tube MN2 of drain electrode connection and the source electrode of the 4th NMOS tube MN4, Source electrode connects the source electrode of the second NMOS tube MN2 and connects the negative voltage VDDN；
The drain electrode of third NMOS tube MN3 and the 4th NMOS tube MN4 connect ground voltage VSS.
Specifically, the negative voltage VDDN will also just be used as the DC-DC after clamper module 10 and output module 60 The output signal of circuit；
The clamper module 10 includes the second PMOS tube MP2, third PMOS tube MP3, the 4th PMOS tube MP4, the 5th PMOS Pipe MP5, the 6th NMOS tube MN6 and the 7th NMOS tube MN7,
The grid of third PMOS tube MP3 connects the enable signal EN, drain electrode connection the 4th PMOS tube MP4 and the 6th The drain electrode of the grid of NMOS tube MN6 and the 5th PMOS tube MP5 and the 7th NMOS tube MN7 and as the defeated of the clamper module 10 Outlet, source electrode connect the source electrode of the second PMOS tube MP2, the 4th PMOS tube MP4 and the 5th PMOS tube MP5 and connect supply voltage VDD；
The grid of second PMOS tube MP2 connects the inversion signal EN_N of the enable signal EN, drain electrode connection the 4th The drain electrode of PMOS tube MP4 and the 6th NMOS tube MN6 and the grid of the 5th PMOS tube MP5 and the 7th NMOS tube MN7；
The source electrode of 6th NMOS tube MN6 and the 7th NMOS tube MN7 connects the negative voltage VDDN；
The output module 60 includes the 6th PMOS tube MP6 and the 8th NMOS tube MN8,
The grid of 6th PMOS tube MP6 connects the grid of the 8th NMOS tube MN8 and connects the output of the clamper module 10 End, source electrode connect ground voltage VSS, the drain electrode of the 8th NMOS tube MN8 of drain electrode connection and the output for exporting the DC-DC circuit Signal；
The source electrode of 8th NMOS tube MN8 connects the negative voltage VDDN.
Specifically, the first switch tube S1 includes the 7th PMOS tube MP7, the second switch S2 includes the 8th PMOS Pipe MP8, the third switching tube S3 include the 9th PMOS tube MP9, and the 4th switching tube S4 includes the tenth PMOS tube MP10；
The grid of 7th PMOS tube MP7 connects described first just non-overlapping clock signal clk _ P1, and source electrode connects power supply Voltage VDD, the source electrode of the 8th PMOS tube MP8 of drain electrode connection；
The grid of 8th PMOS tube MP8 connects described second just non-overlapping clock signal clk _ P2, drain electrode connection ground electricity Press VSS；
The grid of 9th PMOS tube MP9 connects the first negative non-overlapping clock signal clk _ N1, source electrode connection ground electricity Press VSS, the source electrode of the tenth PMOS tube MP10 of drain electrode connection；
The grid of tenth PMOS tube MP10 connects the second negative non-overlapping clock signal clk _ N2, drains described in output Negative voltage VDDN；
First capacitor C1 connects between the 8th PMOS tube MP8 and the source electrode of the tenth PMOS tube MP10, and the second capacitor C2 connects Between 8th PMOS tube MP8 and the drain electrode of the tenth PMOS tube MP10.
Beneficial effects of the present invention are：The present invention passes through positive feedback using the negative voltage VDDN that switching capacity module 50 generates It ensure that the reliability of the negative voltage VDDN of output to drive module 30, while having also speeded up the response time of circuit, Yi Xieshi Applying in example ensure that negative voltage VDDN's stablizes output by clamper module 10 and output module 60, solve traditional negative pressure DC-DC conversion circuit is complicated, output voltage is unstable, power consumption is high and is easy to cause circuit to lose in the moment of circuit electrifying startup The locked problem of effect.
Detailed description of the invention
Fig. 1 is that a kind of a kind of circuit for generating the DC-DC circuit of negative pressure proposed by the present invention realizes structural schematic diagram.
Fig. 2 is proposed by the present invention a kind of for generating the operation timing schematic diagram of the DC-DC circuit of negative pressure.
Specific embodiment
In the following with reference to the drawings and specific embodiments, the technical schemes of the invention are described in detail.
It is proposed by the present invention a kind of for generating the DC-DC circuit of negative pressure, including oscillator module 20, drive module 30, Non-overlapping clock generation module 40 and switching capacity module 50, the enable end of oscillator module 20 connect enable signal EN, electricity Source connects supply voltage VDD, and ground terminal connects ground voltage VSS, and output end exports clock signal clk；Enable signal EN Oscillator is opened when enable signal EN is 0 for the enable signal that outside is given, output is effective；When enable signal EN is 1, Oscillator is closed, output circuit resets.When circuit is started to work, enabled first to using enable signal EN, so that oscillator mould Block 20 generates clock signal clk, and clock signal clk is that amplitude is ground voltage VSS to the square-wave signal of supply voltage VDD, is used for As the input signal of just non-overlapping clock generating unit, also as the input signal of drive module 30 for generating inversion clock Signal CLK_N, inverting clock signal CLK_N are the inversion signal of clock signal clk, clock signal clk and inversion clock letter Number CLK_N by the just non-overlapping clock generating unit in non-overlapping clock generation module 40 and bears non-overlapping clock and generates respectively Switching tube in unit control switch capacitance module 50.
The input terminal of drive module 30 connects clock signal clk, and output end exports inverting clock signal CLK_N；Switch The negative voltage VDDN that capacitance module 50 generates is negative for adjusting as the feedback signal back meeting drive module 30 of drive module 30 Voltage VDDN accelerates the response time of circuit while ensure that the reliability of negative voltage VDDN output.It provides as shown in Figure 1 A kind of circuit of drive module 30 realizes structure, including the first NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3, The grid of 4th NMOS tube MN4, the 5th NMOS tube MN5 and the first PMOS tube MP1, the 5th NMOS tube MN5 connect the first PMOS tube The grid of MP1 and third NMOS tube MN3 and input terminal as drive module 30, the leakage of the first PMOS tube MP1 of drain electrode connection The grid of pole and the 4th NMOS tube MN4, source electrode connect ground voltage VSS；The source electrode of first PMOS tube MP1 connects supply voltage VDD；The grid of first NMOS tube MN1 connects the drain electrode of the second NMOS tube MN2 and the source electrode of third NMOS tube MN3 and as driving The output end of module 30, the grid of the second NMOS tube MN2 of drain electrode connection and the source electrode of the 4th NMOS tube MN4, source electrode connection The source electrode of second NMOS tube MN2 simultaneously connects negative voltage VDDN；The drain electrode of third NMOS tube MN3 and the 4th NMOS tube MN4 connect ground Voltage VSS.Negative voltage VDDN is connected to the source electrode of the first NMOS tube MN1 and the 2nd NMSO pipe MN2 by feedback control loop, guarantees anti- The output amplitude of clock signal CLK_N is further adjusted to the square wave that-VDD arrives VSS.
Non-overlapping clock generation module 40 includes just non-overlapping clock generating unit and bears non-overlapping clock generating unit, just The input terminal of non-overlapping clock generating unit connects clock signal clk, for generating reverse phase each other and non-overlapping first is just non- The overlapping just non-overlapping clock signal clk _ P2 of clock signal clk _ P1 and second；The input terminal for bearing non-overlapping clock generating unit connects Reversed clock signal CLK_N, for generating reverse phase each other and non-overlapping first negative non-overlapping clock signal clk _ N1 and Two negative non-overlapping clock signal clk _ N2.
As shown in Figure 1, switching capacity module 50 is opened including first capacitor C1, the second capacitor C2, first switch tube S1, second The one end for closing pipe S2, third switching tube S3 and the 4th switching tube S4, first switch tube S1 connects supply voltage VDD, and the other end connects Connect one end of second switch S2 and one end of first capacitor C1, control signal be the first just non-overlapping clock signal clk _ P1；One end that the other end of second switch S2 connects the second capacitor C2 simultaneously connects ground voltage VSS, and control signal is second just Non-overlapping clock signal clk _ P2；One end of third switching tube S3 connects ground voltage VSS, and the other end connects the 4th switching tube S4's The other end of one end and first capacitor C1, control signal are first negative non-overlapping clock signal clk _ N1；4th switching tube S4 The other end connect the second capacitor C2 the other end and export output signal of the negative voltage VDDN as DC-DC circuit, control Signal is second negative non-overlapping clock signal clk _ N2.
Clock signal clk generates first just non-overlapping clock signal clk _ P1 and the by just non-overlapping clock generating unit Two just non-overlapping clock signal clk _ P2 are respectively used to control first switch tube S1 and second switch S2, inverting clock signal CLK_N generates the first negative non-overlapping negative non-overlapping clock of clock signal clk _ N1 and second by bearing non-overlapping clock generating unit Signal CLK_N2 is respectively used to control third switching tube S3 and the 4th switching tube S4, first switch tube S1 and third switching tube S3 and leads When logical, first capacitor C1 charges, when second switch S2 and the 4th switching tube S4 are connected, charge in first capacitor C1 to It is shifted on second capacitor C2, negative voltage VDDN is generated under the electric charge transfer of first capacitor C1, the second capacitor C2 output Negative voltage VDDN powers to drive module 30, as positive feedback loop.
Wherein first switch tube S1, second switch S2, third switching tube S3 and the 4th switching tube S4 can open for PMOS Pipe or NMOS switch pipe are closed, by taking PMOS switch pipe as an example, first switch tube S1 includes the 7th PMOS tube MP7, second switch S2 It include the 9th PMOS tube MP9 including the 8th PMOS tube MP8, third switching tube S3, the 4th switching tube S4 includes the tenth PMOS tube MP10；The grid of 7th PMOS tube MP7 connects first just non-overlapping clock signal clk _ P1, and source electrode connects supply voltage VDD, The source electrode of its 8th PMOS tube MP8 of connection that drains；The second just non-overlapping clock signal clk of grid connection of 8th PMOS tube MP8 _ P2, drain electrode connection ground voltage VSS；The grid of 9th PMOS tube MP9 connects first negative non-overlapping clock signal clk _ N1, source Pole connects ground voltage VSS, the source electrode of the tenth PMOS tube MP10 of drain electrode connection；The grid connection second of tenth PMOS tube MP10 is negative Non-overlapping clock signal clk _ N2, drain electrode output negative voltage VDDN；First capacitor C1 connects in the 8th PMOS tube MP8 and the tenth Between the source electrode of PMOS tube MP10, the second capacitor C2 is connect between the 8th PMOS tube MP8 and the drain electrode of the tenth PMOS tube MP10.
In order to which the output for guaranteeing negative voltage VDDN is more stable in some embodiments, negative voltage VDDN can be first passed through into clamper It is just exported as the output signal of DC-DC circuit after module 10 and output module 60, as shown in Figure 1, clamper module 1 includes second PMOS tube MP2, third PMOS tube MP3, the 4th PMOS tube MP4, the 5th PMOS tube MP5, the 6th NMOS tube MN6 and the 7th NMOS tube The grid of MN7, third PMOS tube MP3 connect enable signal EN, drain electrode connection the 4th PMOS tube MP4 and the 6th NMOS tube MN6 Grid and the 5th PMOS tube MP5 and the 7th NMOS tube MN7 drain electrode and output end as clamper module 10, source electrode connect It connects the source electrode of the second PMOS tube MP2, the 4th PMOS tube MP4 and the 5th PMOS tube MP5 and connects supply voltage VDD；2nd PMOS The inversion signal EN_N of the grid connection enable signal EN of pipe MP2, drain electrode the 4th PMOS tube MP4 of connection and the 6th NMOS tube The grid of the drain electrode of MN6 and the 5th PMOS tube MP5 and the 7th NMOS tube MN7；6th NMOS tube MN6 and the 7th NMOS tube MN7 Source electrode connect negative voltage VDDN.Output module 60 includes the 6th PMOS tube MP6 and the 8th NMOS tube MN8, the 6th PMOS tube MP6 Grid connect the grid of the 8th NMOS tube MN8 and connect the output end of clamper module 10, source electrode connects ground voltage VSS, The drain electrode of the 8th NMOS tube MN8 of drain electrode connection and the output signal for exporting DC-DC circuit；The source electrode of 8th NMOS tube MN8 connects Negative voltage VDDN.
At this time when enable signal EN is 0, output signal VOUT=VSS-V at this timeOP-VDD+2VOP-VOP=-VDD, In, VOPThe pressure drop between the drain-source of switching tube.
Be illustrated in figure 2 it is proposed by the present invention a kind of for generating the operation timing schematic diagram of the DC-DC circuit of negative pressure, Middle Δ t is dead time, and all switching tubes are in off state in the period.
In conclusion the invention proposes a kind of for generating the DC-DC circuit of negative pressure, solves traditional negative pressure DC- DC conversion circuit is complicated, output voltage is unstable and is easy to cause circuit malfunction is locked to ask in the moment of circuit electrifying startup Topic ensure that the negative voltage of output by the positive and negative drive module 30 that is fed to using the negative voltage VDDN that switching capacity module 50 generates The reliability of VDDN, while the response time of circuit has been also speeded up, pass through clamper module 10 and output module in some embodiments 60 ensure that negative voltage VDDN's stablizes output, and after the negative voltage VDDN being converted into, clamper module 10 and output mould Block 60 will export clamper output, at this time can save circuit power consumption to enable other modules are turned off.
It is understood that the present invention is not limited to the accurate configuration being illustrated above and components.Claims are not being departed from Protection scope on the basis of, can be to method as described above and structure the step of sequence, details and operation make various modifications and Optimization.

Claims (4)

1. a kind of for generating the DC-DC circuit of negative pressure, which is characterized in that including oscillator module (20), drive module (30), Non-overlapping clock generation module (40) and switching capacity module (50),
The enable end of the oscillator module (20) connects enable signal (EN), and power end connects supply voltage (VDD), connects Ground terminal connects ground voltage (VSS), and output end exports clock signal (CLK)；
The input terminal of the drive module (30) connects the clock signal (CLK), and output end exports inverting clock signal (CLK_N)；
The non-overlapping clock generation module (40) includes just non-overlapping clock generating unit and bears non-overlapping clock generating unit, The input terminal of the just non-overlapping clock generating unit connects the clock signal (CLK), output end output each other reverse phase and The just non-overlapping clock signal (CLK_P1) of non-overlapping first and the second just non-overlapping clock signal (CLK_P2)；It is described to bear non-friendship The input terminal of folded clock generating unit connects the inverting clock signal (CLK_N), and output end exports reverse phase and non-friendship each other The negative non-overlapping clock signal (CLK_N1) of folded first and the second negative non-overlapping clock signal (CLK_N2)；
The switching capacity module (50) includes first capacitor (C1), the second capacitor (C2), first switch tube (S1), second switch (S2), third switching tube (S3) and the 4th switching tube (S4) are managed,
One end of first switch tube (S1) connects supply voltage (VDD), and the other end connects the one end and the of second switch (S2) One end of one capacitor (C1), control signal are the described first just non-overlapping clock signal (CLK_P1)；
One end of the other end connection the second capacitor (C2) of second switch (S2) simultaneously connects ground voltage (VSS), controls signal For the described second just non-overlapping clock signal (CLK_P2)；
One end of third switching tube (S3) connects ground voltage (VSS), and the other end connects one end and first of the 4th switching tube (S4) The other end of capacitor (C1), control signal are the described first negative non-overlapping clock signal (CLK_N1)；
The other end of the other end connection the second capacitor (C2) of 4th switching tube (S4) simultaneously exports described in negative voltage (VDDN) conduct The output signal of DC-DC circuit, control signal are the described second negative non-overlapping clock signal (CLK_N2)；
The negative voltage (VDDN) is used to adjust the negative voltage (VDDN) as the feedback signal of the drive module (30).
2. according to claim 1 for generating the DC-DC circuit of negative pressure, which is characterized in that the drive module (30) Including the first NMOS tube (MN1), the second NMOS tube (MN2), third NMOS tube (MN3), the 4th NMOS tube (MN4), the 5th NMOS (MN5) and the first PMOS tube (MP1) are managed,
The grid of 5th NMOS tube (MN5) connects the grid of the first PMOS tube (MP1) and third NMOS tube (MN3) and as described The input terminal of drive module (30), the drain electrode of drain electrode connection the first PMOS tube (MP1) and the grid of the 4th NMOS tube (MN4), Its source electrode connects ground voltage (VSS)；
The source electrode of first PMOS tube (MP1) connects supply voltage (VDD)；
The drain electrode of the grid connection the second NMOS tube (MN2) of first NMOS tube (MN1) and the source electrode and work of third NMOS tube (MN3) For the output end of the drive module (30), the grid of drain electrode connection the second NMOS tube (MN2) and the 4th NMOS tube (MN4) Source electrode, the source electrode of source electrode connection the second NMOS tube (MN2) simultaneously connect the negative voltage (VDDN)；
Third NMOS tube (MN3) connects ground voltage (VSS) with the drain electrode of the 4th NMOS tube (MN4).
3. according to claim 1 or 2 for generating the DC-DC circuit of negative pressure, which is characterized in that the negative voltage (VDDN) will also after clamper module (10) and output module (60) the just output signal as the DC-DC circuit；
The clamper module (10) includes the second PMOS tube (MP2), third PMOS tube (MP3), the 4th PMOS tube (MP4), the 5th PMOS tube (MP5), the 6th NMOS tube (MN6) and the 7th NMOS tube (MN7),
The grid of third PMOS tube (MP3) connects the enable signal (EN), drain electrode connection the 4th PMOS tube (MP4) and the 6th The drain electrode of the grid of NMOS tube (MN6) and the 5th PMOS tube (MP5) and the 7th NMOS tube (MN7) and as the clamper module (10) output end, source electrode connect the source electrode of the second PMOS tube (MP2), the 4th PMOS tube (MP4) and the 5th PMOS tube (MP5) And connect supply voltage (VDD)；
The grid of second PMOS tube (MP2) connects the inversion signal (EN_N) of the enable signal (EN), drain electrode connection the 4th The drain electrode of PMOS tube (MP4) and the 6th NMOS tube (MN6) and the grid of the 5th PMOS tube (MP5) and the 7th NMOS tube (MN7)；
6th NMOS tube (MN6) connects the negative voltage (VDDN) with the source electrode of the 7th NMOS tube (MN7)；
The output module (60) includes the 6th PMOS tube (MP6) and the 8th NMOS tube (MN8),
The grid of 6th PMOS tube (MP6) connects the grid of the 8th NMOS tube (MN8) and connects the defeated of the clamper module (10) Outlet, source electrode connect ground voltage (VSS), and the drain electrode of drain electrode the 8th NMOS tube (MN8) of connection simultaneously exports the DC-DC circuit Output signal；
The source electrode of 8th NMOS tube (MN8) connects the negative voltage (VDDN).
4. according to claim 1 for generating the DC-DC circuit of negative pressure, which is characterized in that the first switch tube It (S1) include the 7th PMOS tube (MP7), the second switch (S2) includes the 8th PMOS tube (MP8), the third switching tube It (S3) include the 9th PMOS tube (MP9), the 4th switching tube (S4) includes the tenth PMOS tube (MP10)；
The grid of 7th PMOS tube (MP7) connects the described first just non-overlapping clock signal (CLK_P1), and source electrode connects power supply Voltage (VDD), the source electrode of drain electrode the 8th PMOS tube (MP8) of connection；
The grid of 8th PMOS tube (MP8) connects the described second just non-overlapping clock signal (CLK_P2), drain electrode connection ground electricity It presses (VSS)；
The grid of 9th PMOS tube (MP9) connects the first negative non-overlapping clock signal (CLK_N1), source electrode connection ground electricity It presses (VSS), the source electrode of drain electrode the tenth PMOS tube (MP10) of connection；
The grid of tenth PMOS tube (MP10) connects the second negative non-overlapping clock signal (CLK_N2), drains described in output Negative voltage (VDDN)；
First capacitor (C1) connects between the 8th PMOS tube (MP8) and the source electrode of the tenth PMOS tube (MP10), the second capacitor (C2) It connects between the 8th PMOS tube (MP8) and the drain electrode of the tenth PMOS tube (MP10).
CN201810723701.6A 2018-07-04 2018-07-04 It is a kind of for generating the DC-DC circuit of negative pressure Withdrawn CN108832809A (en)

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Application publication date: 20181116