CN108831876A - Filter chip is embedded and has the encapsulating structure and preparation method thereof of hole - Google Patents
Filter chip is embedded and has the encapsulating structure and preparation method thereof of hole Download PDFInfo
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- CN108831876A CN108831876A CN201810911108.4A CN201810911108A CN108831876A CN 108831876 A CN108831876 A CN 108831876A CN 201810911108 A CN201810911108 A CN 201810911108A CN 108831876 A CN108831876 A CN 108831876A
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- cofferdam
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- package substrate
- insulating layer
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- 239000000758 substrate Substances 0.000 claims abstract description 104
- 238000005538 encapsulation Methods 0.000 claims abstract description 11
- 230000003447 ipsilateral effect Effects 0.000 claims abstract description 8
- 238000004806 packaging method and process Methods 0.000 claims description 93
- 229910052751 metal Inorganic materials 0.000 claims description 34
- 239000002184 metal Substances 0.000 claims description 34
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000005253 cladding Methods 0.000 claims description 10
- 239000004744 fabric Substances 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 2
- 238000007747 plating Methods 0.000 claims description 2
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- 229920002120 photoresistant polymer Polymers 0.000 description 18
- 238000003384 imaging method Methods 0.000 description 10
- 230000006872 improvement Effects 0.000 description 10
- 238000000034 method Methods 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000001914 filtration Methods 0.000 description 5
- 125000004122 cyclic group Chemical group 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
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- 238000003199 nucleic acid amplification method Methods 0.000 description 3
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- 239000000126 substance Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229920006336 epoxy molding compound Polymers 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 238000010897 surface acoustic wave method Methods 0.000 description 2
- 229910018487 Ni—Cr Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
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- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Present invention discloses a kind of filter chip, encapsulating structure and preparation method thereof embedded and with hole, encapsulating structure include：Package substrate, with chamber；Filter chip is set in chamber, and the first upper surface and upper surface of base plate are located at ipsilateral, and the first upper surface has several first electrodes；Functional chip is set to the top of package substrate, and the second lower surface is arranged face-to-face with upper surface of base plate, and the second upper surface has several second electrodes；Several interconnection structures, by hole conducting first electrode and second electrode.The present invention utilizes encapsulation technology that in same package substrate, the highly integrated of multi-chip is may be implemented in two different chip packages；In being distributed up and down, the functional chip above package substrate and the space for being not take up package substrate can be improved package substrate utilization rate, simplify interconnection structure for filter chip and functional chip；Filter chip is embedded to be set in chamber, so that encapsulating structure is more frivolous.
Description
Technical field
The encapsulation knot embedded and with hole the present invention relates to field of semiconductor package more particularly to a kind of filter chip
Structure and preparation method thereof.
Background technique
To cater to the increasingly light and short development trend of electronic product, filter and radio-frequency transmissions component, receiving unit are needed
It is highly integrateable in the encapsulating structure of limited areal, forms system in package (SystemInPackage, SIP) structure, with
Reduce the size of hardware system.
For the filter and RF front-end module encapsulation integration technology in system-in-package structure, there are still suitable in the industry
More technical problem urgent need to resolve, for example, connection structure, multiple chips between the protection structure of filter, multiple chips
Layout etc..
Summary of the invention
Encapsulating structure and its production side embedded and with hole the purpose of the present invention is to provide a kind of filter chip
Method.
One of for achieving the above object, it is embedded and have hole to provide a kind of filter chip for an embodiment of the present invention
The encapsulating structure in hole, including：
Package substrate, has the upper surface of base plate and base lower surface being oppositely arranged, and the package substrate has chamber；
Filter chip is set in the chamber, the filter chip have the first upper surface for being oppositely arranged and
First lower surface, first upper surface and the upper surface of base plate are located at ipsilateral, and first upper surface has several the
One electrode；
Functional chip, is set to the top of the package substrate, and the functional chip has table on second be oppositely arranged
Face and the second lower surface, second lower surface are arranged face-to-face with the upper surface of base plate, and second upper surface has
Several second electrodes；
Several first electrodes and several second electrodes are connected by hole in several interconnection structures.
As the further improvement of an embodiment of the present invention, there are several outsides to draw for the side of the base lower surface
Foot, the package substrate have several through-holes, and the first electrode, described the is connected by the through-hole in the interconnection structure
Two electrodes and the external pin.
As the further improvement of an embodiment of the present invention, the through-hole and the second electrode are spaced apart from each other distribution.
As the further improvement of an embodiment of the present invention, the interconnection structure includes metal column and electroplated layer structure,
The second electrode is connected in the metal column, and the first electrode and the metal column is connected in the electroplated layer structure, and described
The external pin is connected by the lower section that the through-hole extends to the package substrate in electroplated layer structure.
As the further improvement of an embodiment of the present invention, the electroplated layer structure includes the upper rewiring of mutual conduction
Layer, intermediate wiring layer and lower rewiring layer, the upper rewiring layer are located at the top of the package substrate and are connected described first
Electrode and the second electrode, the lower rewiring layer are located at the lower section of the package substrate and the external pin are connected, institute
Stating intermediate wiring layer includes connected the first electroplated layer positioned at the upper surface of base plate, the second electricity positioned at the through-hole wall
Coating and third electroplated layer positioned at the base lower surface, wherein first electroplated layer connects the upper rewiring layer, institute
It states third electroplated layer and connects the lower rewiring layer.
As the further improvement of an embodiment of the present invention, the encapsulating structure include positioned at the upper surface of base plate,
First electroplated layer and institute is connected by the hole on first insulating layer in the first insulating layer above first upper surface
State rerouted on the first of first electrode layer, connect first insulating layer and second lower surface second insulating layer and
It is connected by the hole in the second insulating layer and reroutes layer on reroute layer on described first second, on described second
It reroutes layer and the metal column is connected.
As the further improvement of an embodiment of the present invention, first insulating layer and the second insulating layer cooperate shape
At cofferdam, the cofferdam and second lower surface, the first upper surface cooperate and enclose to set to form cavity, and the cofferdam includes being located at
The first cofferdam on the inside of several first electrodes and the second cofferdam on the outside of several first electrodes, first cofferdam with it is described
Second lower surface, first upper surface cooperate and enclose to set to form cavity, and second cofferdam is enclosed towards far from described first
The lateral border that the direction on weir extends up to second cofferdam is flushed with the lateral border of the package substrate, and second cofferdam
Expose the through-hole.
As the further improvement of an embodiment of the present invention, the encapsulating structure further includes remote positioned at the package substrate
The the first plastic packaging layer and top plastic packaging layer of side from the base lower surface, the first plastic packaging layer cladding second insulation
Layer is exposed to outer surface area, the functional chip and the metal column, and the first plastic packaging layer fills the through-hole, institute
It states rewiring layer on second and weight on described first is connected by the first plastic packaging layer and the hole in the second insulating layer
Wiring layer, the second rewiring layer extends to the upper surface of the first plastic packaging layer and the metal column is connected, and the top
Portion's plastic packaging layer coats and reroutes layer on the first plastic packaging layer and described second.
As the further improvement of an embodiment of the present invention, the encapsulating structure include coat the third electroplated layer and
The third insulating layer of base lower surface the third electroplated layer is connected by the hole on the third insulating layer and described in
The lower rewiring layer and coat the third insulating layer and the lower rewiring layer that the lower surface direction of third insulating layer extends
The 4th insulating layer, the external pin connects the lower rewiring layer, and external pin described in the 4th insulating layer exposing.
It is the gap of the filter chip and the chamber, described as the further improvement of an embodiment of the present invention
Base lower surface and first lower surface are provided with the second plastic packaging layer, and first upper surface and the upper surface of base plate are neat
It is flat.
One of for achieving the above object, it is embedded and have hole to provide a kind of filter chip for an embodiment of the present invention
The production method of the encapsulating structure in hole, including step：
S1：Package substrate is provided, there is the upper surface of base plate and base lower surface being oppositely arranged；
S2：In forming chamber on the package substrate；
S3：Filter chip is provided, the filter chip has the first upper surface and the first lower surface being oppositely arranged,
First upper surface has several first electrodes；
S4：The filter chip is loaded to the chamber, first upper surface is located at the upper surface of base plate
It is ipsilateral；
S5：In forming the first interconnection structure on the package substrate, the first electrode is connected in first interconnection structure；
S6：Functional chip is provided, the functional chip has the second upper surface and the second lower surface being oppositely arranged, and institute
The second upper surface is stated with several second electrodes；
S7：The functional chip is loaded into the top of the package substrate, on second lower surface and the substrate
Surface is arranged face-to-face, and forms the second mutually connection that the second electrode and first interconnection structure are connected by hole
Structure；
S8：Form the third interconnection structure of conducting external pin and first interconnection structure.
As the further improvement of an embodiment of the present invention, step S4 is specifically included：
One interim jointing plate is provided；
The upper surface of base plate of package substrate is fitted in into interim jointing plate；
The filter chip is loaded to the chamber, first upper surface and the upper surface of base plate are located at together
Side；
Form gap, the base lower surface and first lower surface for coating the filter chip and the chamber
The second plastic packaging layer；
Remove the interim jointing plate；
Invert the package substrate；
In forming several through-holes on the package substrate, the through-hole runs through the second plastic packaging layer；
Step S5 is specifically included：
The first electroplated layer is formed in upper surface of base plate, forms the second electroplated layer in through-hole wall, below the second plastic packaging layer
Form third electroplated layer；
The first insulating layer is laid in the upper surface of base plate；
It is formed in the top of first insulating layer and the first electrode is connected by the hole on first insulating layer
And layer is rerouted on the first of first electroplated layer；
The second insulation is laid in the top for rerouting layer and the protection zone on first insulating layer, described first
Layer, first insulating layer and the second insulating layer cooperatively form cofferdam, and the cofferdam includes the first cofferdam and the second cofferdam,
First cofferdam is located at the periphery of cavity, and the lateral border in second cofferdam is flushed with the lateral border of the package substrate, institute
It states the second cofferdam and exposes the through-hole；
Step S7, S8 is specifically included：
Metal column is formed in the top of the second electrode；
The functional chip is loaded into the top of the package substrate, second lower surface and the upper surface of base plate
Setting face-to-face, first cofferdam and second lower surface, first upper surface mutual cooperation and enclosing set to be formed it is corresponding
The cavity of the protection zone；
The first plastic packaging layer is formed far from the side of the base lower surface in the package substrate, the first plastic packaging layer is same
When coat second cofferdam and be exposed to outer surface area, the functional chip and the metal column, and first modeling
Sealing fills the through-hole；
It grinds the first plastic packaging layer and exposes the metal column；
The is connected in being formed on the first plastic packaging layer by the hole in the first plastic packaging layer and the second insulating layer
It is rerouted on one and reroutes layer on the second of layer, rerouted layer on described second and the second electrode is connected；
Top plastic packaging layer is formed in the top for rerouting layer on the first plastic packaging layer and described second；
Third insulating layer is formed in the lower section of the third electroplated layer and the second plastic packaging layer；
It is formed in the lower section of the third insulating layer and the third plating is connected by the hole on the third insulating layer
The lower rewiring layer of layer；
It is formed and coats the third insulating layer and lower the 4th insulating layer for rerouting layer, the 4th insulating layer exposing
The lower rewiring layer out；
Ball grid array is formed in being exposed to outer lower rewiring layer.
Compared with prior art, the beneficial effects of the present invention are：An embodiment of the present invention utilizes encapsulation technology by two
The highly integrated of multi-chip may be implemented in same package substrate in a different chip package, improves the utilization rate of package substrate,
And then realize the miniaturization of encapsulating structure；In addition, filter chip and functional chip are located above package substrate in distribution up and down
Functional chip and be not take up the space of package substrate, can be further improved the utilization rate of package substrate, and filter chip
And the spacing between functional chip becomes smaller, the interconnection being easy to implement between filter chip and functional chip, simplifies interconnection structure；
It is set in chamber moreover, filter chip is embedded, so that encapsulating structure is more frivolous.
Detailed description of the invention
Fig. 1 is an exemplary RF front-end module of the invention；
Fig. 2 is another exemplary RF front-end module of the present invention；
Fig. 3 is the cross-sectional view of the encapsulating structure of an embodiment of the present invention；
Fig. 4 is the cofferdam cooperation through-hole of an embodiment of the present invention and the schematic diagram of first electrode；
The step of Fig. 5 is the production method of the encapsulating structure of an embodiment of the present invention figure；
Fig. 6 a to Fig. 6 z-19 is the flow chart of the production method of the encapsulating structure of an embodiment of the present invention.
Specific embodiment
Below with reference to specific embodiment shown in the drawings, the present invention will be described in detail.But these embodiments are simultaneously
The present invention is not limited, structure that those skilled in the art are made according to these embodiments, method or functionally
Transformation is included within the scope of protection of the present invention.
In each diagram of the application, for the ease of illustration, structure or partial certain sizes can be relative to other knots
Structure or part are exaggerated, and therefore, are only used for the basic structure of the theme of diagram the application.
In addition, the term of the representation space relative position used herein such as "upper", " top ", "lower", " lower section " is
A unit as shown in the drawings or feature are described for the purpose convenient for explanation relative to another unit or feature
Relationship.The term of relative space position can be intended to include equipment in use or work other than orientation as shown in the figure not
Same orientation.For example, being described as being located at other units or feature " below " or " under " if the equipment in figure overturn
Unit will be located at other units or feature " top ".Therefore, exemplary term " lower section " can include above and below both
Orientation.Equipment can otherwise be directed (be rotated by 90 ° or other directions), and be interpreted accordingly it is used herein with it is empty
Between relevant description language.
Join Fig. 1 and Fig. 2, an embodiment of the present invention provides a kind of general RF front-end module, and RF front-end module can
For in the mobile devices such as mobile phone, computer either other electronic equipments.
In conjunction with Fig. 1, in one example, RF front-end module includes (the Power Amplifier of power amplifier module 200
Module, PAM), power amplifier module 200 includes the first amplifier unit 201 being successively electrically connected, the first RF switch list
Member 202 and the first RF filter cell 203, the first amplifier unit 201 are multi-mode-wide bandwidth Power Amplifier Unit.
In practical operation, the first amplifier unit 201 is used to receive the modulated signal of other component output, puts through overpower
Greatly after the modulation, amplification of device module 200 and filtering operation, exported by filter cell 203.
In conjunction with Fig. 2, in another example, RF front-end module includes receiving 300 (Receive of diversity module
Diversity Module, RDM), receiving diversity module 300 includes the low noise amplification multiplexer 301 being successively electrically connected
(LNA Multiplexer Module, LMM), the 2nd RF filter cell 302 and RF duplexer unit 303, wherein low noise
It includes the second amplifier unit 3011 and the 2nd RF switch unit 3012 being electrically connected, the second amplification that sound, which amplifies multiplexer 301,
Device unit 3011 is multi-mode-wide bandwidth low-noise amplifier unit, and the both ends of the 2nd RF switch unit 3012 are separately connected
Second amplifier unit 3011 and the 2nd RF filter cell 302.
In practical operation, signal divides by notch diplexer 304 to be believed here with high frequency for high-frequency signal and low frequency signal
For number, high-frequency signal enters RF duplexer unit 303, then successively passes through the 2nd RF filter cell 302 and low noise
It is exported after amplifying the filtering, modulation, amplifying operation of multiplexer 301 by the second amplifier unit 3011.
It should be understood that the electrical property between each units such as above-mentioned RF switch unit, filter cell, amplifier unit connects
Connecing can be realized by packaging technology, i.e., RF switch chip, amplifier chip, filter chip etc. are packaged together and realize
Various functions.
Present embodiment is said by taking RF switch chip, amplifier chip, the encapsulating structure of filter chip, technique as an example
It is bright.
Join Fig. 3, is the section view that the filter chip of an embodiment of the present invention embedded and had the encapsulating structure 100 of hole
Figure.
Encapsulating structure 100 includes package substrate 10, filter chip 20, functional chip 30 and several interconnection structures 50.
Package substrate 10 has the upper surface of base plate 11 and base lower surface 12 being oppositely arranged, and package substrate 10 has chamber
101。
Here, package substrate 10 is the loading plate for carrying chip, and package substrate 10 can be printing made of organic resin
Circuit board is also possible to glass substrate or ceramic substrate etc..
Chamber 101 can be the through hole through package substrate 10, and but not limited to this.
Filter chip 20 is set in chamber 101, filter chip 20 have the first upper surface 21 for being oppositely arranged and
First lower surface 22, the first upper surface 21 and upper surface of base plate 11 are located at ipsilateral, and the first upper surface 21 has several first electricity
Pole 211.
First electrode 211 protrudes out the first upper surface 21 towards the direction far from the first lower surface 22, and but not limited to this.
Filter chip 20 can be surface acoustic wave filter chip (Surface Acoustic Wave, SAW) or volume
Acoustic wave filter chip (Bulk Acoustic Wave, BAW), but not limited to this, the active region on 20 surface of filter chip
Domain (Active Zone) needs to work normally under the contact of no foreign object or coverage condition, that is to say, that needs are filtering
The lower section of device chip 20 forms a cavity to protect the active region.
Functional chip 30 is set to the top of package substrate 10, and functional chip 30 has the second upper surface 31 being oppositely arranged
And second lower surface 32, the second lower surface 32 are arranged face-to-face with upper surface of base plate 11, and the second upper surface 31 has several the
Two electrodes 311.
Second electrode 311 protrudes out the second upper surface 31 towards the direction far from the second lower surface 32, and but not limited to this.
Functional chip 30 is amplifier chip or RF switch chip, and but not limited to this.
Several first electrodes 211 and several second electrodes 311 are connected by hole in several interconnection structures 50.
Here, " several first electrodes 211 and several second electrodes 311 is connected by hole in several interconnection structures 50 " refers to
At least partly interconnection structure 50 realizes the electric connection between first electrode 211 and second electrode 311 by hole, that is, realizes
The interconnection of filter chip 20 and functional chip 30.
Present embodiment is encapsulated two different chips (filter chip 20 and functional chip 30) using encapsulation technology
In same package substrate 10, the highly integrated of multi-chip may be implemented, improve the utilization rate of package substrate 10, and then realize encapsulation
The miniaturization of structure 100.
In addition, filter chip 20 and functional chip 30 are distributed in upper and lower, the functional chip above package substrate 10
30 and be not take up the space of package substrate 10, can be further improved the utilization rate of package substrate 10, and filter chip 20 and
Spacing between functional chip 30 becomes smaller, the interconnection being easy to implement between filter chip 20 and functional chip 30, simplifies interconnection
Structure.
It is set in chamber 101 moreover, filter chip 20 is embedded, so that encapsulating structure 100 is more frivolous.
It should be noted that the encapsulating structure 100 of present embodiment is with a filter chip 20 and a functional chip
30 are loaded into for package substrate 10, it is possible to understand that, in practice, referring to Figure 1 and Figure 2, it may include multiple filtering
Device chip 20 and multiple functional chips 30, (including up and down all around three-dimensional) can for example, around filter chip 20
It is electrically connected with multiple functional chips 30 etc..
In the present embodiment, functional chip 30 is located at the top of chamber 101, several first electrodes 211 and several second
Electrode 311 is in face of back setting.
That is, filter chip 20 and about 30 functional chip are correspondingly arranged, first electrode 211 and the second electricity
Pole 311 is located at the opposite two sides of package substrate 10, in this way, the setting of filter chip 20 can't mistake in the horizontal direction
The spaces for occupying 10 horizontal direction of package substrate, the size of package substrate 10 can be done small more.
Here, the size of functional chip 30 is greater than the size of filter chip 20, and between functional chip 30 and chamber 101
To partly overlap.
That is, the outer profile of functional chip 30 is portion between the upright projection on package substrate 10 and chamber 101
Divide overlapping.
In the present embodiment, the side of package substrate 10 has several external pins 121, and interconnection structure 50 is for being connected
First electrode 211, second electrode 311 and external pin 121.
External pin 121 can be ball grid array (Ball Grid Array, BGA), pad etc., and encapsulating structure 100 is logical
Crossing external pin 121 can be electrically connected with realizations such as other chips or substrates, and here, external pin 121 is with ball grid array 121
For, external pin 121 protrudes out the lower surface of encapsulating structure 100.
In addition, but not limited to this, outside here by taking several external pins 121 are located at the side of base lower surface 12 as an example
Portion's pin 121 may be alternatively located at other regions.
Package substrate 10 has several through-holes 13, and the 211, second electricity of first electrode is connected by through-hole 13 in interconnection structure 50
Pole 311 and external pin 121.
In the present embodiment, through-hole 13 and second electrode 311 are spaced apart from each other distribution.
Here, through-hole 13 is located at the outside of second electrode 311, and through-hole 13 is located at the outside of chamber 101, at this point, being located at
The external pin 121 of 12 side of base lower surface can be towards shifting outside the two sides of functional chip 30, convenient for arranging other chips in advance
The space of embedment, consequently facilitating realizing that the multi-chip 2.5D or 3D of high-performance and small size stack integration packaging and mould group.
In the present embodiment, interconnection structure 50 includes metal column 51 and electroplated layer structure 53.
Second electrode 311 is connected in metal column 51, at this point, metal column 51 is set to the top of second electrode 311.
First electrode 211 and metal column 51 is connected in electroplated layer structure 53, and electroplated layer structure 53 is extended to by through-hole 13
The lower section of package substrate 10 and external pin 121 is connected.
Specifically, electroplated layer structure 53 includes the upper rewiring layer 531, intermediate wiring layer 532 and lower heavy cloth of mutual conduction
Line layer 533.
Upper rewiring layer 531 is located at the top of package substrate 10 and first electrode 211 and second electrode 311 is connected.
Intermediate wiring layer 532 is including being connected positioned at the first electroplated layer 5321 of upper surface of base plate 11, in through-hole 13
Second electroplated layer 5322 of wall and third electroplated layer 5323 positioned at base lower surface 12.
Layer 531 is rerouted in the connection of first electroplated layer 5321.
The width that the first electroplated layer 5321 of rewiring layer 531 extends to upper surface of base plate 11 in connection is substantially equal to correspondence
Third electroplated layer 5323 extend to the width of base lower surface 12.
Here, on the one hand, upper surface of base plate 11 and base lower surface 12 are provided with electroplated layer, can be improved electroplated layer with
The strong degree that package substrate 10 combines；On the other hand, the first electroplated layer 5321 extends towards 211 direction of first electrode, convenient for upper
It reroutes layer 531 and connects the first electroplated layer 5321, through-hole 13 can be towards shifting outside two sides, so that the outside of base lower surface 12
Pin 121 can move in addition.
Lower rewiring layer 533 is located at the lower section of package substrate 10 and external pin 121 is connected, and lower rewiring layer 533 connects
Connect third electroplated layer 5323.
Here, upper rewiring layer 531 includes rerouting to reroute layer 5312 on layer 5311 and second on first.
Specifically, encapsulating structure 100 includes the first insulating layer positioned at upper surface of base plate 11,21 top of the first upper surface
70, it is connected by the hole on the first insulating layer 70 and reroutes layer on the first of first electroplated layer 5321 and first electrode 211
5311, the second insulating layer 71 of the first insulating layer 70 and the second lower surface 32 is connected and by the hole in second insulating layer 71
And be connected and reroute layer 5312 on reroute layer 5311 on first second, layer 5312 is rerouted on second, and metal column 51 is connected.
Encapsulating structure 100 includes the third insulating layer 72 of cladding third electroplated layer 5323 and base lower surface 12, by the
The lower heavy cloth that the lower surface direction of hole conducting third electroplated layer 5323 and past third insulating layer 72 on three insulating layers 72 extends
Line layer 533 and cladding third insulating layer 72 and lower the 4th insulating layer 73 for rerouting layer 533, the lower weight of the connection of external pin 121
Wiring layer 533, and the 4th insulating layer 73 exposure external pin 121.
The lower setting for rerouting layer 533 can not only expand rewiring range, improve the laying of subsequent external pin 121 oneself
By spending, the outer shifting of acceptable further accessory external pin 121.
Metal column 51 is copper post, and upper rewiring layer 531, intermediate wiring layer 532 and lower rewiring layer 533 are layers of copper.
Present embodiment realizes first electrode 211, second electrode 311 and outer using succinct rewiring (RDL) scheme
Electric connection between portion's pin 121, process stabilizing and high reliablity.
The metal line materials of rewiring are that copper is (i.e. upper to reroute layer 531, intermediate wiring layer 532 and lower rewiring layer 533
For layers of copper), it reroutes and enhancing weight cloth can be set between copper and chip electrode (including first electrode 211 and second electrode 311)
Line copper and chip electrode are attached to each other the metal or alloy film of power, which can be nickel, titanium, nickel chromium triangle,
Titanium tungsten etc..
The first insulating layer 70, second is folded between package substrate 10, upper rewiring layer 531 and lower rewiring layer 533 absolutely
Edge layer 71 and third insulating layer 72, to realize the electrical isolation between all parts.
It should be understood that the upper rewiring layer 531 in rewiring scheme is not limited with above-mentioned two layers, lower rewiring layer
533 are not also limited with above-mentioned one layer, can according to the actual situation depending on.
In addition, the advantage for rerouting layer 5312 in present embodiment setting second is：Structure is simple, and it is difficult to reduce technique
Degree improves production efficiency.
In the present embodiment, the first insulating layer 70 and second insulating layer 71 cooperatively form cofferdam 40, cofferdam 40 and second
Lower surface 32, the first upper surface 21 cooperate and enclose to set to form cavity S, the active region on 20 surface of cavity S respective filter chip
Domain.
Present embodiment by setting cofferdam 40 formed cavity S, it is possible to prevente effectively from encapsulating structure manufacturing process or
It is that external substance enters the normal use for inside cavity S and influencing filter chip 20 in encapsulating structure use process, thus
Improve the overall performance of encapsulating structure 100.
In the present embodiment, cavity S is located at the inside of several first electrodes 211.
Cofferdam 40 includes positioned at the first cofferdam 41 of several 211 insides of first electrode and outside several first electrodes 211
Second cofferdam 42 of side, the first cofferdam 41 and the second lower surface 32 and the first upper surface 21 cooperate and enclose and set to form cavity S.
Here, the first cofferdam 41 is located at the inside of through-hole 13, and 42 part of the second cofferdam is located at 13 inside of through-hole, is partially located at
13 outside of through-hole.
Since cofferdam 40 has certain height, when the lower surface area when cofferdam 40 is too small, this may can not be supported
There is collapsing phenomenon so as to cause cofferdam 40 in the cofferdam 40 of height, and the cofferdam 40 of present embodiment includes the first cofferdam 41 and the
Two cofferdam 42, cofferdam 40 have sufficiently large lower surface, improve the stability in entire cofferdam 40；In addition, 40 lower surface of cofferdam
It can combine with the 20 upper surface whole region of filter chip outside the 20 upper surface region cavity S of filter chip, further mention
The forming stability of high cavity S.
In conjunction with Fig. 4, several through-holes 13 are in array distribution in upper surface of base plate 11, and have interval between adjacent through-holes 13,
There is a space between two column through-holes 13, chamber 101 is located in the space, and has interval between chamber 101 and through-hole 13, the
The interior zone of the corresponding chamber 101 in one cofferdam 41, and 41 essence of the first cofferdam is positioned at the inside of first electrode 211, second encloses
Weir 42 is extended by the interior zone of corresponding chamber 101 towards 13 direction of through-hole, and slots 43 positioned at the top in cofferdam 40, fluting 43
Positioned at the outside of functional chip 30.
In addition, the second cofferdam 42 extends up to lateral border and the encapsulation in the second cofferdam 42 towards the direction far from the first cofferdam 41
The lateral border of substrate 10 flushes, and the second cofferdam 42 exposes through-hole 13.
Certainly, since package substrate 10 is quadrilateral structure, lateral border further include package substrate 10 front side lateral margin and after
Side lateral margin, the second cofferdam 42 can also extend to front side lateral margin and rear side lateral margin together, and but not limited to this, and package substrate 10 can also
To be the structure of other shapes.
It should be noted that can be independent from each other between the first cofferdam 41 and the second cofferdam 42, such as the first cofferdam
41 be the first cyclic structure, and the first cyclic structure is located at the inside of several first electrodes 211, and the second cofferdam 42 is the second cyclic annular knot
Structure, the second cyclic structure are located at the outside of several first electrodes 211.
Certainly, be also possible between the first cofferdam 41 and the second cofferdam 42 it is interconnected, at this point, the first cofferdam 41 and
Interconnection is realized by third cofferdam 45 between two cofferdam 42, third cofferdam 45 is located at adjacent through-hole 13, adjacent first electrode
Between 211 or other regions, that is to say, that cofferdam 40 at this time is covered with 21 top of upper surface of base plate 11 and the first upper surface
Remove other whole regions in cavity S and 13 region of through-hole.
In the present embodiment, the second lower surface 32 of functional chip 30 covers the upper surface in the first cofferdam 41, and second
Lower surface 32 is Chong Die with the upper surface portion in the second cofferdam 42, and the first upper surface 21 and upper surface of base plate 11 cover first together and enclose
The lower surface in the lower surface on weir 41 and the second cofferdam 42.
Cofferdam 40 is made of the insulating materials of photaesthesia, and but not limited to this.
In the present embodiment, encapsulating structure 100 further includes the first plastic packaging layer 60 and top plastic packaging layer 62.
First plastic packaging layer 60 cladding second insulating layer 71 is exposed to outer surface area, and (i.e. the second cofferdam 42 is exposed to outer
Surface area), functional chip 30 and metal column 51, the first plastic packaging layer 60 fills through-hole 13, reroutes layer 5312 on second
Rewiring layer 5311 on first is connected by the hole in the first plastic packaging layer 60 and second insulating layer 71, second reroutes layer
5312 extend to the upper surface of the first plastic packaging layer 60 and metal column 51 are connected, and top plastic packaging layer 62 coat the first plastic packaging layer 60 and
Layer 5312 is rerouted on second.
Here, the first plastic packaging layer 60 exposes the upper surface of metal column 51, on the first plastic packaging layer 60 and second insulating layer 71
It is formed with fluting 43, fluting 43 exposes rewiring layer 5311 on first, and fluting 43 is skewed slot wide at the top and narrow at the bottom, weight cloth on second
Line layer 5312 is arranged along the inner wall of fluting 43 and extends to the upper surface of the first plastic packaging layer 60 and metal column 51 is connected.
First plastic packaging layer 60 and top plastic packaging layer 62 are respectively positioned on side of the package substrate 10 far from base lower surface 12.
That is, the first plastic packaging layer 60 is located inside top and the through-hole 13 in the second cofferdam 42 at this time, the first plastic packaging layer
All 13 interior zones of open area and through-hole around 60 cladding functional chips 30, and the cladding of top plastic packaging layer 62 is exposed to outside
The first plastic packaging layer 60 and second on reroute layer 5312.
First plastic packaging layer 60 and top plastic packaging layer 62 can be EMC (Epoxy Molding Compound) plastic packaging layer, by
External substance can be stopped to enter cavity S using cofferdam 40 in present embodiment, without considering the first plastic packaging layer 60 and top modeling
Whether sealing 62 can influence the protection zone in cavity S because of problem of materials, the first plastic packaging layer 60 and top plastic packaging layer
The range of choice of 62 materials expands significantly, and then can evade the selection of specific capsulation material, substantially widen plastic packaging making technology
It window and effectively reduces cost.
In the present embodiment, the first upper surface 21 of filter chip 20 is flushed with upper surface of base plate 11, moreover, filtering
Gap, base lower surface 12 and the first lower surface 22 of device chip 20 and chamber 101 are provided with the second plastic packaging layer 61.
That is, 5323 essence of third electroplated layer is to be located at the lower section of the second plastic packaging layer 61, and third insulating layer 72 is real
For matter also in the lower section of the second plastic packaging layer 61, other explanations of the second plastic packaging layer 61 can saying with reference to the first plastic packaging layer 60
Bright, details are not described herein.
Here, pass through the setting of the second plastic packaging layer 61, on the one hand, can with compensating filter chip 20 and package substrate 10 it
Between difference in thickness, to realize that the first upper surface 21 is flushed with upper surface of base plate 11, in order to subsequent first insulating layer 70, the
The isostructural molding of three insulating layer 72；On the other hand, the second plastic packaging layer 61 can play protecting filter chip 20 and fix
The effect of the relative position of filter chip 20 and chamber 101.
An embodiment of the present invention also provides a kind of production method of encapsulating structure 100, in conjunction with aforementioned encapsulation structure 100
Illustrate and Fig. 5, Fig. 6 a to Fig. 6 z-19, production method include step：
S1：Join Fig. 6 a, package substrate 10 is provided, there is the upper surface of base plate 11 and base lower surface 12 being oppositely arranged；
S2：Join Fig. 6 b, in formation chamber 101 on package substrate 10；
S3：Join Fig. 6 c, filter chip 20 is provided, filter chip 20 has the first upper surface 21 being oppositely arranged and the
A lower surface 22, the first upper surface 21 have several first electrodes 211；
S4：Join Fig. 6 d to Fig. 6 j, filter chip 20 is loaded to chamber 101, the first upper surface 21 and upper surface of base plate
11 positioned at ipsilateral；
Step S4 is specific as follows：
Join Fig. 6 d, an interim jointing plate 90 is provided；
Join Fig. 6 e, the upper surface of base plate 11 of package substrate 10 is fitted in into interim jointing plate 90；
Join Fig. 6 f, filter chip 20 is loaded to chamber 101, the first upper surface 21 is located at same with upper surface of base plate 11
Side；
Here, the first upper surface 21 also fits in interim jointing plate 90, so, it can be achieved that on the first upper surface 21 and substrate
Surface 11 flushes.
Join Fig. 6 g, forms gap, base lower surface 12 and the first lower surface 22 of cladding filter chip 20 and chamber 101
The second plastic packaging layer 61；
Join Fig. 6 h, removes interim jointing plate 90；
Join Fig. 6 i, inverts package substrate 10.
Join Fig. 6 j, in forming several through-holes 13 on package substrate 10, through-hole 13 runs through the second plastic packaging layer 61.
S5：Join Fig. 6 k to Fig. 6 v, in forming the first interconnection structure on package substrate 10, the first interconnection structure conducting first is electric
Pole 211；
Step S5 is specific as follows：
Join Fig. 6 k to Fig. 6 n, form the first electroplated layer 5321 in upper surface of base plate 11, forms the second electricity in 13 inner wall of through-hole
Coating 5322 forms third electroplated layer 5323 below the second plastic packaging layer 61；
It is specific as follows：
Join Fig. 6 k, is respectively formed beneath the first photoresist layer 81 in the top of upper surface of base plate 11 and the second plastic packaging layer 61
And second photoresist layer 82；
Join Fig. 6 l, forms the first aperture 811 in 81 exposure and imaging of the first photoresist layer, the first aperture 811 exposes logical
Hole 13 and upper surface of base plate 11 form the second aperture 821, the second aperture 821 exposure in 82 exposure and imaging of the second photoresist layer
Through-hole 13 and the second plastic packaging layer 61 out；
Join Fig. 6 m, forms the first electroplated layer 5321 in being exposed to outer upper surface of base plate 11, the through-hole 13 outside being exposed to
Inner wall forms the second electroplated layer 5322, forms third electroplated layer 5323 in being exposed to the second outer plastic packaging layer 61；
Join Fig. 6 n, removes the first photoresist layer 81 and the second photoresist layer 82.
Join Fig. 6 o, lays the first insulating layer 70 in upper surface of base plate 11；
Join Fig. 6 p to Fig. 6 t, is formed in the top of the first insulating layer 70 by the hole conducting first on the first insulating layer 70
Layer 5311 is rerouted on the first of electrode 211 and the first electroplated layer 5321；
It is specific as follows：
Join Fig. 6 p, forms the first hole 701 in 70 exposure and imaging of the first insulating layer, the first hole 701 exposes first
Electrode 211, through-hole 13, the first electroplated layer 5321 and protection zone, protection zone are located at the first upper surface 21, and protection zone position
In the inside of several first electrodes 211；
Join Fig. 6 q, forms third photoresist layer 83 in the top of the first insulating layer 70；
Join Fig. 6 r, forms third aperture 831 in 83 exposure and imaging of third photoresist layer, third aperture 831 exposes the
One electrode 211, the first electroplated layer 5321 and the first insulating layer 70；
Join Fig. 6 s, reroutes layer 5311 on first in being formed in third aperture 831；
Join Fig. 6 t, removes third photoresist layer 83.
Join Fig. 6 u and Fig. 6 v, lays the in the top for rerouting layer 5311 and protection zone on the first insulating layer 70, first
Two insulating layers 71, the first insulating layer 70 and second insulating layer 71 cooperatively form cofferdam 40, and cofferdam 40 includes the first cofferdam 41 and the
Two cofferdam 42, the first cofferdam 41 are located at the periphery of cavity S, and the lateral border of the lateral border and package substrate 10 in the second cofferdam 42 is neat
Flat, the second cofferdam 42 exposes through-hole 13；
It is specific as follows：
Join Fig. 6 u, lays the second insulation in the top for rerouting layer 5311 and protection zone on the first insulating layer 70, first
Layer 71；
Join Fig. 6 v, forms the second hole 711 in 71 exposure and imaging of second insulating layer, the second hole 711 exposes through-hole
13 and protection zone, the first insulating layer 70 and second insulating layer 71 cooperatively form cofferdam 40, cofferdam 40 include the first cofferdam 41 and
Second cofferdam 42, the first cofferdam 41 are located at the periphery of protection zone, the lateral border in the second cofferdam 42 and the outside of package substrate 10
Edge flushes, and the second cofferdam 42 exposes through-hole 13.
It should be noted that cofferdam 40 may include the third cofferdam 45 for connecting the first cofferdam 41 and the second cofferdam 42,
That is removing the other surfaces region outside corresponding cavity S and 13 region of through-hole in upper surface of base plate 11 at this time is respectively formed cofferdam
40。
In addition, formed since independent package substrate 10 can be divided by the large substrates of wafer scale, it, can when forming cofferdam 40
With the multiple cofferdam 40 of straight forming on large substrates, the segmentation of large substrates is then carried out again and obtains the list with single cofferdam 40
A package substrate 10, in this way, being greatly improved packaging efficiency, certainly, cofferdam 40 is also plastic on functional chip 30.
S6：Join Fig. 6 w, functional chip 30 is provided, functional chip 30 has under the second upper surface 31 and second being oppositely arranged
Surface 32, and the second upper surface 31 has several second electrodes 311；
S7：Join Fig. 6 x to Fig. 6 z-16, functional chip 30 be loaded into the top of package substrate 10, the second lower surface 32 with
Upper surface of base plate 11 is arranged face-to-face, and forms the second interconnection that second electrode 311 and the first interconnection structure are connected by hole
Structure；
S8：Join Fig. 6 z-17 to Fig. 6 z-19, the third for forming conducting external pin 121 and the first interconnection structure mutually links
Structure.
Step S7, S8 is specific as follows：
Join Fig. 6 x to Fig. 6 z-1, forms metal column 51 in the top of second electrode 311；
It is specific as follows：
Join Fig. 6 x, forms the 4th photoresist layer 84 in the second upper surface 31；
Join Fig. 6 y, forms the 4th aperture 841 in 84 exposure and imaging of the 4th photoresist layer, the 4th aperture 841 exposes the
Two electrodes 311；
Join Fig. 6 z, in formation metal column 51 in the 4th aperture 841；
Join Fig. 6 z-1, removes the 4th photoresist layer 84.
Join Fig. 6 z-2, functional chip 30 is loaded into the top of package substrate 10, the second lower surface 32 and upper surface of base plate
11 settings face-to-face, the first cofferdam 41 cooperate with the second lower surface 32, the first upper surface 21 and enclose to set to form corresponding protection
The cavity S in region.
Join Fig. 6 z-3, forms the first plastic packaging layer 60, the first plastic packaging far from the side of base lower surface 12 in package substrate 10
Layer 60 coats the second cofferdam 42 simultaneously and is exposed to outer surface area, functional chip 30 and metal column 51, and the first plastic packaging layer
60 filling through-holes 13；
Join Fig. 6 z-4, grinds the first plastic packaging layer 60 and expose metal column 51；
Join Fig. 6 z-5 to Fig. 6 z-9, passes through in the first plastic packaging layer 60 and second insulating layer 71 in being formed on the first plastic packaging layer 60
Hole and be connected and reroute layer 5312 on reroute layer 5311 on first second, reroute on second layer 5312 be connected it is described
Second electrode 311；
It is specific as follows：
Join Fig. 6 z-5, is rerouted on first in forming recess 44 on the first plastic packaging layer 60 and second insulating layer 71 and exposing
Layer 5311；
Join Fig. 6 z-6, forms the 5th interim photoresist film 85 in the top of the first plastic packaging layer 60；
Join Fig. 6 z-7, forms the 5th aperture 851 in 85 exposure and imaging of the 5th photoresist layer, the 5th aperture 851 exposes
Recess 44, the first plastic packaging layer 60；
Join Fig. 6 z-8, formed along 44 inner wall of recess and reroute layer 5312 on second, and reroutes layer 5312 on second and extend
Second electrode 311 is connected to the top of the first plastic packaging layer 60；
Join Fig. 6 z-9, removes the 5th interim photoresist film 85.
Join Fig. 6 z-10, forms top plastic packaging layer 62 in the top for rerouting layer 5312 on the first plastic packaging layer 60 and second；
Join Fig. 6 z-11, forms third insulating layer 72 in the lower section of third electroplated layer 5323 and the second plastic packaging layer 61；
Join Fig. 6 z-12 to Fig. 6 z-16, is formed in the lower section of third insulating layer 72 and led by the hole on third insulating layer 72
The lower rewiring layer 533 of logical third electroplated layer 5323；
It is specific as follows：
Join Fig. 6 z-12, forms third hole 721 in 72 exposure and imaging of third insulating layer, third hole 721 exposes the
Three electroplated layers 5323；
Join Fig. 6 z-13, forms the 5th photoresist layer 85 in the lower section of third insulating layer 72；
Join Fig. 6 z-14, forms the 5th aperture 851 in 85 exposure and imaging of the 5th photoresist layer, the 5th aperture 851 exposes
Third hole 721 and third insulating layer 72；
Join Fig. 6 z-15, layer 533 is rerouted under being formed in the 5th aperture 851；
Join Fig. 6 z-16, removes the 5th photoresist layer 85.
Join Fig. 6 z-17 and Fig. 6 z-18, form cladding third insulating layer 72 and lower the 4th insulating layer 73 for rerouting layer 533,
4th insulating layer 73 exposes lower rewiring layer 533；
It is specific as follows：
Join Fig. 6 z-17, forms the 4th insulating layer 73 in the lower section of lower rewiring layer 533 and third insulating layer 72；
Join Fig. 6 z-18, the 4th hole 731 is formed in 73 exposure and imaging of the 4th insulating layer, under the 4th hole 731 exposes
Reroute layer 533.
Join Fig. 6 z-19, forms ball grid array 121 in being exposed to outer lower rewiring layer 533, i.e., in the 4th hole 731
Form ball grid array 121.
Other explanations of the production method of the encapsulating structure 100 of present embodiment can be with reference to above-mentioned encapsulating structure 100
Illustrate, details are not described herein.
Cofferdam 40 of the invention is located at the inside and outside of first electrode 211, and the lateral border in the second cofferdam 42 and encapsulation
The lateral border of substrate 10 flushes, and in other embodiments, cofferdam 40 may be alternatively located at the inside of first electrode 211, alternatively, second
The lateral border in cofferdam 42 is flushed with the lateral border of functional chip 30, or, the lateral border in the second cofferdam 42 is located at functional chip
Between 30 lateral border and the lateral border of package substrate 10 etc..
To sum up, present embodiment forms cavity S by setting cofferdam 40, it is possible to prevente effectively from encapsulating structure manufacturing process
In or external substance enters the normal use for inside cavity S and influencing filter chip 20 in encapsulating structure use process,
To improve the overall performance of encapsulating structure 100.
In addition, present embodiment utilizes encapsulation technology by two different chips (filter chip 20 and functional chip 30)
It is packaged in same package substrate 10, the highly integrated of multi-chip may be implemented, improves the utilization rate of package substrate 10, and then realize
The miniaturization of encapsulating structure 100.
It should be appreciated that although this specification is described in terms of embodiments, but not each embodiment only includes one
A independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should will say
As a whole, the technical solution in each embodiment may also be suitably combined to form those skilled in the art can for bright book
With the other embodiments of understanding.
The series of detailed descriptions listed above only for feasible embodiment of the invention specifically
Protection scope bright, that they are not intended to limit the invention, it is all without departing from equivalent implementations made by technical spirit of the present invention
Or change should all be included in the protection scope of the present invention.
Claims (12)
1. a kind of filter chip is embedded and has the encapsulating structure of hole, which is characterized in that including：
Package substrate, has the upper surface of base plate and base lower surface being oppositely arranged, and the package substrate has chamber；
Filter chip is set in the chamber, and the filter chip has the first upper surface and first being oppositely arranged
Lower surface, first upper surface and the upper surface of base plate are located at ipsilateral, and first upper surface has several first electricity
Pole；
Functional chip, is set to the top of the package substrate, the functional chip have the second upper surface being oppositely arranged and
Second lower surface, second lower surface are arranged face-to-face with the upper surface of base plate, and second upper surface is with several
Second electrode；
Several first electrodes and several second electrodes are connected by hole in several interconnection structures.
2. encapsulating structure according to claim 1, which is characterized in that the side of the base lower surface has several outsides
Pin, the package substrate have several through-holes, and the first electrode, described is connected by the through-hole in the interconnection structure
Second electrode and the external pin.
3. encapsulating structure according to claim 2, which is characterized in that the through-hole and the second electrode are spaced apart from each other point
Cloth.
4. encapsulating structure according to claim 2, which is characterized in that the interconnection structure includes metal column and electroplated layer knot
The second electrode is connected in structure, the metal column, and the first electrode and the metal column, and institute is connected in the electroplated layer structure
It states electroplated layer structure and the external pin is connected by the lower section that the through-hole extends to the package substrate.
5. encapsulating structure according to claim 4, which is characterized in that the electroplated layer structure includes the upper heavy of mutual conduction
Wiring layer, intermediate wiring layer and lower rewiring layer, the upper rewiring layer are located at described in top and the conducting of the package substrate
First electrode and the second electrode, the lower rewiring layer, which is located at the lower section of the package substrate and the outside is connected, to be drawn
Foot, the intermediate wiring layer include it is connected positioned at the first electroplated layer of the upper surface of base plate, positioned at the through-hole wall
Second electroplated layer and third electroplated layer positioned at the base lower surface, wherein first electroplated layer connects the upper heavy cloth
Line layer, the third electroplated layer connect the lower rewiring layer.
6. encapsulating structure according to claim 5, which is characterized in that the encapsulating structure includes being located at table on the substrate
First electroplated layer is connected by the hole on first insulating layer in the first insulating layer above face, the first upper surface
And layer is rerouted on the first of the first electrode, connects first insulating layer and the second insulation of second lower surface
It layer and is connected by the hole in the second insulating layer and reroutes layer on reroute layer on described first second, institute
It states and reroutes the layer conducting metal column on second.
7. encapsulating structure according to claim 6, which is characterized in that first insulating layer and the second insulating layer are matched
Conjunction forms cofferdam, and the cofferdam and second lower surface, the first upper surface cooperate and enclose to set to form cavity, and the cofferdam includes
The first cofferdam on the inside of several first electrodes and the second cofferdam on the outside of several first electrodes, first cofferdam with
Second lower surface, first upper surface cooperate and enclose to set to form cavity, and second cofferdam is towards far from described the
The lateral border that the direction in one cofferdam extends up to second cofferdam is flushed with the lateral border of the package substrate, and described second
Cofferdam exposes the through-hole.
8. encapsulating structure according to claim 6, which is characterized in that the encapsulating structure further includes being located at the encapsulation base
The the first plastic packaging layer and top plastic packaging layer of side of the plate far from the base lower surface, the first plastic packaging layer cladding described second
Surface area, the functional chip and the metal column of insulating layer exposing outside, the first plastic packaging layer filling are described logical
Hole reroutes layer on described second by the first plastic packaging layer and the hole in the second insulating layer and is connected described first
Upper rewiring layer, the second rewiring layer extends to the upper surface of the first plastic packaging layer and the metal column is connected, and institute
It states and reroutes layer on top plastic packaging layer cladding the first plastic packaging layer and described second.
9. encapsulating structure according to claim 5, which is characterized in that the encapsulating structure includes coating the third plating
The third electroplated layer and past is connected by the hole on the third insulating layer in the third insulating layer of layer and base lower surface
The lower rewiring layer and coat the third insulating layer and the lower heavy cloth that the lower surface direction of the third insulating layer extends
4th insulating layer of line layer, the external pin connect the lower rewiring layer, and external described in the 4th insulating layer exposing
Pin.
10. encapsulating structure according to claim 1, which is characterized in that the gap of the filter chip and the chamber,
The base lower surface and first lower surface are provided with the second plastic packaging layer, first upper surface and the upper surface of base plate
It flushes.
11. a kind of filter chip is embedded and has the production method of the encapsulating structure of hole, which is characterized in that including step：
S1：Package substrate is provided, there is the upper surface of base plate and base lower surface being oppositely arranged；
S2：In forming chamber on the package substrate；
S3：Filter chip is provided, the filter chip has the first upper surface and the first lower surface being oppositely arranged, described
First upper surface has several first electrodes；
S4：The filter chip is loaded to the chamber, first upper surface is located at ipsilateral with the upper surface of base plate；
S5：In forming the first interconnection structure on the package substrate, the first electrode is connected in first interconnection structure；
S6：There is provided functional chip, the functional chip has the second upper surface and the second lower surface that are oppositely arranged, and described the
Two upper surfaces have several second electrodes；
S7：The functional chip is loaded into the top of the package substrate, second lower surface and the upper surface of base plate
Setting face-to-face, and form the second interconnection structure that the second electrode and first interconnection structure are connected by hole；
S8：Form the third interconnection structure of conducting external pin and first interconnection structure.
12. the production method of encapsulating structure according to claim 11, which is characterized in that step S4 is specifically included：
One interim jointing plate is provided；
The upper surface of base plate of package substrate is fitted in into interim jointing plate；
The filter chip is loaded to the chamber, first upper surface is located at ipsilateral with the upper surface of base plate；
Form the of the gap for coating the filter chip and the chamber, the base lower surface and first lower surface
Two plastic packaging layers；
Remove the interim jointing plate；
Invert the package substrate；
In forming several through-holes on the package substrate, the through-hole runs through the second plastic packaging layer；
Step S5 is specifically included：
The first electroplated layer is formed in upper surface of base plate, forms the second electroplated layer in through-hole wall, is formed below the second plastic packaging layer
Third electroplated layer；
The first insulating layer is laid in the upper surface of base plate；
It is formed in the top of first insulating layer and the first electrode and institute is connected by the hole on first insulating layer
It states and reroutes layer on the first of the first electroplated layer；
Second insulating layer, institute are laid in the top for rerouting layer and the protection zone on first insulating layer, described first
It states the first insulating layer and the second insulating layer cooperatively forms cofferdam, the cofferdam includes the first cofferdam and the second cofferdam, described
First cofferdam is located at the periphery of cavity, and the lateral border in second cofferdam is flushed with the lateral border of the package substrate, and described
Two cofferdam expose the through-hole；
Step S7, S8 is specifically included：
Metal column is formed in the top of the second electrode；
The functional chip is loaded into the top of the package substrate, second lower surface is faced with the upper surface of base plate
Face setting, first cofferdam and second lower surface, first upper surface mutual cooperation and enclosing set to be formed it is corresponding described in
The cavity of protection zone；
The first plastic packaging layer is formed far from the side of the base lower surface in the package substrate, the first plastic packaging layer wraps simultaneously
It covers second cofferdam and is exposed to outer surface area, the functional chip and the metal column, and the first plastic packaging layer
Fill the through-hole；
It grinds the first plastic packaging layer and exposes the metal column；
It is connected on first in formation on the first plastic packaging layer by the hole on the first plastic packaging layer and the second insulating layer
It reroutes and reroutes layer on the second of layer, reroute layer on described second and the second electrode is connected；
Top plastic packaging layer is formed in the top for rerouting layer on the first plastic packaging layer and described second；
Third insulating layer is formed in the lower section of the third electroplated layer and the second plastic packaging layer；
It is formed in the lower section of the third insulating layer and the third electroplated layer is connected by the hole on the third insulating layer
Lower rewiring layer；
The 4th insulating layer for coating the third insulating layer and the lower rewiring layer is formed, the 4th insulating layer exposing goes out institute
State lower rewiring layer；
Ball grid array is formed in being exposed to outer lower rewiring layer.
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