CN108828529B

CN108828529B - Anti-irradiation wave control special integrated circuit

Info

Publication number: CN108828529B
Application number: CN201810662098.5A
Authority: CN
Inventors: 肖文光; 段玲琳; 段晓超; 黄翌; 李化雷; 宋云霞; 赵宁; 姚佰栋; 张宏财; 李艳华
Original assignee: CETC 38 Research Institute
Current assignee: CETC 38 Research Institute
Priority date: 2018-06-25
Filing date: 2018-06-25
Publication date: 2022-03-25
Anticipated expiration: 2038-06-25
Also published as: CN108828529A

Abstract

The invention discloses an anti-irradiation wave control special integrated circuit.A big data frame extraction module extracts data from a wave beam controller; the data validity detection module adopts a sum check mode for the data extracted by the big data frame extraction module, small data packet recombination is carried out if the check is correct, the data frame is discarded if the check is wrong, and a check error flag bit is recorded; the time sequence combination judging module is a logic combination of a transmitting control time sequence and a receiving control time sequence from the wave beam controller; the pulse width detection only detects the width of the emission control time sequence, if the width does not exceed the detection threshold, the emission control time sequence is output to the microwave component, if the width exceeds the detection threshold, the emission control time sequence is forcibly adjusted to be proper in width and then output, and the pulse width error zone bit is recorded. The miniaturization design of the wave control unit is facilitated; the method is easy to realize localization, and the supply of goods is guaranteed, while the supply of imported controllers, particularly aerospace-level controllers, is difficult to guarantee.

Description

Anti-irradiation wave control special integrated circuit

Technical Field

The invention relates to a beam control technology of a satellite-borne phased array radar, in particular to an anti-irradiation wave control special integrated circuit.

Background

The wave control unit is an important single machine of the satellite-borne phased array radar, on one hand, wave control data and working time sequence sent by the wave beam controller are received, the wave control data are verified, the working time sequence is detected and judged, and the verified and detected data are forwarded to a next microwave assembly without errors; and on the other hand, fault information sent by the antenna array surface microwave assembly is collected, and the fault information, the check error, the time sequence detection error, the A/D sampling data and the like are packaged and transmitted back to the beam controller.

When a single high-energy particle impacts a controller inside a wave control unit, a logical value of configuration data stored in a device is inverted from an original storage state '1' to '0', or from the original storage state '0' to '1', so that the level of a logic circuit is changed, and a program error or system function abnormity is caused, wherein the phenomenon is called a single-particle inversion effect. The high energy particles can also trigger the conduction of a silicon controlled structure in a CMOS circuit, a low-resistance large-current path is formed between a power supply and the ground, the power supply is overloaded until a device is failed and burnt out, and the phenomenon is called single event latch-up effect.

In a controller adopted by the existing design of a satellite-borne wave control unit, an SRAM type FPGA has rich internal resources and flexible design, but an internal RAM storage unit is very sensitive to a single event effect. After the anti-fuse FPGA is burned, the configuration storage bit cannot be modified, so that the configuration bit cannot be subjected to single event upset when in rail operation, but the RAM storage unit in the anti-fuse FPGA is not immune to the single event effect and still can be subjected to the single event upset when being subjected to strong particle incidence. An Application Specific Integrated Circuit (ASIC), which is simply called "ASIC", is a custom integrated circuit with completely solidified functions and internal logic, which can integrate a large number of logic circuits into a single chip, and is beneficial to device miniaturization and low power consumption design; on the other hand, a control kernel with a large number of programmable logic memory cells does not exist in the ASIC device, a special hardware protection process is adopted to meet the requirement of single event upset, the immunity to space radiation and single event upset effect is achieved, and the anti-radiation design requirement of the wave control unit internal controller can be better met.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: the reliability design problems of single event upset, single event latch and the like of an internal controller of a wave control unit of the existing satellite-borne phased array radar provide an anti-irradiation wave control special integrated circuit.

The invention solves the technical problems through the following technical scheme, and the invention comprises a wave control data forwarding module, a time sequence detection distribution module and a telemetering data returning module, wherein the wave control data forwarding module comprises a large data frame extraction module, a data validity detection module, a small data packet recombination and RS422 differential drive module which are sequentially connected, the time sequence detection distribution module comprises a time sequence combination judgment module and a pulse width detection module, and the telemetering data returning module comprises a feedback data frame module, an A/D converter and an RS422 differential receiving module;

the big data frame extraction module extracts data from the beam controller;

the data validity detection module adopts a sum check mode for the data extracted by the big data frame extraction module, small data packet recombination is carried out if the check is correct, the data frame is discarded if the check is wrong, and a check error flag bit is recorded;

the time sequence combination judging module is a logic combination of a transmitting control time sequence and a receiving control time sequence from the wave beam controller, the time sequence is output to the microwave assembly if the time sequence combination logic judges correctly, the time sequence combination logic judges wrongly and is forcibly converted into a safe state, and a time sequence combination error zone bit is recorded;

the pulse width detection only detects the width of the emission control time sequence, if the width does not exceed a detection threshold, the emission control time sequence is output to the microwave assembly, if the width exceeds the detection threshold, the emission control time sequence is forcibly adjusted to be proper in width and then output, and a pulse width error zone bit is recorded;

the RS422 differential drive module is used for sending the wave control data after the small data packet recombination to each microwave assembly;

the RS422 differential receiving module is used for receiving BIT fault information from the microwave assembly and then sending the BIT fault information to a feedback data frame;

the A/D converter converts the analog signal into a digital signal;

the feedback data frame module collects the sampling data of the A/D converter, the BIT information of the microwave assembly, the pulse width error, the time sequence combination error and the data verification error state information and sends the information to the beam controller.

The big data frame extraction module is responsible for receiving wave control data from the wave beam controller in a serial communication mode, and the baud rate is 10Mbps at most.

The detection threshold of the pulse width detection module is determined by a resistor and a capacitor connected outside the application specific integrated circuit.

The pulse width detection module only detects the transmission control time sequence width TR _ T, the detection threshold is determined by the time constants of a resistor R3 and a capacitor C2 which are connected with pins PW1 and PW2, if the detection threshold is not exceeded, the TR _ T is output, and if the detection threshold is exceeded, the transmission control time sequence is forcibly adjusted to be proper in width and then output, and a pulse width error flag bit is recorded.

The special integrated circuit is powered by direct current +5V, the A/D converter supports cyclic collection of 8 paths of differential analog signals, the analog signals are linearly quantized in a full-scale mode with +5V as 8bit, namely 0x00 represents 0V, and 0xFF represents + 5V.

The big Data frame extracted by the big Data frame extraction module comprises a frame header 0 xABB, a Data2 enabling output bit, 8T/R component control Data, control Data and check bits of 1 TTDL component, and the total number of the control Data and the check bits is 264 bits, wherein the control Data length of each T/R component is 24 bits, the control Data length of each TTDL component is also 24 bits, the frame header 0 xABB, the Data2 enabling output bit and 6 spare bits form 24 bits, and the check bits are 24 bits.

The data validity detection module adopts a sum check mode, namely the first 240 bit data is compared with check bits according to the result obtained by adding every 24 bits, if the result is equal, the check is correct, small data packets are immediately recombined according to 24bit sections and then sent to a T/R component and a TTDL component, if the result is not equal, the check is wrong, the data frame is discarded, and a check error flag bit is recorded.

The time sequence combination judging module is a logic combination of a transmitting control time sequence TR _ T and a receiving control time sequence TR _ R from a wave beam controller, the TR _ T and the TR _ R can not be simultaneously effective logically, a pin E _ T is used for setting the effective logic level of the TR _ T, a pin E _ R is used for setting the effective logic level of the TR _ R, if the pin E _ T and the pin E _ R are both connected to +5V, the time sequences TR _ T and TR _ R can not be simultaneously in a logic high level, if the TR _ T and TR _ R are detected to be simultaneously in a logic high level, then converting TR _ T and TR _ R into logic low level forcibly, and recording the time sequence combination error flag bit, if the time sequences TR _ T and TR _ R are logically combined without error, then the time sequence TR _ T continues to the next pulse width detection, and the time sequence TR _ R is forwarded to the pin TR _ R _1 and the pin TR _ R _2 at the same time and sent to the T/R component and the TTDL component.

Compared with the prior art, the invention has the following advantages: the invention has high reliability, and the special integrated circuit has no programmable logic memory cell therein, and has radiation resistance and single event upset effect immunity; the integration level is high, and a plurality of circuit modules such as a digital logic unit, an A/D converter, RS422 differential drive, RS422 differential receiving and the like are integrated in the special integrated circuit, so that the miniaturization design of a wave control unit is facilitated; the method is easy to realize localization, and the supply of goods is guaranteed, while the supply of imported controllers, particularly aerospace-level controllers, is difficult to guarantee; the cost is low, and compared with an expensive import controller, the cost of the special integrated circuit in batch production can be greatly reduced; the security is strong, and the special integrated circuit is equivalent to a black box and is difficult to imitate.

Drawings

FIG. 1 is a schematic block diagram of the circuit configuration of the present invention;

fig. 2 is a circuit diagram of the present invention.

Detailed Description

The following examples are given for the detailed implementation and specific operation of the present invention, but the scope of the present invention is not limited to the following examples.

As shown in fig. 1, the present embodiment includes a wave control data forwarding module, a timing detection distribution module, and a telemetry data return module, where the wave control data forwarding module includes a large data frame extraction module, a data validity detection module, a small data packet reassembly module, and an RS422 differential driving module, which are connected in sequence, the timing detection distribution module includes a timing combination judgment module and a pulse width detection module, and the telemetry data return module includes a feedback data frame module, an a/D converter, and an RS422 differential receiving module;

the big data frame extraction module extracts data from the beam controller;

the A/D converter converts the analog signal into a digital signal;

As shown in fig. 2, the asic of this embodiment is WB812, and is powered by dc + 5V. Pins G3, F1 are analog voltages, and pins N8, M8, H12, H13 are digital voltages, all connected to + 5V. The pins G4, F2, R7, P7, H14 and H15 are corresponding power grounds and are connected to a ground signal corresponding to + 5V.

The interface signals with the beam controller include a refresh control signal SX, a clock signal CLK, a write strobe signal WR, a remote control Data signal Data1, a read strobe signal RD, a telemetry Data signal Data2, a transmission control timing signal TR _ T, and a reception control timing signal TR _ R, and the corresponding pins are distributed as shown in fig. 2. The big Data frame is sent by a Data1 serial receiving beam controller, the baud rate is maximum 10Mbps, the format of the big Data frame is shown in Table 1, the Data frame consists of a frame header 0 xABB, a Data2 enabled output bit, 8T/R component control Data, control Data of 1 TTDL component and a check bit, and the total number of the Data frame is 264 bit. The length of the control Data of each T/R component is 24 bits, the length of the control Data of each TTDL component is also 24 bits, 24 bits are formed by the frame header 0 xABB, the Data2 enabling output bits and 6 spare bits, and the check bit is 24 bits.

Table 1 big data frame format

The data validity detection adopts a sum check mode, namely the first 240 bit data is compared with a check bit according to the result obtained by adding every 24 bits, if the result is equal, the check is correct, the small data packet is immediately recombined according to a 24bit section and then is sent to a T/R component and a TTDL component, if the result is not equal, the check is wrong, the data frame is discarded, and a check error flag bit is recorded.

The timing combination is a logical combination of the transmission control timing TR _ T and the reception control timing TR _ R from the beam controller, and in principle TR _ T and TR _ R cannot be logically simultaneously effective. Pin E _ T is used to set the logic level at which TR _ T is active and pin E _ R is used to set the logic level at which TR _ R is active. If pins E _ T and E _ R are both tied to +5V, then timings TR _ T and TR _ R cannot be logic high at the same time. If the TR _ T and the TR _ R are detected to be at the logic high level at the same time, the TR _ T and the TR _ R are forced to be converted into the logic low level, and the time sequence combination error flag bit is recorded. If the logic combination of the time sequences TR _ T and TR _ R is correct, the time sequence TR _ T continues to perform the next pulse width detection, and the time sequence TR _ R is forwarded to the pin TR _ R _1 and the pin TR _ R _2 to be sent to the T/R component and the TTDL component.

Pulse width detection detects only the transmission control timing width TR _ T, and the detection threshold is determined by the time constant of the resistor R3 and the capacitor C2 connected to the pins PW1 and PW2 (τ ═ R ═ C). If the pulse width does not exceed the detection threshold, outputting TR _ T, if the pulse width exceeds the detection threshold, forcibly adjusting the transmission control time sequence to be proper width and then outputting, and recording the pulse width error flag bit.

The A/D converter supports cyclic collection of 8 paths of differential analog signals, namely a pin AN _1P/AN _1N, a pin AN _2P/AN _2N, a pin AN _3P/AN _3N, a pin AN _4P/AN _4N, a pin AN _5P/AN _5N, a pin AN _6P/AN _6N, a pin AN _7P/AN _7N and a pin AN _8P/AN _ 8N. All the 8 analog signals are linearly quantized with a full scale of 8bit with +5V, i.e. 0x00 represents 0V and 0xFF represents + 5V. The internal self-contained reference voltage, pin VRO is the reference voltage output, connected to the reference voltage input pin VRI, and pin VR connects the filter capacitor C1 to ground.

The pin DATA _0P/DATA _0N, the pin DATA _1P/DATA _1N, the pin DATA _2P/DATA _2N, the pin DATA _3P/DATA _3N, the pin DATA _4P/DATA _4N, the pin DATA _5P/DATA _5N, the pin DATA _6P/DATA _6N, the pin DATA _7P/DATA _7N, and the pin DATA _8P/DATA _8N are 9 RS422 differential driving signals, and the RS422 differential driving circuit module from the special integrated circuit is used for serially transmitting 24-bit small DATA packets to 8T/R components and 1 TTDL component, and the baud rate is maximum 10 Mbps. The pin BITE _0P/DATA _0N, the pin BITE _1P/DATA _1N, the pin BITE _2P/DATA _2N, the pin BITE _3P/DATA _3N, the pin BITE _4P/DATA _4N, the pin BITE _5P/DATA _5N, the pin BITE _6P/DATA _6N, the pin BITE _7P/DATA _7N, and the pin BITE _8P/DATA _8N are 9 RS422 differential receiving signals, and the RS422 differential receiving circuit module from the special integrated circuit is used for receiving BIT fault information of 8T/R components and 1 TTDL component and then sending the BIT fault information back to a feedback DATA frame. The BIT fault information here is a high-low level signal, where a high level represents normal and a low level represents fault.

The interface control signals of the T/R component and the TTDL component include 2-way refresh control signals SX _2 and SX _1, 2-way clock signals CLK _1 and CLK _2, 2-way write strobe signals WR _1 and WR _2, 2-way transmission control timing signals TR _ T _1 and TR _ T _2, and 2-way reception control timing signals TR _ R _1 and TR _ R _2, and corresponding pins are shown in fig. 2. When the microwave module is used, each control signal is generally sent to an external RS422 driver to be converted into an RS422 differential signal, a plurality of microwave assemblies are controlled in an RS422 bus mode, and each control signal can drive 4 RS422 drivers.

When telemetry Data is needed, enabling output bits EN1 and EN2 of Data2 in a large Data frame received by the application specific integrated circuit are effective, corresponding pins EN1 and EN2 output effective control levels, and a return channel is opened. The pins EN1 and EN2 are connected to two enable terminals of an external RS422 driver, and feedback Data are serially transmitted to the beam controller through the Data2 under the control of the clock signal CLK and the read strobe signal RD. The format of the feedback data frame is shown in table 2, and includes 8 channels of a/D sampling data 64BIT, 9 component BIT signals 9BIT, timing combination error 1BIT, pulse width error 1BIT, and check BITs 8BIT, which are 88 BITs in total. The check bits are accumulated from the first 80 bits.

TABLE 2 frame format of feedback data

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims

1. An anti-irradiation wave control special integrated circuit is characterized by comprising a wave control data forwarding module, a time sequence detection distribution module and a telemetering data returning module, wherein the wave control data forwarding module comprises a large data frame extraction module, a data validity detection module, a small data packet recombination and RS422 differential driving module which are sequentially connected, the time sequence detection distribution module comprises a time sequence combination judgment module and a pulse width detection module, and the telemetering data returning module comprises a feedback data frame module, an A/D converter and an RS422 differential receiving module;

the big data frame extraction module extracts data from the beam controller;

the A/D converter converts the analog signal into a digital signal;

2. The radiation-resistant wave-control application specific integrated circuit according to claim 1, wherein the big data frame extraction module is responsible for receiving wave-control data from the wave beam controller in a serial communication mode, and the baud rate is up to 10 Mbps.

3. The radiation-resistant wave-control application specific integrated circuit according to claim 1, wherein the detection threshold of the pulse width detection module is determined by a resistor and a capacitor connected outside the application specific integrated circuit.

4. The radiation-resistant ASIC of claim 3, wherein the pulse width detection module only detects the emission control timing width TR _ T, the detection threshold is determined by the time constant τ of the resistor R3 and capacitor C2 connected to the leads PW1 and PW2, and τ is R _ C, and if the detection threshold is not exceeded, then TR _ T is output, and if the detection threshold is exceeded, then the emission control timing is forced to be adjusted to a proper width and then output, and a pulse width error flag is recorded.

5. The radiation-resistant wave-control application specific integrated circuit according to claim 1, wherein the application specific integrated circuit is powered by direct current +5V, the a/D converter supports cyclic acquisition of 8 paths of differential analog signals, and the analog signals are linearly quantized in a full scale with +5V being 8bit, that is, 0x00 represents 0V, and 0xFF represents + 5V.

6. The radiation-resistant wave-control application specific integrated circuit of claim 1, wherein the big Data frame extracted by the big Data frame extraction module comprises a frame header 0xAABB, a Data2 enabling output bit, 8T/R component control Data, 1 TTDL component control Data and a check bit, wherein the total number of the check bits is 264 bits, the control Data length of each T/R component is 24 bits, the control Data length of the TTDL component is also 24 bits, the frame header 0xAABB, the Data2 enabling output bit and 6 spare bits constitute 24 bits, and the check bit is 24 bits.

7. The radiation-resistant wave-control application-specific integrated circuit according to claim 6, wherein the data validity detection module adopts a sum check mode, that is, the result obtained by adding every 24 bits of the first 240 bits of data is compared with the check bits, if the result is equal, the check is correct, the small data packets are immediately recombined according to 24bit sections and then sent to the T/R component and the TTDL component, if the result is unequal, the check is wrong, the data frame is discarded, and the check error flag bit is recorded.

8. The radiation-resistant wave-control asic as recited in claim 1, wherein the time sequence combination judging module is a logic combination of a transmission control time sequence TR _ T and a reception control time sequence TR _ R from the wave beam controller, TR _ T and TR _ R are not logically simultaneously valid, pin E _ T is used to set a logic level at which TR _ T is valid, pin E _ R is used to set a logic level at which TR _ R is valid, if pin E _ T and pin E _ R are both connected to +5V, then time sequences TR _ T and TR _ R are not simultaneously logic high, if it is detected that TR _ T and TR _ R are simultaneously logic high, then TR _ T and TR _ R are forcibly converted to logic low, and a time sequence combination error flag bit is recorded, if the logic combination of time sequences TR _ T and TR _ R is correct, then the time sequence TR _ T continues to perform the next pulse width detection, and the time sequence TR _ R is forwarded to the pin TR _ R _1 and the pin TR _ R _2 at the same time and sent to the T/R component and the TTDL component.