CN108807620A - A kind of LED epitaxial slice and preparation method thereof - Google Patents
A kind of LED epitaxial slice and preparation method thereof Download PDFInfo
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- CN108807620A CN108807620A CN201810616928.0A CN201810616928A CN108807620A CN 108807620 A CN108807620 A CN 108807620A CN 201810616928 A CN201810616928 A CN 201810616928A CN 108807620 A CN108807620 A CN 108807620A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 230000004888 barrier function Effects 0.000 claims abstract description 120
- 229910016920 AlzGa1−z Inorganic materials 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 34
- 230000006798 recombination Effects 0.000 abstract description 8
- 238000005215 recombination Methods 0.000 abstract description 8
- 238000004020 luminiscence type Methods 0.000 abstract description 4
- 230000010287 polarization Effects 0.000 abstract description 4
- 230000009467 reduction Effects 0.000 abstract description 4
- 230000000903 blocking effect Effects 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 description 12
- 229910002704 AlGaN Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000004047 hole gas Substances 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000005395 radioluminescence Methods 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention discloses a kind of LED epitaxial slices and preparation method thereof, belong to light emitting diode manufacturing field.It sets active layer to include the first barrier layer and multiple InGaN well layer, multiple in the first barrier layer include GaN/InxGa1‑xN/AlzGa1‑zN/InyGa1‑yFirst sub- barrier layer of N/GaN superlattice structures and the alternately laminated setting of InGaN well layer.Due to GaN/InxGa1‑xN/AlzGa1‑ zN/InyGa1‑yThe energy band of N/GaN superlattice structures is higher, blocking electronics can be played and enter p-type GaN layer, therefore electronic barrier layer need not be set to stop that electronics flows out active layer, this set can limit while electronics leaves active layer and improve the number of cavities entered in active layer, and then improve the number of cavities in active layer with electronics recombination luminescence, and it can also reduce in epitaxial layer due to being provided with electronic barrier layer, polarization situation between the electronic barrier layer brought and active layer and P-type layer, and then avoid the reduction of luminous band gap in epitaxial layer, increase the combined efficiency of electronics and hole, and then increase the luminous efficiency of light emitting diode.
Description
Technical field
The present invention relates to light emitting diode manufacturing field, more particularly to a kind of LED epitaxial slice and its preparation side
Method.
Background technology
Light emitting diode is a kind of semiconductor diode that electric energy can be converted to luminous energy, have small, long lifespan,
The advantages that low in energy consumption, is widely used in automobile signal light, traffic lights, display screen and lighting apparatus at present.Epitaxial wafer
It is the foundation structure for making light emitting diode, the structure of epitaxial wafer includes substrate and the epitaxial layer grown on substrate.Wherein,
The structure of epitaxial layer includes mainly：Grow successively low temperature GaN buffer on substrate, undoped GaN layer, N-type GaN layer,
Active layer, AlGaN electronic barrier layers and p-type GaN layer.
AlGaN electronic barrier layers can usually play the role of avoiding in the electron transfer to p-type GaN layer in active layer, protect
It demonstrate,proves electronics as much as possible and carries out luminous efficiency that is compound, and then ensureing light emitting diode in active layer.But AlGaN electronics simultaneously
Barrier layer can also stop that hole enters active layer, and the quantity for entering the hole of active layer relatively enters the electron number of active layer originally
Amount is few, and AlGaN electronic barrier layers can play limitation into the quantity in the hole of active layer so that in active layer and Electronic Coincidence Means
The number of cavities of radioluminescence is less so that the luminous efficiency of light emitting diode entirety is relatively low.
Invention content
An embodiment of the present invention provides a kind of LED epitaxial slices and preparation method thereof, can improve light emitting diode
Luminous efficiency.The technical solution is as follows：
An embodiment of the present invention provides a kind of LED epitaxial slice, the epitaxial wafer includes substrate and is sequentially laminated on
Low temperature GaN buffer, layer of undoped gan, N-type GaN layer, active layer on the substrate and p-type GaN layer,
The active layer includes the first barrier layer and multiple well layer, and first barrier layer includes the multiple first sub- barrier layer, described
First sub- barrier layer and the alternately laminated setting of the well layer, the well layer are InGaN well layer, and the first sub- barrier layer includes GaN/
InxGa1-xN/AlzGa1-zN/InyGa1-yN/GaN superlattice structures, wherein 0<x<0.08,0<y<0.07,0.05<z<0.35.
Optionally, the ratio of x and z is 0.15:1~0.4:1.
Optionally, x>y.
Optionally, the ratio of x and y is 3:1~5:1.
Optionally, the active layer further includes the second barrier layer, and second barrier layer includes two GaN barrier layer, described two
GaN barrier layer is separately positioned on the both sides of first barrier layer, and one is provided between described two GaN barrier layer and first barrier layer
The layer well layer.
Optionally, the thickness of the GaN barrier layer is identical as the thickness of the described first sub- barrier layer.
Optionally, the thickness of the described first sub- barrier layer is 8~20nm.
Optionally, the number of plies of the described first sub- barrier layer is 3~13.
An embodiment of the present invention provides a kind of preparation method of LED epitaxial slice, the preparation method includes：
One substrate is provided；
Growing low temperature GaN buffer layers over the substrate；
Layer of undoped gan is grown on the low temperature GaN buffer；
N-type GaN layer is grown in the layer of undoped gan；
Active layer is grown in the N-type GaN layer；
Growth P-type GaN layer on the active layer,
Wherein, active layer includes the first barrier layer and multiple well layer, and first barrier layer includes the multiple first sub- barrier layer, described
First sub- barrier layer and the alternately laminated setting of the well layer, the well layer are InGaN well layer, and the first sub- barrier layer includes GaN/
InxGa1-xN/AlzGa1-zN/InyGa1-yN/GaN superlattice structures, wherein 0<x<0.08,0<y<0.07,0.05<z<0.35.
Optionally, the growth temperature of the well layer is 720~830 DEG C, the growth temperature of the first sub- barrier layer is 850~
959℃。
The advantageous effect that technical solution provided in an embodiment of the present invention is brought is：Due to GaN/InxGa1-xN/AlzGa1-zN/
InyGa1-yThe energy band of N/GaN superlattice structures is higher, can play the role of stopping that electronics enters in p-type GaN layer, therefore at this
In invention, setting electronic barrier layer is not needed to stop that electronics flows out active layer, this set can leave in limitation electronics
The number of cavities entered in active layer is improved while active layer, and then improves the hole in active layer with electronics recombination luminescence
Quantity can also reduce in epitaxial layer while improving light-emitting diode luminous efficiency due to being provided with electronic barrier layer, band
Polarization situation between the electronic barrier layer come and active layer and P-type layer, and then the reduction of luminous band gap in epitaxial layer is avoided,
Increase the combined efficiency of electronics and hole, and then increases the luminous efficiency of light emitting diode.
Description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, other are can also be obtained according to these attached drawings
Attached drawing.
Fig. 1 is a kind of structure chart of LED epitaxial slice provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of another epitaxial wafer provided in an embodiment of the present invention；
Fig. 3 is a kind of preparation method flow chart of LED epitaxial slice provided in an embodiment of the present invention；
Fig. 4~Fig. 5 is a kind of epitaxial slice structure flow chart of the epitaxial wafer provided in an embodiment of the present invention in preparation process；
Fig. 6 is the preparation method of another epitaxial wafer provided in an embodiment of the present invention；
Fig. 7 is epitaxial slice structure schematic diagram of another epitaxial wafer provided in an embodiment of the present invention in preparation process.
Specific implementation mode
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Fig. 1 is a kind of structure chart of LED epitaxial slice provided in an embodiment of the present invention.As shown in Figure 1, the extension
Piece includes substrate 1 and the low temperature GaN buffer being sequentially laminated on substrate 12, layer of undoped gan 3, N-type GaN layer 4, active layer 5
And p-type GaN layer 6.
Active layer 5 includes the first barrier layer 51 and multiple well layer 521, and the first barrier layer 51 includes the multiple first sub- barrier layer 511, the
One sub- barrier layer 511 and 521 alternately laminated setting of well layer, well layer 521 are InGaN well layer, and the first sub- barrier layer 511 includes GaN/
InxGa1-xN/AlzGa1-zN/InyGa1-yN/GaN superlattice structures, wherein 0<x<0.08,0<y<0.07,0.05<z<0.35.
Due to GaN/InxGa1-xN/AlzGa1-zN/InyGa1-yThe energy band of N/GaN superlattice structures is higher, can play blocking
Electronics enters the effect in p-type GaN layer, therefore in the present invention, does not need to setting electronic barrier layer to stop that electronics flows out
Active layer, this set can improve the number of cavities entered in active layer while limiting electronics and leaving active layer, in turn
The number of cavities in active layer with electronics recombination luminescence is improved while improving light-emitting diode luminous efficiency also can
Reduce in epitaxial layer due to being provided with electronic barrier layer, the polarization between the electronic barrier layer brought and active layer and P-type layer
Situation, and then the reduction of luminous band gap in epitaxial layer is avoided, increase the combined efficiency of electronics and hole, and then increase light-emitting diodes
The luminous efficiency of pipe.
Meanwhile GaN/InxGa1-xN/AlzGa1-zN/InyGa1-yCan be formed in N/GaN superlattice structures two-dimensional electron gas with
Two-dimensional hole gas, GaN/InxGa1-xN/AlzGa1-zN/InyGa1-yTwo-dimensional electron gas and Two-Dimensional Hole in N/GaN superlattice structures
Electronics can be limited in active layer by the formation of gas so that and more electronics can carry out radiation recombination in active layer with hole,
Further increase the luminous efficiency of light emitting diode.
Optionally, the thickness of layer of undoped gan 3 can be 0.1 to 2.0 μm.
Wherein, the doped chemical in N-type GaN layer 4 is Si.The thickness of N-type GaN layer 4 can be 1~5 μm.
Illustratively, the ratio of x and z is 0.15:1~0.4:1.The ratio of x and z is set to range above may make
More uniformly spreading for compound electronics and hole is carried out in active layer, and then improves the luminous efficiency of light emitting diode.
Optionally, x>y.X may make GaN/In more than yxGa1-xN/AlzGa1-zN/InyGa1-yIn N/GaN superlattice structures
Two-dimensional electron gas be more readily formed with two-dimensional hole gas, make electronics be easier with hole to carry out radiation recombination in active layer,
Improve the luminous efficiency of light emitting diode.
Further, the ratio of x and y can be 3:1~5:1.This set may make more electronics with hole active
Radiation recombination is carried out in layer, improves the luminous efficiency of light emitting diode.
Specifically, the ratio of x and y can be 4:The ratio of 1, x and y is set as 4:When 1, the luminous efficiency of light emitting diode carries
It rises larger.
It is additionally provided with p-type GaN layer 6 as shown in Figure 1, dividing in the present embodiment, on active layer 5, the thickness of p-type GaN layer 6 can
For 100~200nm.
Fig. 2 is the structural schematic diagram of another epitaxial wafer provided in an embodiment of the present invention, as shown in Fig. 2, active layer 5 also wraps
The second barrier layer 53 is included, the second barrier layer 53 includes two GaN barrier layer 531, and two GaN barrier layer 531 are separately positioned on the first barrier layer 51
Both sides, one layer of well layer 521 is provided between two GaN barrier layer 531 and the first barrier layer 51.
Two GaN barrier layer 531 are separately positioned on to the both sides of the first barrier layer 51, GaN/In can be reducedxGa1-xN/AlzGa1- zN/InyGa1-yLattice mismatch between N/GaN superlattice structures and p-type GaN layer further increases the total quality of epitaxial layer,
Ensure the luminous efficiency of light emitting diode.
Optionally, active layer 5 further include be positioned close to the GaN barrier layer 531 of 4 side of N-type GaN layer and N-type GaN layer 4 it
Between one layer of well layer 521.The electronics that this set is conducive in N-type GaN layer can smoothly enter into active layer.
Illustratively, the thickness of GaN barrier layer 531 can be identical as the thickness of the first sub- barrier layer 511.By the thickness of GaN barrier layer
Be set as with it is identical, be convenient for active layer entirety growth and making.
Wherein, the thickness of the first sub- barrier layer 511 can be 8~20nm.The thickness of first sub- barrier layer is arranged in range above
It can guarantee the quality of the first sub- barrier layer, and then improve epitaxial layer total quality, ensure the luminous efficiency of light emitting diode.Well layer
521 thickness can be 3nm.
Optionally, the number of plies of the first sub- barrier layer 511 can be 3~13.The number of plies of first sub- barrier layer is arranged in range above
It is more suitable, make more electronics that can carry out radiation recombination in active layer and hole, ensures the luminous effect of light emitting diode
While rate, the cost of manufacture of active layer will not be increased.
As shown in Fig. 2, in the present embodiment, p-type GaN layer 6 and p-type contact layer 7 are additionally provided on active layer 5 respectively.Its
In, the thickness of p-type contact layer 7 can be 5~300nm.
Fig. 3 is a kind of preparation method flow chart of LED epitaxial slice provided in an embodiment of the present invention, such as Fig. 3 institutes
Show, which includes：
Step S11：One substrate is provided.
Wherein, Sapphire Substrate can be used in substrate.
Optionally, this preparation method may also include, and be made annealing treatment to substrate.To obtain surface quality preferably more
Clean substrate advantageously ensures that the quality of the epitaxial layer grown on substrate.
Wherein, annealing is carried out to substrate may include：It anneals in a hydrogen atmosphere to substrate, anneal duration 8min,
Annealing temperature is 1000~1200 DEG C, and annealing pressure is 400~600Torr.
Further, after substrate completes annealing operation, can also nitrogen treatment, i.e. Mr. on substrate be carried out to substrate
Long one layer of AlN, to reduce the lattice mismatch between substrate and N-type GaN layer.
Step S12：Growing low temperature GaN buffer layers on substrate.
Wherein, the growth temperature of low temperature GaN buffer can be 400~600 DEG C, and the growth pressure of low temperature GaN buffer can
For 400~600Torr.The quality of the low temperature GaN buffer obtained at this temperature is preferable, can effectively play and reduce N-type GaN layer
Lattice mismatch issue between substrate.
Optionally, the growth thickness of low temperature GaN buffer can be 15~35nm.
Further, after growth is completed on low temperature GaN buffer, in-situ annealing can be carried out to low temperature GaN buffer
Processing.The dislocation that can be reduced in low temperature GaN buffer is made annealing treatment to low temperature GaN buffer, ensures low temperature GaN buffer
Quality, be conducive to the growth of subsequent epitaxial layer.
Wherein, carrying out annealing to low temperature GaN buffer includes：
Under conditions of annealing temperature is 1000~1200 DEG C, annealing pressure is 400~600Torr, low temperature GaN is buffered
Layer carries out in-situ annealing processing, and anneal duration is 5~10min.
Step S13：Layer of undoped gan is grown on low temperature GaN buffer.
In step S13, the growth temperature of layer of undoped gan can be 1000~1100 DEG C, growth pressure can be 100~
500Torr.The quality of the layer of undoped gan grown with this condition is preferable.
Illustratively, the thickness of layer of undoped gan can be 1~5 μm.
Step S14：N-type GaN layer is grown in layer of undoped gan.
In embodiments of the present invention, N-type GaN layer can be N-type GaN layer.
Wherein, the growth temperature of N-type GaN layer can be 1000~1200 DEG C, and growth pressure can be 100~500Torr.
The thickness of N-type GaN layer can be 1~5 μm.
Optionally, the doped chemical of N-type GaN layer is Si elements, and the doping concentration of Si elements is 1018~1019cm-3。
The structural schematic diagram of the epitaxial layer after S14 is executed the step as shown in figure 4, being sequentially laminated with low temperature on substrate 1
GaN buffer layers 2, layer of undoped gan 3, N-type GaN layer 4.
Step S15：Active layer is grown in N-type GaN layer.
Wherein, active layer may include that the first barrier layer and multiple well layer, the first barrier layer include the multiple first sub- barrier layer, the first son
Barrier layer and the alternately laminated setting of well layer, well layer are InGaN well layer, and the first sub- barrier layer includes GaN/InxGa1-xN/AlzGa1-zN/
InyGa1-yN/GaN superlattice structures, wherein 0<x<0.08,0<y<0.07,0.05<z<0.35.
Wherein, the growth temperature of well layer is 720~830 DEG C, and the growth temperature of the first sub- barrier layer is 850~959 DEG C.By trap
The quality that the growth temperature of layer and the first sub- barrier layer is separately positioned on the active layer that range above can guarantee that growth obtains is preferable, protects
Demonstrate,prove the luminous efficiency of light emitting diode.
Executing the step the epitaxial layer structure after S15 can be as shown in figure 5, growth has low temperature GaN bufferings successively on substrate 1
Layer 2, layer of undoped gan 3, N-type GaN layer 4 and active layer 5, active layer 5 include the first barrier layer 51 and multiple well layer 521, first base
Layer 51 includes the multiple first sub- barrier layer 511, and the first sub- barrier layer 511 and well layer 521 are alternately laminated.
Step S16：The growth P-type GaN layer on active layer.
In the present embodiment, the growth temperature of p-type GaN layer can be 850~1080 DEG C, growth pressure can be 100~
300Torr。
The growth thickness of p-type GaN layer can be 100~800nm.
The epitaxial slice structure of above step has been executed as shown in Figure 1, being provided with p-type GaN layer 6 on active layer 5.
Due to GaN/InxGa1-xN/AlzGa1-zN/InyGa1-yThe energy band of N/GaN superlattice structures is higher, can play blocking
Electronics enters the effect in p-type GaN layer, therefore in the present invention, does not need to setting electronic barrier layer to stop that electronics flows out
Active layer, this set can improve the number of cavities entered in active layer while limiting electronics and leaving active layer, in turn
The number of cavities in active layer with electronics recombination luminescence is improved while improving light-emitting diode luminous efficiency also can
Reduce in epitaxial layer due to being provided with electronic barrier layer, the polarization between the electronic barrier layer brought and active layer and P-type layer
Situation, and then the reduction of luminous band gap in epitaxial layer is avoided, increase the combined efficiency of electronics and hole, and then increase light-emitting diodes
The luminous efficiency of pipe.
Optionally, this preparation method may also include：
It after epitaxial wafer growth terminates, anneals under nitrogen atmosphere to epitaxial wafer, annealing temperature is 650~850
DEG C, anneal duration is 5~15min.Epitaxial wafer growth, which anneals to it after terminating, can activate the Mg in p-type GaN layer former
Son improves the hole concentration in p-type GaN layer, is conducive to the luminous efficiency for improving light emitting diode.
Fig. 6 is the preparation method of another epitaxial wafer provided in an embodiment of the present invention, and step includes：
Step S21：One substrate is provided.
Step S22：Growing low temperature GaN buffer layers on substrate.
Step S23：Layer of undoped gan is grown on low temperature GaN buffer.
In step S23, the growth temperature of layer of undoped gan can be 1000~1100 DEG C, growth pressure can be 100~
500Torr.The quality of the layer of undoped gan grown with this condition is preferable.
Illustratively, the thickness of layer of undoped gan can be 1~5 μm.
Step S24：N-type GaN layer is grown in layer of undoped gan.
Step S25：Active layer is grown in N-type GaN layer.
Active layer may include that the first barrier layer and multiple well layer, the first barrier layer include the multiple first sub- barrier layer, the first sub- barrier layer
With the alternately laminated setting of well layer, well layer is InGaN well layer, and the first sub- barrier layer includes GaN/InxGa1-xN/AlzGa1-zN/InyGa1- yN/GaN superlattice structures, wherein 0<x<0.08,0<y<0.07,0.05<z<0.35.
Further, active layer further includes the second barrier layer, and the second barrier layer includes two GaN barrier layer, two GaN barrier layer difference
It is arranged between the both sides of the first barrier layer, two GaN barrier layer and the first barrier layer and is provided with one layer of well layer.
Wherein, the growth temperature of GaN barrier layer can be identical as the growth temperature of the first sub- barrier layer, is convenient for the life of active layer entirety
Long and making.
Execute the step visible Fig. 7 of epitaxial slice structure after S25, be sequentially laminated on substrate 1 low temperature GaN buffer 2,
Layer of undoped gan 3, N-type GaN layer 4 and active layer 5.Active layer 5 includes the first barrier layer 51 and multiple well layer 521, the first barrier layer 51
Including the multiple first sub- barrier layer 511, the first sub- barrier layer 511 and well layer 521 are alternately laminated.Active layer 5 further includes the second barrier layer 53,
Second barrier layer 53 includes two GaN barrier layer 531, and GaN barrier layer 531 and 521 alternately laminated setting of well layer, two GaN barrier layer 531 are divided
It is not arranged in the both sides of the first barrier layer 51.
Step S26：The growth P-type GaN layer on active layer.
Step S27：The growing P-type contact layer in p-type GaN layer.
Wherein the growth temperature of p-type contact layer can be 650~850 DEG C, and growth pressure can be 100~300Torr.Its thickness
It may be configured as 5~300nm.Visible Fig. 2 of epitaxial slice structure figure after S27 is executed the step,.Its structure include substrate 1 and
Low temperature GaN buffer 2, layer of undoped gan 3, N-type GaN layer 4, active layer 5, p-type GaN layer 6 and the P being sequentially laminated on substrate 1
Type contact layer 7.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of LED epitaxial slice, the epitaxial wafer includes substrate and stacks gradually low temperature GaN over the substrate
Buffer layer, layer of undoped gan, N-type GaN layer, active layer and p-type GaN layer, which is characterized in that
The active layer includes the first barrier layer and multiple well layer, and first barrier layer includes the multiple first sub- barrier layer, and described first
Sub- barrier layer and the alternately laminated setting of the well layer, the well layer are InGaN well layer, and the first sub- barrier layer includes GaN/
InxGa1-xN/AlzGa1-zN/InyGa1-yN/GaN superlattice structures, wherein 0<x<0.08,0<y<0.07,0.05<z<0.35.
2. epitaxial wafer according to claim 1, which is characterized in that the ratio of x and z is 0.15:1~0.4:1.
3. epitaxial wafer according to claim 1, which is characterized in that x>y.
4. epitaxial wafer according to claim 3, which is characterized in that the ratio of x and y is 3:1~5:1.
5. according to claims 1 to 3 any one of them epitaxial wafer, which is characterized in that the active layer further includes the second barrier layer,
Second barrier layer includes two GaN barrier layer, and described two GaN barrier layer are separately positioned on the both sides of first barrier layer, described
One layer of well layer is provided between two GaN barrier layer and first barrier layer.
6. epitaxial wafer according to claim 5, which is characterized in that the thickness of the GaN barrier layer and the described first sub- barrier layer
Thickness it is identical.
7. according to claims 1 to 3 any one of them epitaxial wafer, which is characterized in that the thickness of the first sub- barrier layer be 8~
20nm。
8. according to claims 1 to 3 any one of them epitaxial wafer, which is characterized in that the number of plies of the first sub- barrier layer be 3~
13。
9. a kind of preparation method of LED epitaxial slice, which is characterized in that the preparation method includes：
One substrate is provided；
Growing low temperature GaN buffer layers over the substrate；
Layer of undoped gan is grown on the low temperature GaN buffer；
N-type GaN layer is grown in the layer of undoped gan；
Active layer is grown in the N-type GaN layer；
Growth P-type GaN layer on the active layer,
Wherein, active layer includes the first barrier layer and multiple well layer, and first barrier layer includes the multiple first sub- barrier layer, and described first
Sub- barrier layer and the alternately laminated setting of the well layer, the well layer are InGaN well layer, and the first sub- barrier layer includes GaN/
InxGa1-xN/AlzGa1-zN/InyGa1-yN/GaN superlattice structures, wherein 0<x<0.08,0<y<0.07,0.05<z<0.35.
10. preparation method according to claim 9, which is characterized in that the growth temperature of the well layer is 720~830 DEG C,
The growth temperature of the first sub- barrier layer is 850~959 DEG C.
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