CN108807404B - Semiconductor manufacturing method and semiconductor structure - Google Patents

Semiconductor manufacturing method and semiconductor structure Download PDF

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CN108807404B
CN108807404B CN201810558364.XA CN201810558364A CN108807404B CN 108807404 B CN108807404 B CN 108807404B CN 201810558364 A CN201810558364 A CN 201810558364A CN 108807404 B CN108807404 B CN 108807404B
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contact hole
step area
area
region
forming
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CN108807404A (en
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赵亮亮
张文杰
盖晨光
宋宏光
周文华
王玉岐
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Semiconductor Memories (AREA)
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Abstract

The invention provides a contact hole forming method for forming a contact hole in a step region in a three-dimensional memory device and a three-dimensional memory device using the same. The contact hole forming method comprises the following steps: a step of forming a semiconductor structure having a stepped region including a first stepped region and a second stepped region and formed by alternately stacking at least one dielectric layer and at least one conductive layer; forming a first step area contact hole and a second step area contact hole until the first step area contact hole contacts with the conductive layer of the first step layer; forming a protective layer on the side wall and the bottom surface of the contact hole in the first step area; and consuming the protective layer and enabling the contact hole of the second step area to be in contact with the conductive layer of the second step area.

Description

Semiconductor manufacturing method and semiconductor structure
Technical Field
The present invention relates to a semiconductor manufacturing method and a semiconductor structure using the same, and more particularly, to a method of forming a contact hole in a step region in a three-dimensional memory device and a three-dimensional memory device using the same.
Background
With the continuous development of semiconductor technology, memory manufacturing technology has gradually transitioned from a simple planar structure to a more complex three-dimensional structure, with integration density being increased by three-dimensionally arranging memory cells over a substrate. The technical development of such a three-dimensional memory device is one of the mainstream of international development.
It is known that in semiconductor layouts, connections between active regions, polysilicon and metal layers need to be made through contact holes or via holes. For the formation of the contact hole in the step area in the three-dimensional memory device, because the number of step layers in the step area in the three-dimensional memory device is large, in the step of forming the contact hole, in order to ensure that the lower step has enough Over-etching (Over Etch) depth, the upper step is easy to have etching Through (Punch Through), so that the process requirements cannot be met, and the product yield is reduced.
For such a situation, a plurality of masks are usually selected in the industry at present, and contact holes are respectively formed for the upper step and the lower step.
Disclosure of Invention
Technical problem to be solved by the invention
In the prior art in which contact holes of a high step and a low step are formed by using a plurality of masks, as the number of steps of a step region in a three-dimensional memory device increases, the number of masks needs to be increased accordingly, which results in a significant increase in production cost.
In addition, because different masks are needed to form the contact holes of the high-level step and the low-level step for multiple times, the deviation in the manufacturing process is accumulated and increased continuously, and further, the final product can not meet the process requirement, so that the product yield is reduced.
Technical scheme for solving technical problem
The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of forming a contact hole in a step region in a three-dimensional memory device and a three-dimensional memory device using the same.
The contact hole forming method is used for forming a contact hole of a step area in a three-dimensional memory device, and is characterized by comprising the following steps of:
a semiconductor structure forming procedure, wherein the semiconductor structure is provided with a step area, the step area comprises a first step area and a second step area positioned below the first step area, the first step area and the second step area respectively comprise a plurality of step structures, and the step structures are formed by alternately stacking at least one dielectric layer and at least one conducting layer;
a first step area contact hole corresponding to the conductive layer of the first step area and a second step area contact hole corresponding to the conductive layer of the second step area are formed on the first step area and the second step area, wherein the first step area contact hole is in contact with the conductive layer of the corresponding first step area or is positioned above the conductive layer of the corresponding first step area;
a protective layer forming step of forming a protective layer on the side wall and the bottom surface of the first step region contact hole; and
and a second contact hole forming step of bringing the second step area contact hole into contact with the conductive layer of the second step area corresponding thereto, or bringing the first step area contact hole into contact with the conductive layer of the first step area corresponding thereto while bringing the second step area contact hole into contact with the conductive layer of the second step area corresponding thereto.
Preferably, in the contact hole first forming step, the second step area contact hole is formed to a depth greater than a depth of the first step area contact hole.
Preferably, in the protective layer forming step, a protective layer is further formed on at least a partial region of the sidewall of the second step-region contact hole, and the protective layer is not formed on the bottom surface of the second step-region contact hole.
Preferably, in the contact hole first forming step, a depth of the first step region contact hole is determined according to a number of the step structures included in the step region.
Preferably, in the protective layer forming step, the thickness of the protective layer is determined according to the number of the step structures included in the step region.
Preferably, the same mask is used in the first contact hole forming step and the second contact hole forming step.
Preferably, the protective layer is made of a conductive material.
Preferably, the material of the protective layer is metal or metal silicide.
Further, a three-dimensional memory device according to the present invention includes:
the step area comprises a first step area and a second step area positioned below the first step area, the first step area and the second step area respectively comprise a plurality of step structures, and the step structures are formed by alternately stacking at least one dielectric layer and at least one conducting layer;
a first stepped region conductive contact formed on and in contact with a corresponding conductive layer of the first stepped region, at least a portion of the first stepped region conductive contact comprising a first material layer and a second material layer, the second material layer being comprised of a different material than the first material layer;
and the second step area conductive contact is formed on the conductive layer of the second step area and is in contact with the conductive layer of the corresponding second step area.
Preferably, the first material layer is made of a conductive material.
Preferably, the first material layer is in contact with the conductive layer of the corresponding first step region, and the second material layer is formed on the side wall of the first material layer.
Preferably, the second material layer is made of a conductive material, the second material layer is in contact with the conductive layer of the corresponding first step region, and the second material layer is formed on the side wall and the bottom surface of the first material layer.
Preferably, the three-dimensional memory device is a floating gate type three-dimensional NAND memory or a charge trap type three-dimensional NAND memory.
Effects of the invention
According to the contact hole forming method and the three-dimensional memory device using the contact hole forming method, the step contact hole can be formed in the three-dimensional memory device with more step layers by using only one mask without etching and penetrating, so that the number of the masks is greatly reduced, and the production cost is reduced.
In addition, according to the contact hole forming method and the three-dimensional memory device using the same, with the technical development of the three-dimensional memory device, even if the number of stacked step layers continues to increase, the number of masks does not need to be increased, the production period is greatly shortened, and the production cost is further reduced.
In addition, according to the contact hole forming method and the three-dimensional storage device using the contact hole forming method, as the contact hole with enough over-etching depth and high reliability can be realized only by using one mask in the whole contact hole forming process, the deviation of the whole manufacturing process is reduced, the reliability of the electrical performance of the three-dimensional storage device is improved, and the yield of the final product is improved.
Drawings
Fig. 1 is a cross-sectional view illustrating a step region of a three-dimensional memory device according to the present invention.
Fig. 2 is a flowchart illustrating a contact hole forming method according to embodiment 1 of the present invention.
Fig. 3 is a cross-sectional view showing a first forming step of a contact hole according to embodiment 1 of the present invention.
Fig. 4 is a cross-sectional view showing a protective layer forming step according to embodiment 1 of the present invention.
Fig. 5 is a cross-sectional view showing a second forming process of a contact hole according to embodiment 1 of the present invention.
Fig. 6 is a cross-sectional view showing the semiconductor structure in the second forming step of the contact hole according to embodiment 3 of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the drawings, the same elements are denoted by the same reference numerals, and redundant description thereof is omitted. Further, the lateral chain line and the longitudinal chain line in each figure indicate that similar structures are omitted in the lateral direction and the longitudinal direction, respectively.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
[ method of Forming contact hole ]
Embodiment mode 1
Fig. 1 illustrates a cross-sectional view of a step region in a three-dimensional memory device according to the present invention. As shown in fig. 1, in a three-dimensional memory device, for example, a floating gate type three-dimensional NAND flash memory, there are a step area 100 and a substrate 230. The stepped region 100 is formed on the surface of the substrate 230.
In the stepped region 100, a first stepped region 10 and a second stepped region 20 are formed, and the first stepped region 10 is formed above the second stepped region 20. The first stepped region 10 has a stepped structure formed by alternately stacking dielectric layers 210 and conductive layers 220 in a stacking direction perpendicular to the surface of the stepped region 100. Likewise, the second stepped region 20 has a stepped structure formed by alternately stacking dielectric layers 210 and conductive layers 220 in a stacking direction perpendicular to the surface of the stepped region 100. In addition, a hard mask layer 200 is formed on the surface of the step region 100 to form a mask for forming a contact hole.
For convenience of description, fig. 1 illustrates the structure in which the first stepped region 10 and the second stepped region 20 have two dielectric layers 210 and two conductive layers 220, respectively, but the number of layers of the dielectric layers 210 and the conductive layers 220 is not limited thereto, and the number of layers may be one or more than three.
In the example of fig. 1, the middle step structures are omitted, and according to the depth of the step structures from the surface of the step area, the upper step structure in the step area 100 is used as the first step area, and the lowest step structure in the step area 100 is used as the second step area, but the number of the step structures included in the first step area and the second step area is not particularly limited, and may be selected according to the actual situation in the manufacturing process, for example, a plurality of step structures that are shallower from the surface of the step area are selected as the first step area, a plurality of step structures that are located below the first step area are selected as the second step area, as long as the second step area is located below the first step area.
The materials and formation methods of the dielectric layer 210 and the conductive layer 220 in the step area 100 shown in fig. 1 are not particularly limited, and materials and formation methods commonly used in the art may be used. For example, dielectric layer 210 may be formed using silicon oxide, and conductive layer 220 may be formed using tungsten.
Fig. 2 is a flowchart showing a contact hole forming method according to embodiment 1 of the present invention.
As shown in fig. 2, a semiconductor structure forming step (S101) is first performed, and in this step S101, the semiconductor structure shown in fig. 1 is formed.
Next, a first contact hole forming step (S102) is performed, in which step S102, a first step area contact hole 101 is formed in the first step area 10 corresponding to the conductive layer 220 of the first step area 10 by an etching process using a mask formed of the hard mask layer 200, and at the same time, a second step area contact hole 201 is formed in the second step area 20 corresponding to the conductive layer 220 of the second step area 20 until the first step area contact hole 101 contacts the conductive layer 220 in the step structure, that is, at least a part of the conductive layer 220 is consumed by etching.
Fig. 3 shows a cross-sectional view of the semiconductor structure obtained after the first formation process of the contact hole. As shown in fig. 3, two first-step-region contact holes 101 and two second-step-region contact holes 201 are formed in the first step region and the second step region, respectively, through the contact-hole first forming process. The two first step area contact holes 101 are in contact with the corresponding conductive layers 220, i.e., at least a portion of the conductive layers 220 is consumed by etching. In addition, the two second step region contact holes 201 are formed to a depth deeper than the depth of the two first step region contact holes 101.
In the example of fig. 3, two contact holes are formed in the first step region and the second step region, respectively, but the number of contact holes is not limited to this, and the number of contact holes formed in step S102 may be one or three or more depending on the number of steps included in the first step region and the second step region.
In addition, in the example shown in fig. 3, an example in which the contact hole is formed by using an etching process is shown, but the manner of forming the contact hole is not limited thereto, and other methods commonly used in the art may be used. In this example, a plasma dry etching process having a good anisotropy is used, but the etching process is not limited thereto, and other etching processes commonly used in the art may be used.
Next, a protective layer forming step (S103) is performed, and in this step S103, a protective layer 2210 is further deposited and formed on the surface of the hard mask layer 200 remaining after the step S102 by a deposition process.
Fig. 4 shows a cross-sectional view of the semiconductor structure obtained after the protective layer forming process. As shown in fig. 4, by controlling the time when the deposition process is performed, the sidewalls and the bottom surfaces of the two first-mesa region contact holes 101 of the first-mesa region are covered with the protection layer 2210. Since the deposition conditions are the same and the depth of the second-mesa region contact hole 201 of the second-mesa region is deeper than that of the first-mesa region contact hole 101, accordingly, only a part of the sidewalls of the two second-mesa region contact holes 201 of the second-mesa region is covered with the protection layer 2210, while the bottom surface of the second-mesa region contact hole 201 is not covered with the protection layer 2210 or the covered protection layer 2210 is very thin. Here, fig. 4 shows only an example in which the bottom surface of the second stepped region contact hole 201 is not covered with the protective layer 2210.
In addition, in order to ensure that etching Through (Punch Through) does not occur at the bottom surface of the first stepped region contact hole 101 in the next process, the thickness of the protection layer 2210 is determined according to the number of stepped structures included in the stepped region 100. This thickness can be achieved by controlling the time of the deposition process.
In the example of fig. 4, an example of forming the protection layer 2210 by a deposition process is shown, but the manner of forming the protection layer 2210 is not limited thereto, and other methods commonly used in the art may also be used. In this example, as the deposition process, chemical vapor deposition, physical vapor deposition, or atomic layer deposition is used, but the deposition process is not limited thereto, and other deposition processes commonly used in the art may be used.
The material of the protective layer 2210 formed in the protective layer forming step (S103) may be a conductive material or a non-conductive material. Preferably, a conductive material such as a metal or metal silicide is used. The material of the protection layer 2210 may be the same as that of the conductive layer 220, for example, tungsten is used, or may be different from that of the conductive layer 220, for example, tungsten silicide is used.
Finally, a second contact hole forming process (S104) is performed, in which in the process S104, etching is continued using the same mask as in the process S102, and the protective layer is consumed until the bottom surface of the second step region contact hole 201 comes into contact with the conductive layer 220 in the second step region step structure.
Fig. 5 illustrates a cross-sectional view of the semiconductor structure obtained after the second forming process of the contact hole. As shown in FIG. 5, the passivation layer 2210 on the sidewalls and bottom surfaces of the two first-level-region contact holes 101 of the first level-region are consumed by etching, and no etching through occurs. In contrast, the protection layer 2210 on the sidewalls of the two second-level-region contact holes 201 of the second level-region is also consumed by etching, and through further etching, both the two second-level-region contact holes 201 are in contact with the conductive layer 220 of the second level-region, with a sufficient over-etching depth, ensuring reliability of electrical performance. As described above, according to the contact hole forming method shown in fig. 2, a contact hole having a sufficient over-etching depth and high reliability can be formed in the step region of the three-dimensional memory device having a multi-step structure using the same mask, thereby greatly reducing the number of masks and reducing the production cost.
In addition, according to the contact hole forming method shown in fig. 2, even if the number of step layers in the step region of the three-dimensional memory device continues to increase, the number of masks does not need to be increased, the production period is greatly shortened, and the production cost is further reduced.
In addition, according to the contact hole forming method shown in fig. 2, since only one mask needs to be used in the whole contact hole forming process, the deviation of the whole manufacturing process is reduced, the reliability of the electrical performance of the three-dimensional memory device is increased, and the yield of the final product is improved.
Embodiment mode 2
The contact hole forming method according to embodiment 2 differs from embodiment 1 in that:
in the first contact hole forming step (S102) of embodiment 1, the first step area contact hole 101 corresponding to the conductive layer 220 of the first step area 10 and the second step area contact hole 201 corresponding to the conductive layer 220 of the second step area 20 are formed on the first step area 10 and the second step area 20 until the first step area contact hole 101 comes into contact with the conductive layer 220 in the step structure, that is, at least a part of the conductive layer 220 is consumed by etching.
In contrast, in the first contact hole forming step (S102) of embodiment 2, the first step area contact hole 101 corresponding to the conductive layer 220 of the first step area 10 and the second step area contact hole 201 corresponding to the conductive layer 220 of the second step area 20 are formed on the first step area 10 and the second step area 20 until the first step area contact hole 101 is located above the conductive layer 220 in the step structure, that is, the conductive layer 220 is not consumed by etching (not shown).
Accordingly, in the second contact hole forming process (S104) of embodiment 2, etching is continued using the same mask as in the process S102, and the protective layer is consumed, so that the second step area contact hole 201 is brought into contact with the conductive layer 220 in the second step area step structure, and at the same time, the first step area contact hole 101 is brought into contact with the conductive layer 220 in the first step area step structure.
Other steps in embodiment 2 are similar to those in embodiment 1, and the same effects as those in embodiment 1 can be obtained by the contact hole forming method in embodiment 2.
Embodiment 3
Fig. 6 shows a cross-sectional view of the semiconductor structure obtained after the second formation process of the contact hole in embodiment 3. Embodiment 3 differs from embodiments 1 and 2 in that only an example in which the protective layer 2210 of the side wall of the first stepped region contact hole 101 and the protective layer 2210 of the side wall of the second stepped region contact hole 201 are completely consumed is shown in fig. 5 of embodiments 1 and 2, but is not limited thereto.
In embodiment 3, as shown in FIG. 6, after the second contact hole forming process, the protective layer 2210 is not completely consumed, so that the protective layer 2210 remains on at least a portion of the sidewalls of the first and second step-area contact holes 101 and 201.
Although not shown, when the protective layer 2210 is made of a conductive material, the protective layer 2210 may remain on the bottom surface of the first land contact hole 101.
Thus, according to the method for forming a contact hole in embodiment 3, the same effects as those in embodiments 1 and 2 can be obtained, and in addition, the process difficulty can be reduced in the actual process without affecting the electrical performance of the final semiconductor device.
[ three-dimensional memory device ]
In embodiment mode 3, a three-dimensional memory device having the following structure can be obtained by further filling the formed contact hole with the filler 300 for conductive contact.
As shown in fig. 6, the three-dimensional memory device includes: a step region including a first step region 10 and a second step region 20 located below the first step region 10, each of the first step region 10 and the second step region 20 including a plurality of step structures, the step structures being formed by alternately stacking at least one dielectric layer 210 and at least one conductive layer 220; a first stepped region conductive contact formed on the conductive layer 220 of the first stepped region 10 and contacting the conductive layer 220 of the first stepped region 10 corresponding thereto, at least a portion of the first stepped region conductive contact including a filler 300 as a first material layer and a protection layer 2210 as a second material layer, the protection layer 2210 being of a material different from the filler 300; and a second stepped region conductive contact formed on the conductive layer 220 of the second stepped region 20 and in contact with the conductive layer 220 of its corresponding second stepped region 20.
Preferably, the filler 300 is composed of a conductive material.
Preferably, the filler 300 is in contact with the conductive layer 220 of the corresponding first stepped region 10, and the protection layer 2210 is formed on the sidewall of the filler 300.
In addition, although not illustrated, in a case where the protection layer 2210 is also composed of a conductive material, the protection layer 2210 may be formed on the side wall and the bottom surface of the filler 300, and the protection layer 2210 is in contact with the conductive layer 220 of the corresponding first stepped region 10.
In addition, the three-dimensional memory device having the above structure is, for example, a floating gate type three-dimensional NAND memory or a charge trap type three-dimensional NAND memory.
Other details regarding the three-dimensional memory device, such as the structure of the memory array, the periphery interconnections, etc., are not material to the present invention and will not be described herein.
This application uses specific words to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.
Although the present invention has been described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (8)

1. A contact hole forming method for forming a contact hole of a step region in a three-dimensional memory device, comprising the steps of:
a semiconductor structure forming procedure, wherein the semiconductor structure is provided with a step area, the step area comprises a first step area and a second step area positioned below the first step area, the first step area and the second step area respectively comprise a plurality of step structures, and the step structures are formed by alternately stacking at least one dielectric layer and at least one conducting layer;
a first step area contact hole corresponding to the conductive layer of the first step area and a second step area contact hole corresponding to the conductive layer of the second step area are formed on the first step area and the second step area, wherein the first step area contact hole is in contact with the conductive layer of the corresponding first step area or is positioned above the conductive layer of the corresponding first step area, and the second step area contact hole is positioned above the conductive layer of the corresponding second step area;
a protective layer forming step of forming a protective layer on the side wall and the bottom surface of the first step region contact hole; and
and a second contact hole forming step of, when the side wall and the bottom surface of the first step area contact hole have the protective layer, bringing the second step area contact hole into contact with the conductive layer of the second step area corresponding thereto, or bringing the first step area contact hole into contact with the conductive layer of the first step area corresponding thereto while bringing the second step area contact hole into contact with the conductive layer of the second step area corresponding thereto.
2. The contact hole forming method according to claim 1,
in the contact hole first forming step, the second step area contact hole is formed to a depth greater than that of the first step area contact hole.
3. The contact hole forming method according to claim 1,
in the protective layer forming step, a protective layer is further formed on at least a partial region of the sidewall of the second step region contact hole, and the protective layer is not formed on the bottom surface of the second step region contact hole.
4. The contact hole forming method according to claim 1,
in the contact hole first forming step, a depth of the first step region contact hole is determined according to the number of the step structures included in the step region.
5. The contact hole forming method according to claim 1,
in the protective layer forming step, the thickness of the protective layer is determined according to the number of the step structures included in the step region.
6. The contact hole forming method according to claim 1,
in the first forming process of the contact hole and the second forming process of the contact hole, the same mask is used.
7. The contact hole forming method according to claim 1,
the protective layer is composed of a conductive material.
8. The contact hole forming method according to claim 7,
the protective layer is made of metal or metal silicide.
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