CN108807381B - Finfet器件及其制造方法 - Google Patents
Finfet器件及其制造方法 Download PDFInfo
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- CN108807381B CN108807381B CN201711351246.3A CN201711351246A CN108807381B CN 108807381 B CN108807381 B CN 108807381B CN 201711351246 A CN201711351246 A CN 201711351246A CN 108807381 B CN108807381 B CN 108807381B
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- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 201
- 238000000034 method Methods 0.000 claims abstract description 85
- 239000000463 material Substances 0.000 claims abstract description 68
- 230000005669 field effect Effects 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000002955 isolation Methods 0.000 claims description 43
- 150000004767 nitrides Chemical class 0.000 claims description 43
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 34
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 31
- 229910052710 silicon Inorganic materials 0.000 claims description 31
- 239000010703 silicon Substances 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 17
- 230000003647 oxidation Effects 0.000 claims description 16
- 238000007254 oxidation reaction Methods 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 239000000203 mixture Substances 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 11
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 388
- 229920002120 photoresistant polymer Polymers 0.000 description 24
- 230000008901 benefit Effects 0.000 description 11
- 238000005137 deposition process Methods 0.000 description 10
- 238000005530 etching Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000011161 development Methods 0.000 description 5
- 239000003570 air Substances 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 238000007517 polishing process Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000012080 ambient air Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/1025—Channel region of field-effect devices
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- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
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Abstract
一种半导体器件包括P型场效应晶体管(PFET)和NFET。PFET包括设置在衬底中的N阱、设置在N阱上方的第一鳍结构、设置在N阱上方的第一衬垫层以及设置在第一衬垫层上方的第二衬垫层。第一衬垫层和第二衬垫层包括不同的材料。NFET包括设置在衬底中的P阱、设置在P阱上方的第二鳍结构、设置在P阱上方的第三衬垫层。第三衬垫层和第二衬垫层包括相同的材料。本发明实施例涉及FINFET器件及其制造方法。
Description
技术领域
本发明实施例涉及FINFET器件及其制造方法。
背景技术
为了追求更高的器件密度、更高的性能和更低的成本,半导体产业已经发展到纳米技术工艺节点。随着这种进展的发生,来自制造和设计问题的挑战已经导致诸如鳍式场效应晶体管(FinFET)器件的三维设计的发展。利用从衬底延伸的薄的“鳍”(或鳍状结构)制造典型的FinFET器件。鳍通常包括硅并形成晶体管器件的主体。在这个垂直的鳍中形成晶体管的沟道。在鳍上方(例如,包裹在鳍周围)提供栅极。这种类型的栅极允许更好地控制沟道。FinFET器件的其他优势包括降低的短沟道效应和较高的电流。
然而,传统FinFET器件仍然可能具有特定的缺陷。例如,用于传统的FinFET器件的浅沟槽隔离(STI)衬垫还没有配置为优化FinFET器件的性能。
因此,尽管现有的FinFET器件及其制造通常已经足够用于其预期的目的,但是还没有在各个方面完全令人满意。
发明内容
根据本发明的一些实施例,提供了一种半导体器件,包括:P型场效应晶体管(PFET),包括:N阱,设置在衬底中;隔离结构,设置在所述N阱上方;第一鳍结构,设置在所述N阱上方,其中,所述第一鳍结构包括下部区段和设置在所述下部区段上方的上部区段,并且其中,所述下部区段设置在所述隔离结构的上表面下方;第一衬垫层,设置在所述N阱上方和所述第一鳍结构的下部区段的侧壁上;以及第二衬垫层,设置在所述第一衬垫层上方,其中,所述第一衬垫层和所述第二衬垫层包括不同的材料;以及N型场效应晶体管(NFET),包括:P阱,设置在所述衬底中;隔离结构,设置在所述P阱上方;第二鳍结构,设置在所述P阱上方,其中,所述第二鳍结构包括下部区段和设置在所述下部区段上方的上部区段,并且其中,所述下部区段设置在所述隔离结构的上表面下方;以及第三衬垫层,设置在所述P阱上方和所述第二鳍结构的下部区段的侧壁上,其中,所述第三衬垫层和所述第二衬垫层包括相同的材料。
根据本发明的另一些实施例,提供了一种FinFET器件,包括:P型场效应晶体管(PFET),包括:N阱,形成在衬底中,其中,所述N阱包括第一部分和突出于所述第一部分的第二部分;第一半导体层,位于所述N阱的第二部分上方,其中,所述第一半导体层包括硅锗,并且其中,所述N阱的第二部分和所述第一半导体层是所述P型场效应晶体管的第一鳍结构的部分;第一衬垫层,位于所述N阱的第一部分上方和所述N阱的第二部分的侧壁上方,但不位于所述第一半导体层上方,其中,所述第一衬垫层包括防止所述硅锗被氧化的材料;以及第二衬垫层的第一区段,位于所述第一衬垫层上方,其中,所述第二衬垫层包括对硅产生应力的材料;以及N型场效应晶体管(NFET),包括:P阱,形成在所述衬底中,其中,所述P阱包括第一部分和突出于所述第一部分的第二部分;第二半导体层,位于所述P阱的第二部分上方,其中,所述第二半导体层包括硅,并且其中,所述P阱的第二部分和所述第二半导体层是所述N型场效应晶体管的第二鳍结构的部分;以及所述第二衬垫层的第二区段,位于所述P阱的第一部分上方和所述P阱的第二部分的侧壁上,但不位于所述第二半导体层上方。
根据本发明的又一些实施例,还提供了一种制造半导体器件的方法,所述方法包括:在N阱上方形成第一半导体层;在P阱上方形成第二半导体层;实施图案化工艺以形成第一鳍结构和第二鳍结构,其中,所述第一鳍结构包括所述第一半导体层的部分和所述N阱的部分,并且所述第二鳍结构包括所述第二半导体层的部分和所述P阱的部分;在所述第一鳍结构、所述N阱、所述第二鳍结构和所述P阱上方形成第一衬垫层;选择性地去除所述第一衬垫层,从而去除形成在所述第二鳍结构和所述P阱上方的所述第一衬垫层,其中,形成在所述第一鳍结构和所述N阱上方的所述第一衬垫层的剩余部分不受选择性地去除的影响;以及在选择性地去除所述第一衬垫层之后,在所述第二鳍结构、所述P阱和所述第一衬垫层的剩余部分上方形成第二衬垫层,其中,所述第二衬垫层和所述第一衬垫层具有不同的材料组成。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1是示例性FinFET器件的立体图。
图2至图17是根据本发明的各个实施例的在不同制造阶段处的FinFET器件的截面侧视图。
图18是根据本发明的实施例的用于制造FinFET器件的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为了便于描述,在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。例如,如果翻转附图中的器件,则描述为在其他元件或特征“下方”或“下面”的元件将定向为在其他元件或部件“之上”。因此,示例性术语“在...下面”可以包括之上和下面的方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且在此使用的空间相对描述符可以同样地作出相应的解释。
本发明涉及,但不限于,鳍式场效应晶体管(FinFET)器件。FinFET器件例如可以是包括P型金属氧化物半导体FinFET器件和N型金属氧化物半导体FinFET器件的互补金属氧化物半导体(CMOS)器件。下面的公开将继续利用一个或多个FinFET实例以示出本发明的各个实施例。然而,应该理解,除非另有明确说明,否则该应用不应限制于特定类型的器件。
FinFET器件的使用在半导体产业已经越来越受欢迎。参考图1,示出示例性FinFET器件50的立体图。FinFET器件50是构建在衬底(诸如块状衬底)上方的非平面多栅极晶体管。薄的含硅“鳍状”结构(在下文中称为“鳍”)形成FinFET器件50的主体。鳍沿着图1所示的X方向延伸。鳍具有沿着与X方向正交的Y方向测量的鳍宽度W鳍。FinFET器件50的栅极60包裹在该鳍周围,例如包裹在鳍的顶面和相对的侧壁表面周围。因此,在与X方向和Y方向都正交的Z方向上,栅极60的部分位于鳍上方。
LG表示在X方向上测量的栅极60的长度(或宽度,取决于视角)。栅极60可以包括栅电极组件60A和栅极介电组件60B。栅极介电组件60B具有在Y方向上测量的厚度tox。栅极60的部分位于诸如浅沟槽隔离(STI)的介电隔离结构上方。FinFET器件50的源极70和漏极80形成在位于栅极60的相对侧上的鳍的延伸件中。鳍的由栅极60包裹环绕的部分用作FinFET器件50的沟道。由鳍的尺寸确定FinFET器件50的有效沟道长度。
与传统的金属氧化物半导体场效应晶体管(MOSFET)器件(还称为平面晶体管器件)相比,FinFET器件提供了若干优势。这些优势可以包括更好的芯片面积效率、改善的载流子迁移率、以及与平面器件的制造处理兼容的制造处理。FinFET器件也与高k金属栅极(HKMG)工艺流程兼容。因此,FinFET器件可以实现为HKMG器件,其中,每个栅极均具有高k栅极电介质和金属栅电极。对于上面讨论的这些益处,期望设计对于部分或整个IC芯片而言,使用FinFET器件的集成电路(IC)芯片。
然而,传统的FinFET制造方法可能仍然存在缺陷。例如,传统的FinFET制造可以使用相同类型的浅沟槽隔离(STI)衬垫材料,从而用于NFET和PFET。这种方法不会优化FinFET晶体管的性能。为了改善FinFET器件的性能,本发明利用双STI衬垫方法来同时改善NFET和PFET的性能,如下面参考图2-图18更详细讨论的。
图2-图17是在各个制造阶段处的FinFET器件100的示意性局部截面侧视图。参考图2,FinFET器件100包括均形成在衬底中的N阱110和P阱120。衬底可以是例如硅衬底的半导体衬底。N阱110和P阱120可以使用一个或多个离子注入工艺来形成并且被不同地掺杂,以便具有不同类型的导电性。在一些实施例中,掺杂剂离子可以包括例如砷(As)或磷(P)的n型材料,或者在一些其他实施例中,它们可以包括例如硼(B)的p型材料,这取决于需要NFET还是PFET。
在N阱110上方且在P阱120上方形成半导体层130。在一些实施例中,半导体层130包括硅。可以使用外延生长工艺在N阱110和P阱120上方生长半导体层130的硅材料。半导体层130生长为具有厚度140。在一些实施例中,厚度140在约30纳米(nm)和约70nm之间的范围内。如下面将更详细讨论的,半导体层130的部分(在经历图案化工艺之后)将用作鳍,从而用于FinFET器件100的NFET(也称为NMOS)。
现在参考图3,在半导体层130上方形成介电层150。在一些实施例中,介电层150包括例如氧化硅的氧化物材料。可以使用诸如化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)或它们的组合的沉积工艺来形成介电层150。介电层150形成为具有厚度160。在一些实施例中,厚度160在约10nm和约20nm之间的范围内。在下面讨论的图案化工艺中介电层150将用作硬掩模。
现在参考图4,在介电层150上方形成图案化的光刻胶层170。在一些实施例中,通过诸如光刻胶涂覆(例如,光刻胶旋涂)、曝光、曝光后烘烤、显影和清洗的一个或多个工艺来形成图案化的光刻胶层170。在显影之后,由光刻胶材料的剩余部分形成图案化的光刻胶层170。如图4所示,在P阱120上方但不在N阱110上方形成图案化的光刻胶层170。换言之,图案化的光刻胶层170与P阱120垂直地对准(例如,在图1所示的Z方向上),但不与N阱110垂直地对准。
现在参考图5,由图案化的光刻胶层170图案化介电层150,从而形成图案化的硬掩模150A。然后例如使用光刻胶剥离工艺或光刻胶灰化工艺去除图案化的光刻胶层170。使用图案化的硬掩模150A作为保护掩模,然后实施蚀刻工艺以蚀刻掉半导体层130的部分。换言之,图案化的硬掩模150A在蚀刻工艺期间保护其下面的半导体层130的部分130B不被蚀刻,而去除半导体层130的未被图案化硬掩模150A保护的部分。
如图5所示,以使得半导体层130的部分130A仍然保留在N阱110上的方式实施蚀刻工艺。因为部分130A是层130的部分,所以部分130A和半导体层130的剩余部分具有相同的材料组成(例如,它们都含有Si)。半导体层130的部分130A形成为具有厚度190。在一些实施例中,厚度190在约2nm和约8nm之间的范围内。保留半导体层130的部分130A的原因之一是为了在稍后的工艺中更好地外延生长硅锗材料。例如,半导体层130的部分130A有助于将N阱110与稍后将在半导体层130上方生长的硅锗材料隔离。
现在参考图6,在半导体层130的部分130A上方形成半导体层200。半导体层200具有与半导体层130不同的材料组成。例如,在一些实施例中,半导体层200包括硅锗(SiGe)。可以使用外延生长工艺来生长半导体层200。如上所述,由于存在半导体层130的部分130A,半导体层200不直接形成在N阱110上,而是形成在半导体层130的部分130A上。半导体层130的部分130A在N阱110和半导体层200之间提供隔离,并且允许半导体层200形成为具有更好的外延生长质量。半导体层200形成为具有厚度210。在一些实施例中,厚度210在从约40nm至约60nm的范围内。如将在下面更详细讨论的,半导体层200将用作FinFET器件100的PFET(也称为PMOS)的鳍。
现在参考图7,例如使用诸如化学机械抛光(CMP)的抛光工艺去除图案化的硬掩模150A。CMP工艺还可以去除半导体层200的小部分和半导体层130的部分130B的小部分。作为抛光工艺的结果,FinFET器件100现在具有大致平坦的或平坦化的上表面220。
现在参考图8,在半导体层200和130B的平坦化的上表面220上形成覆盖层230。在一些实施例中,覆盖层230包括硅并且可以称为硅覆盖层。覆盖层230形成为具有厚度240。在一些实施例中,厚度240在从约0.5nm至约5nm的范围内。覆盖层230保护半导体层200免受不期望的氧化。例如,如果暴露于环境空气(其含有氧),则半导体层200中的硅锗材料容易被氧化,这是不期望的,因为其可能不利地影响硅锗材料(例如,用作半导体材料)的预期功能。覆盖层230的形成防止半导体层200暴露在空气中,并且因此防止了半导体层200的硅锗材料的潜在氧化。将在之后的工艺中去除覆盖层230。
现在参考图9,在覆盖层230上方形成介电层270。在一些实施例中,介电层270包括氧化硅并且可以称为垫氧化物层270。然后在介电层270上方形成介电层280。在一些实施例中,介电层280包括氮化硅并且可以称为垫氮化物层280。介电层270和280可以用作后续的光刻图案化工艺的硬掩模的材料。
现在参考图10,实施OD(有源区)图案化工艺290以形成向上突出(例如,在图1的Z方向上向上)的鳍结构295。作为OD图案化工艺290的部分,可以图案化(例如,使用图案化的光刻胶层)介电层270和280以形成限定鳍结构295的横向尺寸的图案化的硬掩模。然后使用图案化的硬掩模270/280来图案化其下面的层。例如,在一个或多个蚀刻工艺中蚀刻掉未被图案化的掩模270/280保护的层230、200和130B以及N阱110和P阱120的部分。可以看出,蚀刻N阱110,从而使得其区段110A突出于未被蚀刻掉的区段110B,并且蚀刻P型阱120,从而使得其区段120A突出于未被蚀刻掉的区段120B。应当理解,区段110A和区段110B具有相同的材料组成,并且区段120A和区段120B具有相同的材料组成。然而,区段110A和110B之间以及区段120A和120B之间的掺杂浓度水平可能不同。例如,区段110B可以具有比区段110A更低的掺杂浓度水平,并且区段120B可以具有比区段120A更低的掺杂浓度水平。层230和200的剩余部分、部分130A以及N阱110A的向上突出的区段共同形成用于PFET的鳍结构295,并且半导体层130B的剩余部分和P阱120A的向上突出的区段共同形成用于NFET的鳍结构295。可以在鳍结构295中,例如在半导体层200和130B中形成NFET和PFET的沟道和源极/漏极区。
现在参考图11,实施沉积工艺300以在每个鳍结构295的顶面和侧面上形成含氮化物的衬垫层310。在一些实施例中,沉积工艺300包括沉积工艺温度范围在约550摄氏度和约950摄氏度之间的CVD工艺。例如,在PFET中,在半导体层200的侧壁表面上并且在N阱110的区段110A的侧壁表面上形成含氮化物的衬垫层310。在一些实施例中,含氮化物的衬垫层310与半导体层200的侧壁表面以及N阱110的区段110A的侧壁表面直接物理接触。在一些实施例中,含氮化物的衬垫层310可以包括氮化硅材料。含氮化物的衬垫层310形成为具有厚度320。在一些实施例中,沉积工艺300配置为使得厚度320在从约2nm至约5nm的范围内。
衬垫层310的氮化硅材料防止半导体层200的硅锗材料暴露于空气中的氧气。如上所述,硅锗容易发生不期望的氧化。在实施上面参考图10讨论的OD图案化工艺290之后,暴露鳍结构295中的半导体层200(包括硅锗)的侧壁。如果不采取其他措施,半导体层200暴露于空气会氧化半导体层200中的硅锗,从而降低器件性能。
为了抑制半导体层200的氧化,本发明在半导体层200的侧壁上形成含氮化物的衬垫层310(例如,含有氮化硅)以防止半导体层200暴露于空气中。含氮化物的衬垫层310的存在因此降低了半导体层200的不期望的氧化的可能性。厚度320的范围也配置为优化含氮化物的衬垫层310的功能,例如相对于防止半导体层200的氧化。应当理解,虽然氮化硅用作含氮化物的衬垫层310的实例,但是也可以使用其他合适的材料,只要这些材料适合于防止半导体层200的硅锗的氧化。
注意,还在用于NFET的鳍结构295上形成含氮化物的衬垫层310。然而,这不是必须的,并且因此在稍后的工艺中去除用于NFET的含氮化物的衬垫层310。
现在参考图12,形成图案化的光刻胶层330以覆盖FinFET器件100的PFET,同时暴露留下的NFET。换言之,在形成在N阱110B上方的鳍结构295上方形成图案化的光刻胶层330,但不在形成在P阱120B上方的鳍结构295上方形成图案化的光刻胶层330。如此,通过图案化的光刻胶层330覆盖PFET的含氮化物的衬垫层310的区段,同时暴露NFET的含氮化物的衬垫层310的区段。可以通过诸如沉积、曝光、显影、烘烤等的工艺(不一定按照该顺序实施)来形成图案化的光刻胶层330。
现在参考图13,对FinFET器件100实施蚀刻工艺350以去除含氮化物的衬垫层310的设置在FinFET器件100的NFET区中的部分。在蚀刻工艺350期间,图案化的光刻胶层330保护位于其下面的含氮化物的衬垫层310免受蚀刻。如此,PFET中的含氮化物的衬垫层310的部分保持完整并且不通过蚀刻工艺350去除。然而,由于设置在NFET中的含氮化物的衬垫层310的部分未被图案化的光刻胶330保护,因此对于NFET,去除含氮化物的衬垫层310,由此暴露NFET的鳍结构295的上表面和侧壁表面。例如,暴露半导体层130B的侧壁表面以及P阱的区段120A的侧壁表面。
现在参考图14,例如使用光刻胶剥离工艺或光刻胶灰化工艺去除图案化的光刻胶层330。去除图案化的光刻胶层330,使得含氮化物的衬垫层310(覆盖PFET中的鳍结构295)暴露。
现在参考图15,实施沉积工艺400以在每个鳍结构295的顶面和侧面上形成含氧化物的衬垫层410。在一些实施例中,沉积工艺400包括沉积工艺的温度范围在约550摄氏度和约950摄氏度之间的CVD工艺。例如,在PFET中,在含氮化物的衬垫层310上形成含氧化物的衬垫层410。在一些实施例中,含氧化物的衬垫层410直接物理接触含氮化物的衬垫层310。在NFET中,在半导体层130B的侧壁表面上且在P阱120的区段120A的侧壁表面上形成含氧化物的衬垫层410。在一些实施例中,含氧化物的衬垫层410直接物理接触半导体层130B的侧壁表面并且直接物理接触P阱120的区段120A的侧壁表面。
在一些实施例中,含氧化物的衬垫层410可以包括氧化硅材料。在一些其他实施例中,含氧化物的衬垫层410可以包括氧化铝材料。含氧化物的衬垫层410形成为具有厚度420。在一些实施例中,沉积工艺300配置为使得厚度420在从约2nm至约5nm的范围内。
衬垫层410的氧化硅材料导致应力。例如,由于NFET的沟道将形成在半导体层130B中,所以衬垫层410与半导体层130B的接近(例如,直接物理接触)可能对NFET的沟道产生拉伸应力。被施加应力的沟道可能会导致性能改善,诸如载流子迁移率提高,并且因此可能是期望的。虽然诸如含氮化物的衬垫310的氮化物衬垫也可能对NFET的沟道产生一些应力(如果已将用于NFET的含氮化物的衬垫310用于替换含氧化物的衬垫层410),则氮化物材料可能不会像氧化物那样产生太多的压力。另外,氮化物材料可以是带正电的。正电荷可能会导致NFET太容易导通,这是不期望的。除此之外,如果NFET太容易导通,可能会导致高泄漏。因此,期望NFET附近的衬垫层是中性的(例如,不带电荷)或具有负电荷。
由于上面讨论的这些原因,含氧化物的衬垫层410的材料组成配置为在中性或带正电的同时对NFET的沟道产生应力。氧化硅材料或氧化铝材料组成可以满足这些条件,并且因此,在各个实施例中,含氧化物的衬垫层410可以包括氧化硅、氧化铝或它们的组合。注意,在图15所示的制造阶段处,在鳍结构295之间存在多个间隙或沟槽450。将在稍后讨论的工艺中填充这些间隙或沟槽450。
现在参考图16,例如通过诸如炉化学汽相沉积(FCVD)的沉积工艺来形成介电隔离结构500。介电隔离结构500形成为填充鳍结构295之间的间隙或沟槽450。在一些实施例中,介电隔离结构500可以包括浅沟槽隔离(STI)。介电隔离结构500可以包括例如氧化硅的氧化物材料。在形成介电隔离结构500之前或之后,可以实施诸如CMP工艺的抛光工艺以去除介电层270和280(以及介电隔离结构500的部分)。抛光工艺还可以去除PFET的鳍结构295中的覆盖层230。
现在参考图17,对FinFET器件100实施鳍凹进工艺600,以选择性地去除用于PFET和NFET的含氧化物的衬垫层410的部分,并且选择性地去除用于PFET的含氮化物的衬垫层310的部分。更详细地,对于NFET,去除含氧化物的衬垫层410的部分,从而暴露半导体层130B,包括暴露其上表面及其侧壁表面。类似地,对于PFET,去除含氧化物的衬垫层410的部分以及含氮化物的衬垫层310的部分,从而暴露半导体层200,包括暴露其上表面及其侧壁表面。作为鳍凹进工艺600的部分,还去除介电隔离结构500的部分,以帮助暴露半导体层200和130B的侧面。
同时,鳍凹进工艺600配置为使得其基本不影响衬垫层310和410的未设置在半导体层200和130B上的部分。例如,在实施鳍凹进工艺600之后,含氮化物的衬垫层310的部分仍然保持设置在N阱的区段110A和130A的侧壁表面上以及N阱的区段110B的上表面上。含氧化物的衬垫层410的部分也保留在PFET中的含氮化物的衬垫层310上。对于NFET,含氧化物的衬垫层410的另一部分保持设置在P阱的区段120A的侧壁表面上以及P阱的区段120B的上表面上。在图17的截面图中,含氧化物的衬垫层410围绕介电隔离结构500的侧面和底面。由于本发明对于NFET和PFET使用不同的衬垫层,因此可以说本发明的FinFET器件100是“双衬垫”器件。
在一些实施例中,鳍凹进工艺600包括诸如干蚀刻、湿蚀刻、反应离子蚀刻(RIE)等的一个或多个蚀刻工艺。可以调整各个蚀刻参数以选择性地蚀刻掉衬垫层310和410的期望的量(例如,刚好足以暴露半导体层200和130B)。这些蚀刻参数可以包括但不限于:蚀刻剂组成、蚀刻温度、蚀刻溶液浓度、蚀刻时间、蚀刻压力、源功率、RF(射频)偏置电压、RF偏置功率、蚀刻剂流量或它们的组合。
图18是根据本发明的各个方面的用于制造FinFET器件的方法900的流程图。方法900包括在N阱上方形成第一半导体层的步骤910。在一些实施例中,形成第一半导体层包括在N阱上方外延生长硅锗作为第一半导体层。
方法900包括在P阱上方形成第二半导体层的步骤920。在一些实施例中,形成第二半导体层包括在P阱上方外延生长硅作为第二半导体层。在一些实施例中,在第一半导体层之前形成第二半导体层。在一些实施例中,实施硅的外延生长,从而使得在N阱和P阱两者上方生长硅。在一些实施例中,在形成第二半导体层之后但在形成第一半导体层之前,部分地去除位于N阱上方的第二半导体层。在部分地去除第二半导体层之后,在第二半导体层的位于N阱上方的剩余部分上方外延生长第一半导体层。
方法900包括实施图案化工艺以形成第一鳍结构和第二鳍结构的步骤930。第一鳍结构包括第一半导体层的部分和N阱的部分,并且第二鳍结构包括第二半导体层的部分和P阱的部分。
方法900包括在第一鳍结构、N阱、第二鳍结构和P阱上方形成第一衬垫层的步骤940。在一些实施例中,形成第一衬垫层包括形成含氮化物层作为第一衬垫层。在一些实施例中,含氮化物的衬垫层包括氮化硅。
方法900包括选择性地去除第一衬垫层,从而去除形成在第二鳍结构和P阱上方的第一衬垫层的步骤950。第一衬垫层的形成在第一鳍结构和N阱上方的剩余部分不受选择性去除的影响。
方法900包括在第二鳍结构、P阱和第一衬垫层的剩余部分上方形成第二衬垫层的步骤960。第二衬垫层和第一衬垫层具有不同的材料组成。在一些实施例中,形成第二衬垫层包括形成含氧化物层作为第二衬垫层。在一些实施例中,含氧化物层包括氧化硅。
在一些实施例中,方法900可以进一步包括去除形成在第一半导体层上方的第一衬垫层和第二衬垫层的部分以及去除形成在第二半导体层上方的第二衬垫层的部分的步骤。
应该理解,可以在上面讨论的步骤910-960之前、期间或之后实施额外的工艺步骤,以完成半导体器件的制造。例如,方法900可以进一步实施工艺以形成栅极结构。可以使用“先栅极”或“后栅极”工艺形成栅极结构。方法900可以进一步包括形成源极/漏极部件以及形成层间介电(ILD)层的步骤。此外,可以形成包括导电接触件、通孔和互连线的互连结构。另外,可以实施测试和封装步骤来完成集成电路的制造。
基于以上讨论,可以看出,本发明提供了优于传统的FinFET及其制造的优势。然而,应该理解,其他实施例可以提供额外的优势,并且不是所有的优势都必须在此公开,并且没有特定优势是所有实施例都需要的。一个优势是,通过使用含氮化物的衬垫,本发明可以减少或防止PFET的鳍中的硅锗材料的不期望的氧化。另一个优势是,通过使用含氧化物的衬垫,本发明可以增加对NFET的沟道的应力。含氧化物的衬垫也不具有正电荷,这意味着NFET不太容易导通。由于这些原因,FinFET器件性能得到改善。另外,本发明的各个方面与当前的制造工艺流程兼容且易于实施。
本发明的一个实施例涉及一种半导体器件。该半导体器件包括P型场效应晶体管(PFET),该P型场效应晶体管包括:设置在衬底中的N阱;设置在N阱上方的第一鳍结构;设置在N阱上方的第一衬垫层;以及设置在第一衬垫层上方的第二衬垫层,其中,第一衬垫层和第二衬垫层包括不同的材料。半导体器件还包括N型场效应晶体管(NFET),其中,该N型场效应晶体管包括:设置在衬底中的P阱;设置在P阱上方的第二鳍结构;以及设置在P阱上方的第三衬垫层,其中,第三衬垫层和第二衬垫层包括相同的材料。在一些实施例中,第一鳍结构包括硅锗层;第二鳍结构包括硅层;第一衬垫层包括配置为防止硅锗层被氧化的材料;并且第二衬垫层包括配置为对NFET提供应力的材料。在一些实施例中,第一衬垫层包括含氮化物的材料;第二衬垫层包括含氧化物的材料;并且第三衬垫层包括含氧化物的材料。在一些实施例中,第一衬垫层包括氮化硅;并且第二衬垫层和第三衬垫层均包括氧化硅。在一些实施例中,第一衬垫层和第二衬垫层的任何部分都不设置在硅锗层的侧壁上;并且第三衬垫的任何部分都不设置在硅层的侧壁上。在一些实施例中,第一衬垫层的部分设置在N阱的侧面上;并且第二衬垫层的部分设置在P阱的侧面上。在一些实施例中,半导体器件还包括:位于PFET和NFET之间的介电隔离结构,其中,在截面侧视图中,第二衬垫层和第三衬垫层围绕介电隔离结构。
本发明的另一实施例涉及FinFET器件。FinFET器件包括P型场效应晶体管(PFET),其中,P型场效应晶体管包括:形成在衬底中的N阱,其中,N阱包括第一部分和突出于第一部分的第二部分;位于N阱的第二部分上方的第一半导体层,其中,第一半导体层包括硅锗;位于N阱上方但不位于第一半导体层上方的第一衬垫层,其中,第一衬垫层包括防止硅锗被氧化的材料;以及位于第一衬垫层上方的第二衬垫层的第一区段,其中,第二衬垫层包括对硅施加应力的材料。FinFET器件还包括N型场效应晶体管(NFET),其中,N型场效应晶体管包括:形成在衬底中的P阱,其中,P阱包括第一部分和突出于第一部分的第二部分;位于P阱的第二部分上方的第二半导体层,其中,第二半导体层包括硅;以及位于P阱上方但不位于第二半导体层上方的第二衬垫层的第二区段。在一些实施例中,第一衬垫层包括氮化硅,并且第二衬垫层的第一区段和第二区段均包括氧化硅。在一些实施例中,第一衬垫层与N阱的第一部分的侧壁直接物理接触,并且第二衬垫层的第二区段与P阱的第一部分的侧壁直接物理接触。在一些实施例中,FinFET器件还包括:位于PFET和NFET之间的介电隔离结构。介电隔离结构与第二衬垫层的第一区段和第二区段两者直接物理接触。
本发明的另一实施例涉及一种制造半导体器件的方法。该方法包括:在N阱上方形成第一半导体层;在P阱上方形成第二半导体层;实施图案化工艺以形成第一鳍结构和第二鳍结构,其中,第一鳍结构包括第一半导体层的部分和N阱的部分,并且第二鳍结构包括第二半导体层的部分和P阱的部分;在第一鳍结构、N阱、第二鳍结构和P阱上方形成第一衬垫层;选择性地去除第一衬垫层,从而去除形成在第二鳍结构和P阱上方的第一衬垫层,其中,形成在第一鳍结构和N阱上方的第一衬垫层的剩余部分不受选择性地去除的影响;并且在选择性地去除第一衬垫层之后,在第二鳍结构、P阱以及第一衬垫层的剩余部分上方形成第二衬垫层,其中,第二衬垫层和第一衬垫层具有不同的材料组成。在一些实施例中,该方法还包括以下步骤:去除形成在第一半导体层上方的第一衬垫层和第二衬垫层的部分,并去除形成在第二半导体层上方的第二衬垫层的部分。在一些实施例中,形成第一衬垫层包括形成含氮化物层作为第一衬垫层。在一些实施例中,含氮化物层包括氮化硅。在一些实施例中,形成第二衬垫层包括形成含氧化物层作为第二衬垫层。在一些实施例中,含氧化物层包括氧化硅。在一些实施例中,形成第一半导体层包括在N阱上方外延生长硅锗作为第一半导体层;并且形成第二半导体层包括在P阱上方外延生长硅作为第二半导体层。在一些实施例中,在第一半导体层之前形成第二半导体层;并且实施硅的外延生长,从而使得在N阱和P阱两者上生方长硅。在一些实施例中,该方法还包括以下步骤:在形成第二半导体层之后但在形成第一半导体层之前,部分地去除位于N阱上方的第二半导体层,其中,在部分地去除第二半导体层之后,在位于N阱上方的第二半导体层的剩余部分上方外延生长第一半导体层。
根据本发明的一些实施例,提供了一种半导体器件,包括:P型场效应晶体管(PFET),包括:N阱,设置在衬底中;隔离结构,设置在所述N阱上方;第一鳍结构,设置在所述N阱上方,其中,所述第一鳍结构包括下部区段和设置在所述下部区段上方的上部区段,并且其中,所述下部区段设置在所述隔离结构的上表面下方;第一衬垫层,设置在所述N阱上方和所述第一鳍结构的下部区段的侧壁上;以及第二衬垫层,设置在所述第一衬垫层上方,其中,所述第一衬垫层和所述第二衬垫层包括不同的材料;以及N型场效应晶体管(NFET),包括:P阱,设置在所述衬底中;隔离结构,设置在所述P阱上方;第二鳍结构,设置在所述P阱上方,其中,所述第二鳍结构包括下部区段和设置在所述下部区段上方的上部区段,并且其中,所述下部区段设置在所述隔离结构的上表面下方;以及第三衬垫层,设置在所述P阱上方和所述第二鳍结构的下部区段的侧壁上,其中,所述第三衬垫层和所述第二衬垫层包括相同的材料。
在上述半导体器件中,所述第一鳍结构包括硅锗层;所述第二鳍结构包括硅层;所述第一衬垫层包括配置为防止所述硅锗层被氧化的材料;以及所述第二衬垫层包括配置为对所述N型场效应晶体管提供应力的材料。
在上述半导体器件中,所述第一衬垫层包括含氮化物的材料;所述第二衬垫层包括含氧化物的材料;以及所述第三衬垫层包括含氧化物层的材料。
在上述半导体器件中,所述第一衬垫层包括氮化硅;以及所述第二衬垫层和所述第三衬垫层均包括氧化硅。
在上述半导体器件中,所述第一衬垫层和所述第二衬垫层的任何部分都不设置在所述硅锗层的侧壁上;以及所述第三衬垫层的任何部分都不设置在所述硅层的侧壁上。
在上述半导体器件中,所述第一衬垫层的部分设置在所述N阱的侧面上;以及所述第二衬垫层的部分设置在所述P阱的侧面上。
在上述半导体器件中,所述隔离结构包括浅沟槽隔离(STI),并且其中,在截面侧视图中,所述第二衬垫层和所述第三衬垫层围绕所述浅沟槽隔离。
根据本发明的另一方面,提供了一种FinFET器件,包括:P型场效应晶体管(PFET),包括:N阱,形成在衬底中,其中,所述N阱包括第一部分和突出于所述第一部分的第二部分;第一半导体层,位于所述N阱的第二部分上方,其中,所述第一半导体层包括硅锗,并且其中,所述N阱的第二部分和所述第一半导体层是所述P型场效应晶体管的第一鳍结构的部分;第一衬垫层,位于所述N阱的第一部分上方和所述N阱的第二部分的侧壁上方,但不位于所述第一半导体层上方,其中,所述第一衬垫层包括防止所述硅锗被氧化的材料;以及第二衬垫层的第一区段,位于所述第一衬垫层上方,其中,所述第二衬垫层包括对硅产生应力的材料;以及N型场效应晶体管(NFET),包括:P阱,形成在所述衬底中,其中,所述P阱包括第一部分和突出于所述第一部分的第二部分;第二半导体层,位于所述P阱的第二部分上方,其中,所述第二半导体层包括硅,并且其中,所述P阱的第二部分和所述第二半导体层是所述N型场效应晶体管的第二鳍结构的部分;以及所述第二衬垫层的第二区段,位于所述P阱的第一部分上方和所述P阱的第二部分的侧壁上,但不位于所述第二半导体层上方。
在上述FinFET器件中,所述第一衬垫层包括氮化硅;以及所述第二衬垫层的第一区段和第二区段均包括氧化硅。
在上述FinFET器件中,所述第一衬垫层与所述N阱的第二部分的侧壁直接物理接触;以及所述第二衬垫层的第二区段与所述P阱的第二部分的侧壁直接物理接触。
在上述FinFET器件中,还包括:位于所述P型场效应晶体管和所述N型场效应晶体管之间的介电隔离结构,其中,所述介电隔离结构与所述第二衬垫层的第一区段和第二区段均直接物理接触。
根据本发明的另一实施例,还提供了一种制造半导体器件的方法,所述方法包括:在N阱上方形成第一半导体层;在P阱上方形成第二半导体层;实施图案化工艺以形成第一鳍结构和第二鳍结构,其中,所述第一鳍结构包括所述第一半导体层的部分和所述N阱的部分,并且所述第二鳍结构包括所述第二半导体层的部分和所述P阱的部分;在所述第一鳍结构、所述N阱、所述第二鳍结构和所述P阱上方形成第一衬垫层;选择性地去除所述第一衬垫层,从而去除形成在所述第二鳍结构和所述P阱上方的所述第一衬垫层,其中,形成在所述第一鳍结构和所述N阱上方的所述第一衬垫层的剩余部分不受选择性地去除的影响;以及在选择性地去除所述第一衬垫层之后,在所述第二鳍结构、所述P阱和所述第一衬垫层的剩余部分上方形成第二衬垫层,其中,所述第二衬垫层和所述第一衬垫层具有不同的材料组成。
在上述方法中,还包括:去除所述第一衬垫层和所述第二衬垫层的形成在所述第一半导体层上方的部分;以及去除所述第二衬垫层的形成在所述第二半导体层上方的部分。
在上述方法中,形成所述第一衬垫层包括形成含氮化物层作为所述第一衬垫层。
在上述方法中,所述含氮化物层包括氮化硅。
在上述方法中,形成所述第二衬垫层包括形成含氧化物层作为所述第二衬垫层。
在上述方法中,所述含氧化物层包括氧化硅。
在上述方法中,形成所述第一半导体层包括在所述N阱上方外延生长硅锗作为所述第一半导体层;以及形成所述第二半导体层包括在所述P阱上方外延生长硅作为所述第二半导体层。
在上述方法中,在所述第一半导体层之前形成所述第二半导体层;以及实施所述硅的外延生长,从而在所述N阱和所述P阱两者上方生长所述硅。
在上述方法中,还包括:在形成所述第二半导体层之后但在形成所述第一半导体层之前,部分地去除位于所述N阱上方的所述第二半导体层,其中,在部分地去除所述第二半导体层之后,在所述第二半导体层的位于所述N阱上方的剩余部分上方外延生长所述第一半导体层。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (20)
1.一种半导体器件,包括:
P型场效应晶体管(PFET),包括:
N阱,设置在衬底中;
隔离结构,设置在所述N阱上方;
第一鳍结构,设置在所述N阱上方,其中,所述第一鳍结构包括下部区段和设置在所述下部区段上方的上部区段,并且其中,所述下部区段设置在所述隔离结构的上表面下方;
所述下部区段还包括设置在所述N阱上方的第二半导体层,所述第二半导体层包含硅层,所述上部区段包括第一半导体层,所述第一半导体层包含硅锗层;
第一衬垫层,设置在所述N阱上方和所述第一鳍结构的下部区段的侧壁上;以及
第二衬垫层,设置在所述第一衬垫层上方,其中,所述第一衬垫层和所述第二衬垫层包括不同的材料,所述第一衬垫层和所述第二衬垫层均与所述第一半导体层和所述第二半导体层的接触界面共面;以及
N型场效应晶体管(NFET),包括:
P阱,设置在所述衬底中;
隔离结构,设置在所述P阱上方;
第二鳍结构,设置在所述P阱上方,其中,所述第二鳍结构包括下部区段和设置在所述下部区段上方的上部区段,并且其中,所述下部区段设置在所述隔离结构的上表面下方;以及
第三衬垫层,设置在所述P阱上方和所述第二鳍结构的下部区段的侧壁上,其中,所述第三衬垫层和所述第二衬垫层包括相同的材料,所述第三衬垫层的顶面与所述隔离结构的顶面共面,
其中,所述P型场效应晶体管和所述N型场效应晶体管具有不同数量的衬垫层。
2.根据权利要求1所述的半导体器件,其中:
所述第二鳍结构包括硅层;
所述第一衬垫层包括配置为防止所述硅锗层被氧化的材料;以及
所述第三衬垫层包括配置为对所述N型场效应晶体管提供应力的材料。
3.根据权利要求2所述的半导体器件,其中:
所述第一衬垫层包括含氮化物的材料;
所述第二衬垫层包括含氧化物的材料;以及
所述第三衬垫层包括含氧化物层的材料。
4.根据权利要求3所述的半导体器件,其中:
所述第一衬垫层包括氮化硅;以及
所述第二衬垫层和所述第三衬垫层均包括氧化硅。
5.根据权利要求2所述的半导体器件,其中:
所述第一衬垫层和所述第二衬垫层的任何部分都不设置在所述硅锗层的侧壁上;以及
所述第三衬垫层的任何部分都不设置在所述硅层的侧壁上。
6.根据权利要求1所述的半导体器件,其中:
所述第一衬垫层的部分设置在所述N阱的侧面上;以及
所述第三衬垫层的部分设置在所述P阱的侧面上。
7.根据权利要求1所述的半导体器件,其中,所述隔离结构包括浅沟槽隔离(STI),并且其中,在截面侧视图中,所述第二衬垫层和所述第三衬垫层围绕所述浅沟槽隔离。
8.一种FinFET器件,包括:
P型场效应晶体管(PFET),包括:
N阱,形成在衬底中,其中,所述N阱包括第一部分和突出于所述第一部分的第二部分;
第一半导体层,位于所述N阱的第二部分上方,其中,所述第一半导体层包括硅锗,并且其中,所述N阱的第二部分和所述第一半导体层是所述P型场效应晶体管的第一鳍结构的部分;
第一衬垫层,位于所述N阱的第一部分上方和所述N阱的第二部分的侧壁上方,但不位于所述第一半导体层上方,其中,所述第一衬垫层包括防止所述硅锗被氧化的材料;以及
第二衬垫层的第一区段,位于所述第一衬垫层上方,其中,所述第二衬垫层包括对硅产生应力的材料;以及
N型场效应晶体管(NFET),包括:
P阱,形成在所述衬底中,其中,所述P阱包括第一部分和突出于所述第一部分的第二部分;
第二半导体层,位于所述P阱的第二部分上方,其中,所述第二半导体层包括硅,并且其中,所述P阱的第二部分和所述第二半导体层是所述N型场效应晶体管的第二鳍结构的部分;以及
所述第二衬垫层的第二区段,位于所述P阱的第一部分上方并且直接地位于所述P阱的第二部分的侧壁上,但不位于所述第二半导体层上方,所述第一衬垫层和所述第二衬垫层的第二区段具有相同的高度;
所述第二半导体层还位于所述N阱的所述第二部分上方并且位于所述第一半导体层的下方,所述第一衬垫层和所述第二衬垫层均与所述第一半导体层和所述第二半导体层的接触界面共面。
9.根据权利要求8所述的FinFET器件,其中:
所述第一衬垫层包括氮化硅;以及
所述第二衬垫层的第一区段和第二区段均包括氧化硅。
10.根据权利要求8所述的FinFET器件,其中:
所述第一衬垫层与所述N阱的第二部分的侧壁直接物理接触;以及
所述第二衬垫层的第二区段与所述P阱的第二部分的侧壁直接物理接触。
11.根据权利要求8所述的FinFET器件,还包括:位于所述P型场效应晶体管和所述N型场效应晶体管之间的介电隔离结构,其中,所述介电隔离结构与所述第二衬垫层的第一区段和第二区段均直接物理接触。
12.一种制造半导体器件的方法,所述方法包括:
在N阱和P阱上方形成第二半导体层,包括在所述N阱和所述P阱上方外延生长作为所述第二半导体层的硅;
部分地去除所述N阱上方的所述第二半导体层;
在所述N阱上方形成第一半导体层,包括:在所述N阱上方外延生长作为所述第一半导体层的硅锗,所述第一半导体层外延生长在所述第二半导体层在所述部分地去除之后的位于所述N阱上方的剩余部分上方;
实施图案化工艺以形成第一鳍结构和第二鳍结构,其中,所述第一鳍结构包括所述第一半导体层的部分和所述N阱的部分,并且所述第二鳍结构包括所述第二半导体层的部分和所述P阱的部分;
在所述第一鳍结构、所述N阱、所述第二鳍结构和所述P阱上方形成第一衬垫层;
选择性地去除所述第一衬垫层,从而去除形成在所述第二鳍结构和所述P阱上方的所述第一衬垫层,其中,形成在所述第一鳍结构和所述N阱上方的所述第一衬垫层的剩余部分不受选择性地去除的影响;以及
在选择性地去除所述第一衬垫层之后,在所述第二鳍结构、所述P阱和所述第一衬垫层的剩余部分上方形成第二衬垫层,其中,所述第二衬垫层和所述第一衬垫层具有不同的材料组成。
13.根据权利要求12所述的方法,还包括:
去除所述第一衬垫层和所述第二衬垫层的形成在所述第一半导体层上方的部分;以及
去除所述第二衬垫层的形成在所述第二半导体层上方的部分。
14.根据权利要求12所述的方法,其中,形成所述第一衬垫层包括形成含氮化物层作为所述第一衬垫层。
15.根据权利要求14所述的方法,其中,所述含氮化物层包括氮化硅。
16.根据权利要求12所述的方法,其中,形成所述第二衬垫层包括形成含氧化物层作为所述第二衬垫层。
17.根据权利要求16所述的方法,其中,所述含氧化物层包括氧化硅。
18.根据权利要求12所述的方法,其中,所述N阱和所述P阱分别形成为包括从衬底中垂直突出的部分。
19.根据权利要求13所述的方法,其中:在去除所述第一衬垫层的部分和所述第二衬垫层的部分后,所述第二鳍结构的部分侧壁暴露,所述第二鳍结构未暴露全部侧壁。
20.根据权利要求13所述的方法,还包括:在去除所述第一衬垫层的部分和所述第二衬垫层的部分前,形成围绕所述第一鳍结构和所述第二鳍结构的隔离结构;
在去除所述第一衬垫层的部分和所述第二衬垫层的部分时,也部分地去除所述隔离结构。
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US11031299B2 (en) | 2021-06-08 |
CN108807381A (zh) | 2018-11-13 |
US10522417B2 (en) | 2019-12-31 |
KR102111416B1 (ko) | 2020-05-18 |
US20180350697A1 (en) | 2018-12-06 |
US20210366784A1 (en) | 2021-11-25 |
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