CN108807275A - The production method of semiconductor devices - Google Patents
The production method of semiconductor devices Download PDFInfo
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- CN108807275A CN108807275A CN201710298703.0A CN201710298703A CN108807275A CN 108807275 A CN108807275 A CN 108807275A CN 201710298703 A CN201710298703 A CN 201710298703A CN 108807275 A CN108807275 A CN 108807275A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title description 8
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- 239000002184 metal Substances 0.000 claims abstract description 87
- 229910052751 metal Inorganic materials 0.000 claims abstract description 87
- 239000002019 doping agent Substances 0.000 claims abstract description 55
- 238000000034 method Methods 0.000 claims abstract description 37
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 24
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 24
- 239000002344 surface layer Substances 0.000 claims abstract description 20
- 239000011241 protective layer Substances 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 16
- 238000001312 dry etching Methods 0.000 claims description 11
- 238000004544 sputter deposition Methods 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 10
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- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 19
- 238000005530 etching Methods 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
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- 239000002356 single layer Substances 0.000 description 5
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- 239000000377 silicon dioxide Substances 0.000 description 4
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- 125000006850 spacer group Chemical group 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
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- 229910002601 GaN Inorganic materials 0.000 description 1
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of forming method of semiconductor devices comprising：Underlying structure is provided, the underlying structure includes transistor, and the transistor includes gate structure and the source electrode positioned at the gate structure both sides, drain electrode；Carry out prerinse；At least in the source electrode, the forming metal layer on surface of drain electrode after progress prerinse；Dopant is mixed to the surface of the source electrode, drain electrode, the type of the dopant is identical as the doping type of the source electrode, drain electrode；It anneals, so as to be mixed with the metal layer of the dopant and the surface layer of the source electrode, drain electrode reacts and generates metal silicide.Technical scheme of the present invention has further reduced transistor source and the contact resistance of drain electrode.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of production methods of semiconductor devices.
Background technology
As integrated circuit technology node constantly reduces, the contact area of the source electrode of transistor, drain electrode and plug is increasingly
It is small so that the contact resistance of the source electrode of transistor, drain electrode and plug increases therewith, affects the electric property of transistor.In order to
Reduce the contact resistance of source electrode and drain electrode, generally can form metal silicide on the surface of source electrode and drain electrode.The metal silicide
Forming method include：It in the forming metal layer on surface of transistor, then, is made annealing treatment so that metal layer and source electrode, leakage
The surface layer of pole, which reacts, generates metal silicide, finally, removes the metal layer not reacted.However, with integrated circuit
Process node further reduces, and how only reduces the requirement that contact resistance has been unable to meet device by metal silicide
The further contact resistance for reducing source electrode and drain electrode becomes industry technical problem urgently to be resolved hurrily.
Invention content
The technical problem to be solved in the present invention：How transistor source and the contact resistance of drain electrode further reduced.
To solve the above-mentioned problems, An embodiment provides a kind of forming method of semiconductor devices,
Including：There is provided underlying structure, the underlying structure includes transistor, the transistor include gate structure and be located at the grid
The source electrode of pole structure both sides, drain electrode；Carry out prerinse；After carrying out the prerinse, at least in the source electrode, the surface shape of drain electrode
At metal layer；Dopant is mixed to the surface of the source electrode, drain electrode, the type of the dopant and the source electrode, mixing of draining
Miscellany type is identical；It anneals, so that the metal layer for being mixed with the dopant is reacted with the surface layer of the source electrode, drain electrode
Generate metal silicide.
Optionally, the source electrode, drain electrode forming metal layer on surface after, to the surface of the source electrode, drain electrode mix
Dopant.
Optionally, further include：
The source electrode, drain electrode forming metal layer on surface after, to the surface of the source electrode, drain electrode incorporation dopant it
Before, form protective layer on the metal layer；
After mixing dopant to the surface of the source electrode, drain electrode, the protective layer is removed.
Optionally, after mixing dopant to the surface of the source electrode, drain electrode, execute described the step of being annealed it
Before, remove the protective layer.
Optionally, the material of the protective layer includes silica.
Optionally, further include：Plug is formed in the source electrode, drain electrode.
Optionally, the underlying structure further includes covering the interlayer dielectric layer of the transistor, the formation side of the plug
Method includes：
Before the prerinse, formed in the interlayer dielectric layer expose the source electrode, drain electrode contact hole；
After the annealing, conductive material is filled into the contact hole to form the plug.
Optionally, before the prerinse, side wall is formed in the side wall of the contact hole.
Optionally, the transistor is fin formula field effect transistor.
Optionally, the fin formula field effect transistor includes fin, and the gate structure is located on the fin, and wraps
The cap layer on metal gates and the metal gates is included, the source electrode, drain electrode include the groove being located in the fin
And it is filled in the semi-conducting material in the groove.
Optionally, the transistor includes at least one of PMOS transistor, NMOS transistor.
Optionally, the dopant is B or P.
Optionally, the prerinse includes physical sputtering and dry etching.
Optionally, the physical sputtering uses Ar, and technological parameter includes：Radio-frequency power is 100W~400W.
Optionally, the dry etching is Siconi pre-cleaning processes, and technological parameter includes：The flow of He is
600SCCM~2000SCCM, NH3Flow be 200SCCM~500SCCM, NF3Flow be 20SCCM~200SCCM, air pressure
For 2Torr~10Torr, the time is 5s~100s.
In the inventive solutions, prerinse is carried out successively, is formed on the surface of source electrode, drain electrode for making metal
The metal layer of silicide and then to the surface of source electrode, drain electrode mix identical with the doping type of source electrode, drain electrode dopant with
Reduce the contact resistance of source electrode, drain electrode by reducing schottky barrier height, then annealed so that metal layer and source electrode,
The surface layer reaction of drain electrode generates metal silicide to further decrease contact resistance.Since prewashed step is in incorporation dopant
The step of before carry out, therefore can prevent source electrode, drain electrode the surface layer containing dopant be removed and source electrode, drain electrode in adulterate
The concentration of object reduces, so as to avoid source electrode, drain electrode surface layer in dopant loss, have effectively achieved source electrode, drain electrode
Contact resistance further reduces.
By referring to the drawings to the detailed description of exemplary embodiment of the present invention, other feature of the invention, side
Face and its advantage will become apparent.
Description of the drawings
Attached drawing forms part of this specification, and which depict exemplary embodiment of the present invention, and together with specification
Principle for explaining the present invention together, in the accompanying drawings：
Fig. 1 is the production flow diagram of semiconductor devices in one embodiment of the present of invention；
Fig. 2 to Figure 10 be in one embodiment of the present of invention semiconductor devices in the sectional view of each production phase.
Specific implementation mode
As previously mentioned, as integrated circuit technology node further reduces, contact is only reduced by metal silicide
Resistance has been unable to meet the requirement of device, and it is urgently to be resolved hurrily as industry how further to reduce the contact resistance of source electrode and drain electrode
The technical issues of.
A kind of research approach regarding to the issue above is：It is formed after the source electrode of transistor, drain electrode, in source electrode, drain electrode
Dopant is injected on surface, and the type of the dopant is identical as the doping type of source electrode, drain electrode；Then, it is cleaned；Then,
It in the forming metal layer on surface of transistor, anneals later, to form metal silicide on the surface of source electrode, drain electrode；Finally,
The plug contacted is formed in the top of source electrode, drain electrode.
Theoretically speaking the dopant of source electrode, drain surface can reduce schottky barrier height (Schottky
Barrier Height, abbreviation SBH), and then the contact resistance of reduction source electrode, drain electrode.However, practical form said program
Semiconductor devices carries out test discovery, and the larger problem of the source electrode of transistor, the contact resistance of drain electrode is not improved.
For this purpose, the present invention has carried out numerous studies analysis, and the reason of finding, causing the above problem may be the side of plug
Wall pattern, the depth of plug, doping concentration of dopant etc..It is found however, carrying out verification one by one to these reasons, even if excluding
The influence of these reasons, the source electrode of transistor, there are still the larger problems of contact resistance for drain electrode.In consideration of it, the present invention carries out
Further further investigation, and find, it is cleaned before source electrode, drain electrode form the metal layer for making metal silicide
When, the surface layer containing the dopant that can not only remove source electrode, drain makes the area for containing the dopant in source electrode, drain electrode
Domain thickness reduces, in addition, can also make the loss of dopant described in source electrode, drain electrode that its concentration be made to reduce, causes institute in source electrode, drain electrode
The loss for stating dopant, to cause the contact resistance of source electrode, drain electrode still larger.
In consideration of it, the present invention proposes a kind of improved method, prerinse is carried out successively, in source electrode, the surface shape of drain electrode
At for making metal silicide metal layer and then to the surface of source electrode, drain electrode incorporation with source electrode, drain electrode doping type
Identical dopant to reduce the contact resistance of source electrode, drain electrode by reducing schottky barrier height, then anneal with
So that metal layer is reacted with the surface layer of source electrode, drain electrode and generates metal silicide to further decrease contact resistance.Due to prewashed
Step carries out before the step of mixing dopant, therefore the surface layer containing dopant of source electrode, drain electrode can be prevented to be removed, and
The concentration of dopant reduces in source electrode, drain electrode, so as to avoid source electrode, drain electrode surface layer in dopant loss, it is effectively real
Source electrode is showed, the contact resistance of drain electrode further reduces.
Carry out the various exemplary embodiments of detailed description of the present invention now with reference to attached drawing.It should be understood that unless in addition specific
Illustrate, component and the positioned opposite of step that otherwise illustrates in these embodiments, numerical expression and numerical value are not understood that
For limitation of the scope of the invention.
In addition, it should be understood that for ease of description, the size of attached all parts shown in the drawings is not necessarily according to reality
The proportionate relationship on border is drawn, such as certain layers of thickness or width can be exaggerated relative to other layers.
The description of exemplary embodiment is merely illustrative below, in any sense all not as to the present invention and
Its any restrictions applied or used.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of these technologies, method and apparatus, these technologies, method and apparatus should be considered as the part of this specification.
It should be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined or illustrates in attached drawing, then it need not be further discussed in the explanation of subsequent attached drawing.
The production method of the semiconductor devices of the present embodiment is described in detail with reference to Fig. 1 to Figure 10.
First, with reference to figure 2, the step S1 in Fig. 1 is executed, provides underlying structure S, underlying structure S includes transistor, described
Transistor includes gate structure and the source electrode positioned at the gate structure both sides, drain electrode, and the source electrode, drain electrode are doped
Source electrode, drain electrode.
In the present embodiment, underlying structure S includes transistor 2, the transistor in semiconductor substrate 1 and semiconductor substrate 1
3, wherein transistor 2 is NMOS transistor, and positioned at the NMOS area of semiconductor substrate 1, the source S 1 of transistor 2, drain D 1
Doping type is N-type, and transistor 3 is PMOS transistor, and is located at the areas PMOS of semiconductor substrate 1, the source S 2 of transistor 3,
The doping type of drain D 2 is p-type.
Semiconductor substrate 1 can be monocrystalline substrate, multicrystalline silicon substrate, amorphous silicon substrate, germanium silicon substrate, carbon silicon substrate,
Silicon-on-insulator substrate, germanium substrate on insulator, glass substrate, III-V compound substrate (such as gallium nitride substrate or arsenic
Change gallium substrate etc.) etc. substrates.
Transistor 2 is fin formula field effect transistor, and includes fin 20, the gate structure G1 on fin 20, with
And source S 1, drain D 1 positioned at the both sides gate structure G1.Further, gate structure G1 includes metal gates 21, metal gate
Cap layer 22 on pole 21, and the side wall (not identifying) that is covered in around metal gates 21 and cap layer 22, the side wall
It can be single-layer or multi-layer.Metal gates 21 can be single-layer metal or metal laminated, and the effect of cap layer 22 is included in subsequently
The metal gates 21 of protection lower section are not etched and (will illustrate in step s 2) in step S2.Source S 1, drain D 1 are wrapped
It groove (not identifying) and the semi-conducting material that is filled in the groove to include in the fin 20, and the semi-conducting material can
It is filled in a manner of by epitaxial growth in the groove.In a particular embodiment, the semi-conducting material selects SiC, with
Apply stress to the raceway groove of NMOS transistor to improve the carrier mobility of transistor.Further, source S 1, drain D 1
It is set as the source/drain (top for the source/drain being lifted exceeds the surface of fin 20) of lifting, to improve NMOS transistor
Performance.
Transistor 3 is fin formula field effect transistor, and includes fin 30, the gate structure G2 on fin 30, with
And source S 2, drain D 2 positioned at the both sides gate structure G2.Further, gate structure G2 includes metal gates 31, metal gate
Cap layer 32 on pole 31, and the side wall (not identifying) that is covered in around metal gates 31 and cap layer 32, the side wall
It can be single-layer or multi-layer.Metal gates 31 can be single-layer metal or metal laminated, and the effect of cap layer 32 is included in subsequently
The metal gates 31 of protection lower section are not etched and (will illustrate in step s 2) in step S2.Source S 2, drain D 2 are wrapped
It groove (not identifying) and the semi-conducting material that is filled in the groove to include in the fin 30, and the groove can be arranged
For ∑ type or rectangle, the semi-conducting material can be filled in the groove by way of epitaxial growth.It is being embodied
In example, the semi-conducting material selects SiGe, to apply stress to the raceway groove of PMOS transistor to improve the current-carrying of transistor
Transport factor.Further, source S 2, drain D 2 are also configured as the source/drain of lifting (top of the source/drain being lifted are super
Go out the surface of fin 30), to improve the performance of PMOS transistor.
It should be noted that in the inventive solutions, the type of transistor should not be limited to fin field effect crystalline substance
Body pipe can be adapted for any kind of transistor, such as MOS transistor.In the alternative of the present embodiment, underlying structure S
In can only include PMOS transistor or only include NMOS transistor.
Underlying structure S further includes being covered in semiconductor other than including semiconductor substrate 1, transistor 2 and transistor 3
Interlayer dielectric layer on substrate 1, transistor 2 and transistor 3.In the present embodiment, the interlayer dielectric layer includes first Jie
Electric layer 40, the second dielectric layer 42 on the first dielectric layer 40 and the third dielectric layer on the second dielectric layer 42
43, wherein the gap between the first dielectric layer 40, the second dielectric layer 42 filling transistor 2 and transistor 3, the second dielectric layer 42
Upper surface and gate structure G1, gate structure G2 at the top of flush.
In a preferred embodiment, the insulating materials that the first dielectric layer 40 selects hardness smaller, to obtain better fillibility
Energy.The insulating materials that second dielectric layer 42 selects hardness larger, preferably to carry out flatening process to the second dielectric layer 42, from
And the surface of the second dielectric layer 42 is made to be flushed with the surface of gate structure G1, gate structure G2.In the present embodiment, the first dielectric
Layer 40 and the second dielectric layer 42 select identical material (such as silica), but the manufacture craft of the two is different, different to obtain
Hardness.In the alternative of the present embodiment, the first dielectric layer 40 and the second dielectric layer 42 can select identical material.
Third dielectric layer 43 can select material identical with the first dielectric layer 40, the second dielectric layer 42, can also select
The material different from the first dielectric layer 40, the second dielectric layer 42.In the present embodiment, third dielectric layer 43 is silica.
It should be noted that although in the technical solution of the present embodiment, the interlayer dielectric layer is that laminated construction (includes
The dielectric layer of two layers or more of stacking), but in other embodiments, the interlayer dielectric layer may be single layer structure.
In a preferred embodiment, it is formed with contact hole etching barrier layer between the first dielectric layer 40 and the second dielectric layer 42
41, the part on contact hole etching barrier layer 41 be covered in the side wall, source S 1, drain D 1, source S 2 and drain D 2 it
On.Contact hole etching barrier layer 41 in subsequent step S2 for playing the role of etching stopping.In the present embodiment, contact hole
The material of etching barrier layer 41 is silicon nitride.
Then, with reference to figure 3, the step S2 in Fig. 1 is executed, contact hole is formed in the interlayer dielectric layer.
In the present embodiment, the contact hole C1, Yi Jilu for exposing source S 1, drain D 1 are formed in the interlayer dielectric layer
Go out the contact hole C2 of source S 2, drain D 2, contact hole C1, contact hole C2 at least run through third dielectric layer 43 and the second dielectric layer
42。
In a particular embodiment, contact hole C1, contact hole C2 forming method include：Figure is formed on third dielectric layer 43
The photoresist layer (not shown) of shape；It is performed etching as mask using the patterned photoresist layer, until exposing source S 1, leakage
Pole D1, source S 2 and drain D 2, the etching can be dry etching；Then, the patterned photoresist layer is removed.
During performing etching to form contact hole C1, contact hole C2, contact hole C1, the position of contact hole C2 are smart
Degree, pattern precision are possible to can have relatively large deviation, so that being exposed to quarter at the top of the top of gate structure G1, gate structure G2
It loses in environment, due to being provided with cap layer 22 at the top of gate structure G1, being provided with cap layer 32 at the top of gate structure G2, therefore
Etching stopping can be made in cap layer 22, cap layer 32, prevent the metal gates 21 of 22 lower section of cap layer, the gold of 32 lower section of cap layer
Belong to grid 31 and forms short circuit with the conductive material contacts being subsequently filled in contact hole C1, contact hole C2 because etching is exposed.
In a preferred embodiment, cap layer 22, cap layer 32 material be silicon nitride, have under a variety of etching environment
There is preferable elching resistant energy, to more reliably protect metal gates 21, the metal gates 31 of lower section.
In the present embodiment, contact hole C1, contact hole C2 are stepped hole, and pattern wide at the top and narrow at the bottom is presented.Wherein, it connects
Contact hole C1 is formed with step (not identifying) in the position at the top of gate structure G1, and contact hole C2 is close to the tops gate structure G2
The position in portion is formed with step (not identifying).
Then, with reference to figure 4, the step S3 in Fig. 1 is executed, side wall 44 is respectively formed in the side wall of contact hole C1, contact hole C2.
As previously mentioned, contact hole C1 is formed with step (not identifying), contact hole in the position at the top of gate structure G1
C2 is formed with step (not identifying) in the position at the top of gate structure G2, and contact hole C1, contact hole C2 are in the step
Corner location structure is more fragile, easy tos produce defect, which can cause subsequently to be filled in contact hole C1, contact hole C2
Conductive material forms short circuit with metal gates 21, metal gates 31.Side wall is formed by the side wall in contact hole C1, contact hole C2
44, the Step Coverage on contact hole C1, contact hole C2 side walls can be lived, after so that the defect of the step corner is not touched
The continuous conductive material being filled in contact hole C1, contact hole C2, thus avoid the problem of short circuit.
In the present embodiment, the forming method of side wall 44 includes：In third dielectric layer 43, the side wall of contact hole C1, contact
The side wall of hole C2, drain D 1, source S 2, forms spacer material layer in drain D 2 at source S 1；The spacer material layer is returned
It carves, the upper surface of third dielectric layer 43, source S 1, drain D 1, source S 2, the spacer material in drain D 2 is covered in removal
Layer, remaining spacer material layer constitute side wall 44.
In the present embodiment, the material of side wall 44 includes silicon nitride, and certainly, side wall 44 can also select other to be suitable as
The insulating materials of side wall, such as silicon oxynitride.
Then, with reference to figure 5, the step S4 in Fig. 1 is executed, prerinse is carried out, then, at least in source S 1, drain D 1, source
The forming metal layer on surface 5 of pole S2, drain D 2, metal layer 5 are used to form metal silicide.
In order to reduce the contact resistance of source S 1, drain D 1, source S 2, drain D 2 in semiconductor devices, in source S 1, leakage
The surface formation metal silicide of pole D1, source S 2, drain D 2.Before forming the metal silicide, need to semiconductor
Device carries out prerinse.
In the present embodiment, prewashed act on includes：Remove source S 1, drain D 1, source S 2,2 surface of drain D
Natural silicon oxide (native oxide), cause contact resistance larger to avoid the presence because of the natural silicon oxide.Described
In prewashed step, first, physical sputtering is carried out, then, carries out dry etching.
In the prerinse step, why first physical sputtering again dry etching the reason of be, physical sputtering it is clear
It is clean ineffective, it, can be due to removing intensity height to semiconductor devices (especially source to completely remove the natural silicon oxide on surface
Pole S1, drain D 1, source S 2, drain D 2) it causes to damage, and dry etching can make up the deficiency of physical sputtering just, use
Remove remaining natural silicon oxide, and since the time of dry etching will not cause contact hole C1, contact hole C2 because too long
Sidewall loss it is excessive.In addition, dry etching can also make semiconductor devices obtain more smooth interface and good interface
Characteristic.
Further, in the present embodiment, the physical sputtering includes using Ar, the technological parameter of the physical sputtering：It penetrates
Frequency power is 100W~400W.When being sputtered using the parameter, source electrode S1, drain D 1, source S 2, drain D 2 can not damaged
In the case of effectively remove most of natural oxide.Certainly, in other embodiments, the physical sputtering can also use
Generated ion after other ionized inert gas.
Further, in the present embodiment, the dry etching is Siconi pre-cleaning processes, the Siconi prerinse works
The technological parameter of skill includes：The flow of He is 600SCCM~2000SCCM, NH3Flow be 200SCCM~500SCCM, NF3's
Flow is 20SCCM~200SCCM, and air pressure is 2Torr~10Torr, and the time is 5s~100s.The Siconi pre-cleaning processes
There is preferable Etch selectivity to the pre-removal substance on semiconductor devices, the loss of semiconductor devices is reduced, moreover, energy
It accesses lower leakage current and is distributed the contact resistance more concentrated, to which metal evenly can be formed in the subsequent process
Silicide.
Carry out prerinse after, the upper surface of third dielectric layer 43, the side wall of contact hole C1, contact hole C2 side wall,
Source S 1, source S 2, forms metal layer 5 in drain D 2 at drain D 1.In the present embodiment, metal layer 5 includes Ti layers and is located at
TiN layer on Ti layers, metal layer 5 are used to form metal silicide TiSi after the annealing steps of subsequent step S8x, metallic silicon
Compound TiSixWith lower schottky barrier height (SBH), it is thus possible to significantly more reduction source S 1, drain D 1, source
The contact resistance of pole S2, drain D 2.But it should be noted that in the inventive solutions, the material of metal layer 5 does not answer office
It is limited to this, can also is Co, Ni, Pt etc..
Then, with reference to figure 6, the step S5 in Fig. 1 is executed, forms protective layer 6 on metal layer 5, protective layer 6 is for preventing
Metal layer 6 in the annealing through subsequent step S8 to be aoxidized before forming metal silicide, and for preventing metal layer 6 dirty
It contaminates (will illustrate in subsequent step S6).
It can be removed after protective layer 6 realizes its effect.In the present embodiment, the material selection silica of protective layer 6,
It is easier to remove, and the not metal layer 5 below easy damaged while removal.Further, the formation process of protective layer 6
For atomic layer deposition (ALD).
Then, with reference to figure 7, the step S6 in Fig. 1 is executed, the surface to source S 1, drain D 1 (refers to being connect with metal layer 5
Tactile surface) incorporation dopant 230, in other words, dopant 230 is made only in the surface layer of source S 1, drain D 1, and is not formed at
The bottom of source S 1, drain D 1.The type of dopant 230 is identical as the doping type of source S 1, drain D 1, is N-type.Xiang Yuan
Surface (referring to the surface contacted with metal layer 5) the incorporation dopant 330 of pole S2, drain D 2, in other words, the only shape of dopant 330
At on the surface layer of source S 2, drain D 2, and it is not formed at the bottom of source S 2, drain D 2.The type and source electrode of dopant 330
S2, the doping type of drain D 2 are identical, are p-type.Dopant 230, dopant 330 can be used in reducing Schottky barrier height
Degree, and then reduce the contact resistance of source S 1, drain D 1, source S 2, drain D 2.
In the present embodiment, dopant 230, dopant 330 are formed by way of ion implanting, are specifically included：It is protecting
The first patterned photoresist layer (not shown) is formed on sheath 6, the first patterned photoresist layer exposes source S 1, leakage
Pole D1, but source S 2, drain D 2 are covered；The first ion implanting is carried out, dopant 230 is injected into source S 1, drain electrode
The interface of D1 and metal layer 5；Remove the described first patterned photoresist layer；Second graphical is formed on protective layer 6
Photoresist layer (not shown), the photoresist layer of the second graphical expose source S 2, drain D 2, but by source S 1, drain D 1
It covers；The second ion implanting is carried out, dopant 330 is injected into the interface of source S 2, drain D 2 and metal layer 5.?
In the alternative of the present embodiment, it can also first sequentially form the photoresist layer of the second graphical, carry out second ion
Injection, then sequentially form the described first patterned photoresist layer, carry out first ion implanting.
Pollution is will produce when removing the photoresist layer of the first patterned photoresist layer, the second graphical
Object, protective layer 6 can prevent the pollutant to be attached on the metal layer 5 of 6 lower section of protective layer, to prevent metal layer 5 contaminated.
Further, in the present embodiment, dopant 230 is B, and dopant 330 is P.In a particular embodiment, described
The technological parameter of one ion implanting includes：Implantation Energy is 1kev~10kev, implantation dosage 5.0E14atm/cm2~
1.0E16atm/cm2, the technological parameter of the second ion implanting includes：Implantation Energy is 5kev~20kev, and implantation dosage is
5.0E14atm/cm2~1.0E16atm/cm2。
, can also be after the prerinse of above-mentioned steps S4 in the alternative of the present embodiment, the shape in source electrode and drain electrode
Before metal layer, above-mentioned steps S6 is executed.
Then, with reference to figure 8, the step S7 in Fig. 1 is executed, removes the protective layer 6 in Fig. 7.In the present embodiment, use is wet
The method of method etching removes protective layer 6, and used etching agent is hydrofluoric acid aqueous solution.
Then, with reference to figure 9, the step S8 in Fig. 1 is executed, is annealed, so that the surface layer of metal layer 5 and source S 1, leakage
The surface layer reaction on the surface layer of pole D1, the surface layer of source S 2, drain D 2 generates metal silicide 50.In the present embodiment, metallic silicon
Compound 50 is TiSix。
In the present embodiment, described to be annealed into laser annealing, technological parameter includes：Temperature is 800 DEG C~1000 DEG C.
In the alternative of the present embodiment, it can also first carry out above-mentioned steps S8 and carry out above-mentioned steps S7 again.The present embodiment
Technical solution had the following advantages relative to the technical solution of the alternative：The annealing steps can be densified protective layer 6, make
Not only protective layer 6 be difficult to remove, but also the third dielectric layer 43 below also making when remove protective layer 6 lose it is more, and
When the annealing steps it is rear carry out, removal protective layer 6 the step of formerly carry out when, the problem can be avoided.
As the above analysis, in the inventive solutions, prerinse is carried out successively, on source electrode, the surface of drain electrode
Form the metal layer for making metal silicide and then the doping class to the surface of source electrode, drain electrode incorporation and source electrode, drain electrode
The identical dopant of type is then annealed with reducing the contact resistance of source electrode, drain electrode by reducing schottky barrier height
So that metal layer is reacted with the surface layer of source electrode, drain electrode generates metal silicide to further decrease contact resistance.Due to prerinse
The step of carried out before the step of mixing dopant, therefore can prevent source electrode, drain electrode the surface layer containing dopant be removed, with
And in source electrode, drain electrode dopant concentration reduce, so as to avoid source electrode, drain electrode surface layer in dopant loss, effectively
Realize source electrode, the contact resistance of drain electrode further reduces.
Finally, with reference to figure 10, the step S9 in Fig. 1 is executed, conductive material is filled into contact hole C1, contact hole C2 with shape
At plug C3, plug C4, plug C3, plug C4 and source S 1, drain D 1, source S 2,2 surface of drain D metal silicide 50
Ohmic contact is formed, contact resistance is reduced.There is provided underlying structure comprising transistor, the transistor include gate structure
And the source electrode positioned at the gate structure both sides, drain electrode
In the present embodiment, the conductive material filled in contact hole C1, contact hole C2 includes W.Certainly, the conductive material
The lower material of other resistance, such as Cu can be selected.
In the present embodiment, plug C3, plug C4 forming method include：It forms covering third dielectric layer 43 and fills and connect
The conductive material layer of contact hole C1, contact hole C2；Planarized, to remove the extra conductive material layer, formed plug C3,
Plug C4.
So far, semiconductor device according to the ... of the embodiment of the present invention and its manufacturing method is described in detail.In order to avoid
The design for covering the present invention, does not describe some details known in the field, those skilled in the art as described above,
Completely it can be appreciated how implementing technical solution disclosed herein.In addition, each embodiment for being instructed of this disclosure can be with
Independent assortment.It should be appreciated by those skilled in the art, can to embodiments illustrated above carry out it is a variety of modification without departing from
The spirit and scope of the present invention as defined in the appended claims.
Claims (15)
1. a kind of forming method of semiconductor devices, which is characterized in that including：
There is provided underlying structure, the underlying structure includes transistor, the transistor include gate structure and be located at the grid
The source electrode of pole structure both sides, drain electrode；
Carry out prerinse；
After carrying out the prerinse, at least in the source electrode, the forming metal layer on surface of drain electrode；
Dopant, the type of the dopant and the source electrode, the doping type of drain electrode are mixed to the surface of the source electrode, drain electrode
It is identical；
It anneals, so as to be mixed with the metal layer of the dopant and generation gold is reacted on the surface layer of the source electrode, drain electrode
Belong to silicide.
2. the forming method of semiconductor devices as described in claim 1, which is characterized in that on the source electrode, the surface of drain electrode
It is formed after metal layer, dopant is mixed to the surface of the source electrode, drain electrode.
3. the forming method of semiconductor devices as claimed in claim 2, which is characterized in that further include：
The source electrode, drain electrode forming metal layer on surface after, to the surface of the source electrode, drain electrode mix dopant before,
Protective layer is formed on the metal layer；
After mixing dopant to the surface of the source electrode, drain electrode, the protective layer is removed.
4. the forming method of semiconductor devices as claimed in claim 3, which is characterized in that the source electrode, the surface of drain electrode
After mixing dopant, before executing described the step of being annealed, the protective layer is removed.
5. the forming method of semiconductor devices as claimed in claim 3, which is characterized in that the material of the protective layer includes oxygen
SiClx.
6. the forming method of semiconductor devices as described in claim 1, which is characterized in that further include：In the source electrode, drain electrode
Upper formation plug.
7. the forming method of semiconductor devices as claimed in claim 6, which is characterized in that the underlying structure further includes covering
The forming method of the interlayer dielectric layer of the transistor, the plug includes：
Before the prerinse, formed in the interlayer dielectric layer expose the source electrode, drain electrode contact hole；
After the annealing, conductive material is filled into the contact hole to form the plug.
8. the forming method of semiconductor devices as claimed in claim 7, which is characterized in that before the prerinse, in institute
The side wall for stating contact hole forms side wall.
9. such as the forming method of claim 1 to 8 any one of them semiconductor devices, which is characterized in that the transistor is
Fin formula field effect transistor.
10. the forming method of semiconductor devices as claimed in claim 9, which is characterized in that the fin formula field effect transistor
Including fin, the gate structure is located on the fin, and includes the lid on metal gates and the metal gates
Cap layers, the source electrode, drain electrode include the groove being located in the fin and the semi-conducting material being filled in the groove.
11. such as the forming method of claim 1 to 8 any one of them semiconductor devices, which is characterized in that the transistor packet
Include at least one of PMOS transistor, NMOS transistor.
12. such as the forming method of claim 1 to 8 any one of them semiconductor devices, which is characterized in that the dopant is
B or P.
13. such as the forming method of claim 1 to 8 any one of them semiconductor devices, which is characterized in that the prerinse packet
It includes：Physical sputtering and dry etching.
14. the forming method of semiconductor devices as claimed in claim 13, which is characterized in that the physical sputtering uses Ar,
And technological parameter includes：Radio-frequency power is 100W~400W.
15. the forming method of semiconductor devices as claimed in claim 13, which is characterized in that the dry etching is Siconi
Pre-cleaning processes, and technological parameter includes：The flow of He is 600SCCM~2000SCCM, NH3Flow be 200SCCM~
500SCCM, NF3Flow be 20SCCM~200SCCM, air pressure be 2Torr~10Torr, the time be 5s~100s.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030127738A1 (en) * | 2002-01-04 | 2003-07-10 | Promos Technologies Inc. | Semiconductor device with SI-GE layer-containing low resistance, tunable contact |
| CN1921073A (en) * | 2005-08-26 | 2007-02-28 | 中芯国际集成电路制造(上海)有限公司 | Selective ion implantation pre-amorphous method for metal silicide production |
| CN101884091A (en) * | 2007-11-29 | 2010-11-10 | 应用材料公司 | Apparatus and method for depositing electrically conductive pasting material |
| CN102122639A (en) * | 2010-01-08 | 2011-07-13 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of non-volatile memory |
| US20160247805A1 (en) * | 2015-02-05 | 2016-08-25 | Globalfoundries Inc. | Method of forming a complementary metal oxide semiconductor structure with n-type and p-type field effect transistors having symmetric source/drain junctions and optional dual silicides |
-
2017
- 2017-04-27 CN CN201710298703.0A patent/CN108807275A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030127738A1 (en) * | 2002-01-04 | 2003-07-10 | Promos Technologies Inc. | Semiconductor device with SI-GE layer-containing low resistance, tunable contact |
| CN1921073A (en) * | 2005-08-26 | 2007-02-28 | 中芯国际集成电路制造(上海)有限公司 | Selective ion implantation pre-amorphous method for metal silicide production |
| CN101884091A (en) * | 2007-11-29 | 2010-11-10 | 应用材料公司 | Apparatus and method for depositing electrically conductive pasting material |
| CN102122639A (en) * | 2010-01-08 | 2011-07-13 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of non-volatile memory |
| US20160247805A1 (en) * | 2015-02-05 | 2016-08-25 | Globalfoundries Inc. | Method of forming a complementary metal oxide semiconductor structure with n-type and p-type field effect transistors having symmetric source/drain junctions and optional dual silicides |
Non-Patent Citations (2)
| Title |
|---|
| 叶志镇: "《半导体薄膜技术与物理》", 31 December 2008 * |
| 杨柳: "最新PVD预清洗-SiCoNi", 《集成电路应用》 * |
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Application publication date: 20181113 |