CN108807179A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
CN108807179A
CN108807179A CN201710313105.6A CN201710313105A CN108807179A CN 108807179 A CN108807179 A CN 108807179A CN 201710313105 A CN201710313105 A CN 201710313105A CN 108807179 A CN108807179 A CN 108807179A
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side wall
oxide layer
semiconductor structure
substrate
forming method
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CN108807179B (zh
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刘艳
刘佳
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to US15/970,565 priority patent/US10411118B2/en
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明提供一种半导体结构及其形成方法，所述形成方法包括：提供基底，所述基底上形成有栅极；在所述栅极的侧壁上形成第一侧墙；形成第一侧墙后，于基底上形成氧化层；在所述第一侧墙的侧壁上形成第二侧墙，所述栅极、所述第一侧墙和所述第二侧墙构成栅极结构；在所述栅极结构两侧的氧化层和基底中形成沟槽。本发明形成的半导体结构电学性能得到提高。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体制造技术领域，特别涉及一种半导体结构及其形成方法。
背景技术
随着半导体技术的飞速发展，半导体结构的特征尺寸不断缩小，使得集成电路的集成度越来越高，这对器件的性能也提出了更高的要求。
目前，随着金属-氧化物半导体场效应晶体管(MOSFET)的尺寸不断变小。为了适应工艺节点的减小，只能不断缩短MOSFET场效应管的沟道长度。沟道长度的缩短具有增加芯片的管芯密度、增加MOSFET场效应管的开关速度等好处。
然而，随着器件沟道长度的缩短，器件源极与漏极间的距离也随之缩短，这样一来栅极对沟道的控制能力变差，栅极电压夹断(pinch off)沟道的难度也越来越大，使得亚阀值漏电现象，即短沟道效应(SCE：short-channel effects)成为一个至关重要的技术问题。
因此，为了更好的适应器件尺寸按比例缩小的要求，半导体工艺逐渐开始从平面MOSFET晶体管向具有更高功效的三维立体式的晶体管过渡，如鳍式场效应管(FinFET)。FinFET具有很好的沟道控制能力。
然而，现有技术形成的半导体结构的电学性能有待提高。
发明内容
本发明解决的问题是提供一种半导体结构及其形成方法，提高半导体结构的电学性能。
为解决上述问题，本发明提供一种半导体结构的形成方法，包括：提供基底，所述基底上形成有栅极；在所述栅极的侧壁上形成第一侧墙；形成第一侧墙后，于基底上形成氧化层；在所述第一侧墙的侧壁上形成第二侧墙，所述栅极、所述第一侧墙和所述第二侧墙构成栅极结构；在所述栅极结构两侧的氧化层和基底中形成沟槽。
可选的，形成所述沟槽的步骤包括：对所述栅极结构两侧的氧化层和基底进行第一刻蚀，形成初始沟槽；对所述初始沟槽进行清洗处理，并部分去除第二侧墙底部的氧化层，使得剩余氧化层底部具有切角；对经过清洗处理之后的初始沟槽进行第二刻蚀，形成所述沟槽。
可选的，所述第一刻蚀工艺为干法刻蚀。
可选的，对所述初始沟槽进行清洗处理的步骤中，采用稀释的HF清洗所述初始沟槽。
可选的，所述第二刻蚀工艺为湿法刻蚀。
可选的，所述氧化层的材料为氧化硅。
可选的，所述氧化层的厚度在20埃至30埃范围内。
可选的，形成所述氧化层的工艺为氧化生长、化学气相沉积或者原子层沉积。
可选的，所述第一侧墙和所述第二侧墙的材料为氮化物。
可选的，所述第二侧墙的厚度在100埃至180埃范围内。
可选的，所述沟槽具有Σ形状。
可选的，形成所述沟槽之后，还包括：形成填充满所述沟槽的源漏外延掺杂层。
相应地，本发明还提供一种半导体结构，包括：基底，所述基底上具有栅极；第一侧墙，位于所述栅极侧壁上；氧化层，位于第一侧墙两侧的基底上，所述氧化层底部具有切角；第二侧墙，位于所述第一侧墙侧壁上，所述栅极、所述第一侧墙和所述第二侧墙构成栅极结构；沟槽，位于所述栅极结构两侧的氧化层和基底内。
可选的，所述氧化层的材料为氧化硅。
与现有技术相比，本发明的技术方案具有以下优点：
先在所述栅极的侧壁上形成第一侧墙；形成第一侧墙后，于基底上形成氧化层；在所述第一侧墙的侧壁上形成第二侧墙，使得所述栅极、所述第一侧墙和所述第二侧墙构成叠层的栅极结构。所述氧化层在形成第一侧墙之后形成，在第二侧墙形成之前形成，从而使得所述第二侧墙底部与所述基底之间还具有氧化层。在形成所述沟槽的步骤中，需要去除位于所述栅极结构两侧的氧化层和基底，受刻蚀选择性的影响，所述第一侧墙和第二侧墙不被去除，所述氧化层和基底则被部分去除。由于位于所述第二侧墙底部与所述基底之间的氧化层也同时被部分去除，使得剩余氧化层底部具有切角，从而使得所述沟槽能够产生较大的应力，且所述沟槽距离半导体结构沟道的距离小，从而使得后续填充满所述沟槽的源漏外延掺杂层的电阻小，因此改善了所述半导体结构的电学性能。
可选技术方案中，所述氧化层的厚度在20埃至30埃范围内。将所述氧化层的厚度控制在合理的范围内，能够实现使所述沟槽产生较大应力的同时，又距离所述半导体结构沟道的距离较小。若所述氧化层的厚度过大，则会导致所述凹槽产生的应力小，从而不利于减小后续源漏外延掺杂层的电阻；若所述氧化层的厚度过小，则会造成工艺难度的加大。
附图说明
图1是一种半导体结构的结构示意图；
图2至图10是本发明实施例半导体结构形成过程各个步骤对应的结构示意图。
具体实施方式
根据背景技术形成的半导体结构的电学性能有待提高。图1示出了一种半导体结构的结构示意图，现结合图1对半导体结构的电学性能有待提高的原因进行分析。
参考图1，所述半导体结构包括：基底100，所述基底100上具有栅极110；侧墙120，位于所述栅极110的侧壁上；源漏外延掺杂层130，位于所述栅极110两侧的基底100内。
上述半导体结构的电学性能有待提高。
经分析发现，导致所述半导体结构电学性能有待提高的原因包括：形成所述源漏外延掺杂层130的步骤包括：刻蚀位于所述栅极110两侧的基底100，形成沟槽(图未示)；形成填充满所述沟槽的源漏外延掺杂层130。由于所述源漏外延掺杂层130的应力小，且所述源漏外延层130距离半导体结构沟道的距离大，导致所述半导体结构的电学性能有待提高。
为了解决上述问题，本发明提供一种半导体结构的形成方法，包括：提供基底，所述基底上形成有栅极；在所述栅极的侧壁上形成第一侧墙；形成第一侧墙后，于基底上形成氧化层；在所述第一侧墙的侧壁上形成第二侧墙，所述栅极、所述第一侧墙和所述第二侧墙构成栅极结构；在所述栅极结构两侧的氧化层和基底中形成沟槽。
在去除位于栅极结构两侧的氧化层和基底，由于位于所述第二侧墙底部与所述基底之间的氧化层也被部分去除，使得剩余氧化层底部具有切角，从而使得所述沟槽能够产生较大的应力，且距离所述半导体结构沟道的距离小，从而减小了后续源漏外延掺杂层的电阻，因此使得所述半导体结构的电学性能得到改善。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图2至图10是本发明实施例半导体结构形成过程各步骤对应的结构示意图。
参考图2，提供基底200，所述基底200上形成有栅极210。
本实施例中，所述基底200为用于形成PMOS器件的衬底，相应地，本实施例形成的半导体结构为PMOS器件。在本发明其他实施例中，所述基底还可以为：用于形成PMOS器件的衬底或者用于形成NMOS器件的衬底。
本实施例中，所述基底200的材料为硅。在本发明其他实施例中，所述基底的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟。在其他实施例中，所述基底还可以为绝缘体上的硅衬底或者绝缘体上的锗衬底。
本实施例中，所述栅极210包括多晶硅栅极或者金属栅极。
本实施例中，形成所述栅极210的步骤包括：在所述基底200上形成栅极膜；在所述栅极膜上形成硬掩膜；以所述硬掩膜为掩膜刻蚀所述栅极膜，形成所述栅极210；形成所述栅极210之后，去除所述硬掩膜。
结合参考图3和图4，在所述栅极210的侧壁上形成第一侧墙221。
参考图3，在所述栅极210的顶部和侧壁以及所述基底200上形成第一侧墙膜220。
本实施例中，所述第一侧墙膜220的材料为氮化物。具体为：氮化硅、碳氮化硅、硼氮化硅中的一种或者多种。
本实施例中，形成所述第一侧墙膜220的工艺为化学气相沉积或者原子层沉积。
参考图4，去除位于所述栅极210顶部以及所述基底200上的第一侧墙膜220，形成第一侧墙221，所述第一侧墙221位于所述栅极210的侧壁上。
本实施例中，所述第一侧墙221的作用是用于定义后续形成的源漏外延掺杂层的位置。所述第一侧墙221的材料为氮化物。具体为：氮化硅、碳氮化硅、硼氮化硅中的一种或者多种。
本实施例中，去除位于所述栅极210顶部以及所述基底200上的第一侧墙膜220的工艺为干法刻蚀工艺。
参考图5，形成第一侧墙221后，于基底200上形成氧化层230。
本实施例中，所述氧化层230的材料与所述第一侧墙221的材料不同。所述氧化层230的材料为氧化硅。
本实施例中，所述氧化层230的厚度既不能过大也不能过小。若所述氧化层230的厚度过大，则会使得刻蚀方向与垂直于所述基底200表面的方向之间的夹角小，导致后续凹槽产生的应力小，从而不利于减小后续源漏外延掺杂层的电阻；若所述氧化层230的厚度过小，则会造成工艺难度的加大。因此，所述氧化层230的厚度在20埃至30埃范围内。
本实施例中，形成所述氧化层230的工艺为氧化生长。采用氧化生长的工艺，在所述第一侧墙221露出的基底200上形成氧化层230，起到了简化工艺流程的作用。
参考图6，在所述第一侧墙221的侧壁上形成第二侧墙240，所述栅极210、所述第一侧墙221和所述第二侧墙240构成栅极结构(未标示)。
本实施例中，所述第二侧墙240与所述第一侧墙221都起到定义后续源漏外延掺杂层位置的作用。
本实施例中，所述栅极结构是由所述栅极210、所述第一侧墙221和所述第二侧墙240构成的叠层结构。所述第二侧墙240的材料为氮化物。具体为：氮化硅、碳氮化硅、硼氮化硅中的一种或者多种。
本实施例中，所述第二侧墙240的厚度既不能过大也不能过小。若所述第二侧墙240的厚度过大，则会相邻栅极结构的距离过小，无法满足半导体结构尺寸的要求；若所述第二侧墙240的厚度过小，则会导致后续沟槽产生的应力小。因此，所述第二侧墙240的厚度在100埃至180埃范围内。
结合参考图7和图9，在所述栅极结构两侧的氧化层230和基底200中形成沟槽260(如图9所示)。
本实施例中，所述沟槽260为Σ形状。在本发明其他实施例中，所述沟槽260的形状还可以为：矩形或者方形。
以下将结合附图对所述沟槽260的形成过程做详细说明。
参考图7，对所述栅极结构两侧的氧化层230和基底200进行第一刻蚀，形成初始沟槽250。
本实施例中，所述初始沟槽250为矩形。在本发明其他实施例中，所述初始沟槽250还可以为Σ形状或者方形。
本实施例中，所述第一刻蚀工艺为干法刻蚀。
参考图8，对所述初始沟槽250(参考图7)进行清洗处理，并部分去除第二侧墙240底部的氧化层230，使得剩余氧化层底部具有切角。
本实施例中，对所述初始沟槽250进行清洗不仅可以去除第二侧墙240底部的部分氧化层230，使得剩余氧化层底部具有切角，从而使得后续形成的沟槽能够产生较大的应力；同时所述清洗还可以去除所述初始沟槽250内的杂质，提高所述初始沟槽250的清洁度，从而使得后续形成的沟槽质量得到提高。由于后续在所述沟槽内形成源漏外延掺杂层，相应地也使得所述源漏外延掺杂层的质量得到提高。
具体地，对所述初始沟槽250进行清洗处理的步骤中，采用稀释的HF清洗所述初始沟槽250。所述稀释的HF能够进一步腐蚀位于第二侧墙240底部的部分氧化层230，从而露出所述第二侧墙240的底部，为后续进行第二刻蚀提供工艺基础。
参考图9，对经过清洗处理之后的初始沟槽250进行第二刻蚀，形成所述沟槽260。
本实施例中，由于位于第二侧墙240底部的氧化层230得以部分去除，从而使得剩余氧化层230的底部具有切角，从而使得所述沟槽260能够产生较大的应力。此外，所述沟槽260的位置紧临所述第二侧墙240，因此所述沟槽260距离半导体结构沟道的距离也较小。结合上述两个方面，本发明使得后续源漏外延掺杂层的电阻得到减小，从而改善了所述半导体结构的电学性能。
本实施例中，所述第二刻蚀工艺为湿法刻蚀。
参考图10，形成填充满所述沟槽260(参考图9)的源漏外延掺杂层270。
本实施例中，由于所述沟槽260能够产生较大的应力，且距离所述半导体结构沟道的距离小，从而减小了所述源漏外延掺杂层270的电阻，进而提高了所述半导体结构的电学性能。
本实施例中，所述基底200为用于形成PMOS器件的衬底，相应地，所述源漏外延掺杂层270的材料为锗化硅。所述源漏外延掺杂层270起到向沟道提供压应力的作用，并提高PMOS器件的载流子迁移率。
相应地，本发明还提供一种半导体结构，参考图9，包括：基底200，所述基底200上具有栅极210；第一侧墙221，位于所述栅极210侧壁上；氧化层230，位于第一侧墙221两侧的基底200上，所述氧化层230底部具有切角；第二侧墙240，位于所述第一侧墙221侧壁上，所述栅极210、所述第一侧墙221和所述第二侧墙240构成栅极结构；沟槽260，位于所述栅极结构两侧的氧化层230和基底200内。
本实施例中，所述沟槽260能够产生较大的应力，且所述沟槽260距离半导体结构的距离小，从而使得后续源漏外延掺杂层的电阻小，因此使得所述半导体结构的电学性能得到改善。
本实施例中，所述氧化层230的材料与所述第一侧墙221的材料不同。所述氧化层230的材料为氧化硅。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (14)

1.一种半导体结构的形成方法，其特征在于，包括：
提供基底，所述基底上形成有栅极；
在所述栅极的侧壁上形成第一侧墙；
形成第一侧墙后，于基底上形成氧化层；
在所述第一侧墙的侧壁上形成第二侧墙，所述栅极、所述第一侧墙和所述第二侧墙构成栅极结构；
在所述栅极结构两侧的氧化层和基底中形成沟槽。
2.如权利要求1所述的半导体结构的形成方法，其特征在于，形成所述沟槽的步骤包括：
对所述栅极结构两侧的氧化层和基底进行第一刻蚀，形成初始沟槽；
对所述初始沟槽进行清洗处理，并部分去除第二侧墙底部的氧化层，使得剩余氧化层底部具有切角；
对经过清洗处理之后的初始沟槽进行第二刻蚀，形成所述沟槽。
3.如权利要求2所述的半导体结构的形成方法，其特征在于，所述第一刻蚀工艺为干法刻蚀。
4.如权利要求2所述的半导体结构的形成方法，其特征在于，对所述初始沟槽进行清洗处理的步骤中，采用稀释的HF清洗所述初始沟槽。
5.如权利要求2所述的半导体结构的形成方法，其特征在于，所述第二刻蚀工艺为湿法刻蚀。
6.如权利要求1所述的半导体结构的形成方法，其特征在于，所述氧化层的材料为氧化硅。
7.如权利要求6所述的半导体结构的形成方法，其特征在于，所述氧化层的厚度在20埃至30埃范围内。
8.如权利要求7所述的半导体结构的形成方法，其特征在于，形成所述氧化层的工艺为氧化生长、化学气相沉积或者原子层沉积。
9.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第一侧墙和所述第二侧墙的材料为氮化物。
10.如权利要求9所述的半导体结构的形成方法，其特征在于，所述第二侧墙的厚度在100埃至180埃范围内。
11.如权利要求1所述的半导体结构的形成方法，其特征在于，所述沟槽具有Σ形状。
12.如权利要求1所述的半导体结构的形成方法，其特征在于，形成所述沟槽之后，还包括：形成填充满所述沟槽的源漏外延掺杂层。
13.一种半导体结构，其特征在于，包括：
基底，所述基底上具有栅极；
第一侧墙，位于所述栅极侧壁上；
氧化层，位于第一侧墙两侧的基底上，所述氧化层底部具有切角；
第二侧墙，位于所述第一侧墙侧壁上，所述栅极、所述第一侧墙和所述第二侧墙构成栅极结构；
沟槽，位于所述栅极结构两侧的氧化层和基底内。
14.如权利要求13所述的半导体结构，其特征在于，所述氧化层的材料为氧化硅。
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