CN108804275A - A kind of server electrifying timing sequence detection method and system based on CPLD-FPGA - Google Patents
A kind of server electrifying timing sequence detection method and system based on CPLD-FPGA Download PDFInfo
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- CN108804275A CN108804275A CN201810287686.5A CN201810287686A CN108804275A CN 108804275 A CN108804275 A CN 108804275A CN 201810287686 A CN201810287686 A CN 201810287686A CN 108804275 A CN108804275 A CN 108804275A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/28—Error detection; Error correction; Monitoring by checking the correct order of processing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
- G06F11/324—Display of status information
- G06F11/325—Display of status information by lamps or LED's
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Elimination Of Static Electricity (AREA)
Abstract
The present invention provides a kind of server electrifying timing sequence detection method and system based on CPLD-FPGA, the method includes：S101, setting state machine registers；Under S102, current state, current VR is opened, and PWRGD signals are exported through CPLD-FPGA；S103, when monitoring PWRGD signals, state machine registers preserve current state value, and light test LED；If S104, current VR are enabled, state machine enters NextState, and carries out the unlatchings of the VR under NextState；If current VR is enabled abnormal, retain current state value；S105, each electricity condition is shown successively.The present invention solve the problems, such as to need when server power up test gradually to be measured with multimeter it is non-intuitive caused by voltage, realize server power-up state intuitively show, improve power up test efficiency.And the present invention effectively reduces the number that other monitor single electric signal LED, reduces PCB surface product, reduces manufacturing cost.
Description
Technical field
The present invention relates to server data Center Technology field, especially a kind of server based on CPLD-FPGA powers on
Time-series rules method and system.
Background technology
The control of server electrifying timing sequence is the important component of entire server booting, the wherein control units such as electrifying timing sequence
Divide and is realized by programming device CPLD/FPGA.CPLD/FPGA is the application-specific integrated circuit of semi-custom, have it is programmable,
The number of advantages such as integrated level height have been more and more widely used in exploitation verification and application field, in server design field,
CPLD/FPGA be substantially carried out power on and under reply by cable the interface communications such as miscellaneous timing control, I2C and indicator light control etc..
At the beginning of returning board test, first having to boot up debugging, smoothly booting is the premise that follow-up additional function is realized, this
On the one hand CPLD/FPGA designers is required to do sufficient simulating, verifying on the basis of ensureing that design code is correct early period, including
Functional simulation, Gate Level Simulation and time stimulatiom etc., but on actual hardware circuit board, it may be due to CPLD/FPGA plate grade time delays
Or the problems such as hardware circuit rosin joint itself, it cannot be guaranteed that smoothly booting.Electronics Engineer must just position sequential and run at this time
Which step, to be directed to problem adjustment CPLD/FPGA designs or hardware circuit, Electronics Engineer passes through general-purpose in traditional design
Table measures electric signal with orientation problem, or prompts Electronics Engineer by limited crucial electric signal indicator light.But this side
Formula is unfavorable for Electronics Engineer's quick positioning question to realize quick solve the problems, such as and quick turn-on, another party will pass through specially
LED detects all electric signals, and this realization is most intuitive, most beneficial for debugging, but can accordingly increase PCB space and LED numbers, increases
Addition sheet.
Invention content
The object of the present invention is to provide a kind of server electrifying timing sequence detection method and system based on CPLD-FPGA, purport
It needs gradually to measure the non-intuitive problem caused by voltage with multimeter in settlement server power up test, realizes server
Power-up state is intuitively shown, improves power up test efficiency.
To reach above-mentioned technical purpose, the server electrifying timing sequence detection based on CPLD-FPGA that the present invention provides a kind of
Method includes the following steps：
S1, setting state machine registers；
Under S2, current state, current VR is opened, and PWRGD signals are exported through CPLD-FPGA；
S3, when monitoring PWRGD signals, state machine registers preserve current state value, and light test LED；
If S4, current VR (Voltage Regulator, voltage regulator) are enabled, state machine enters NextState, and
The VR carried out under NextState is opened；If current VR is enabled abnormal, retain current state value；
S5, each electricity condition is shown successively.
Preferably, real-time preservation and output of the state machine registers for state machines state value, as test LED shapes
The control terminal of state.
Preferably, the step S3 specifically includes following operation：
S301, when PWGRD be " 1 " when, state machine registers preserve current state value；
S302, output current state value, the control terminal as test LED.
Preferably, further include regulation resistance in the link of the LED, the regulation resistance is used for adjusting brightness of LED lamps.
The server electrifying timing sequence detecting system based on CPLD-FPGA that the present invention also provides a kind of, including：
State machine registers module, for state machine registers to be arranged；
Signal conversion module exports PWRGD signals under current state, opening current VR, and through CPLD-FPGA；
LED lights module, for when monitoring PWRGD signals, state machine registers to preserve current state value, and light
Test LED；
VR enables monitoring modular, if enabled for current VR, state machine enters NextState, and carries out under NextState
VR open；If current VR is enabled abnormal, retain current state value；
Electrify state display module, for showing each electricity condition successively.
Preferably, real-time preservation and output of the state machine registers for state machines state value, as test LED shapes
The control terminal of state.
Preferably, the LED lights module and includes：
PWRGD signal monitoring units, for when PWGRD is " 1 ", state machine registers to preserve current state value；
State value output unit, for exporting current state value, the control terminal as test LED.
Preferably, further include regulation resistance in the link of the LED, the regulation resistance is used for adjusting brightness of LED lamps.
The effect provided in invention content is only the effect of embodiment, rather than invents all whole effects, above-mentioned
A technical solution in technical solution has the following advantages that or advantageous effect：
Compared with prior art, the present invention preserves state machine by the way that state machine registers are arranged according to VR open states
State value, and test LED is sent it to, as the control terminal of test LED light light on and off, so as to according to the light on and off of LED reality
When monitoring server power-up state, need gradually to be measured caused by voltage not with multimeter when solving server power up test
Intuitive problem realizes that server power-up state is intuitively shown, improves power up test efficiency.And the present invention effectively reduces it
He monitors the number of single electric signal LED, reduces PCB surface product, reduces manufacturing cost.
Description of the drawings
Fig. 1 is a kind of server electrifying timing sequence detection method based on CPLD-FPGA provided in the embodiment of the present invention
Flow chart；
Fig. 2 is a kind of CPLD-FPGA structural schematic diagrams provided in the embodiment of the present invention；
Fig. 3 is a kind of server electrifying timing sequence detecting system based on CPLD-FPGA provided in the embodiment of the present invention
Structure diagram.
Specific implementation mode
In order to clearly illustrate the technical characterstic of this programme, below by specific implementation mode, and its attached drawing is combined, to this
Invention is described in detail.Following disclosure provides many different embodiments or example is used for realizing the different knots of the present invention
Structure.In order to simplify disclosure of the invention, hereinafter the component of specific examples and setting are described.In addition, the present invention can be with
Repeat reference numerals and/or letter in different examples.This repetition is that for purposes of simplicity and clarity, itself is not indicated
Relationship between various embodiments and/or setting is discussed.It should be noted that illustrated component is not necessarily to scale in the accompanying drawings
It draws.Present invention omits the descriptions to known assemblies and treatment technology and process to avoid the present invention is unnecessarily limiting.
It is provided for the embodiments of the invention a kind of server electrifying timing sequence inspection based on CPLD-FPGA below in conjunction with the accompanying drawings
Method and system is surveyed to be described in detail.
As shown in Figure 1, the embodiment of the invention discloses a kind of server electrifying timing sequence detection side based on CPLD-FPGA
Method includes the following steps：
S1, setting state machine registers；
Under S2, current state, current VR is opened, and PWRGD signals are exported through CPLD-FPGA；
S3, when monitoring PWRGD signals, state machine registers preserve current state value, and light test LED；
If S4, current VR are enabled, state machine enters NextState, and carries out the unlatchings of the VR under NextState；If worked as
Preceding VR is enabled abnormal, then retains current state value；
S5, each electricity condition is shown successively.
On the server in electric process, the PWGRD signals that CPLD-FPGA is inputted according to each electric signal are next to carry out
Electricity enables, i.e. CPLD-FPGA is the VR that next electricity is enabled according to a upper electric PWGRD, if a upper electric PWGRD
For " 1 " (" 0 " indicates not rise, and " 1 " indicates to have risen), CPLD-FPGA controls the enabled unlatching of next electricity, otherwise, CPLD-FPGA
Control the not enabled unlatching of next electricity.
As shown in Fig. 2, during electrifying timing sequence controls, state machine registers are set, state machine state are carried out real-time
Retain, deposit and exports.Reflect and preserve the state value of state machine in real time by state machine registers, then in real time by this
State value exports and controls the state of DEBUG LED.Since the unlatching of specific VR carries out in particular state, so passing through
LED indication state value can accurately reflect the state of VR.S0 states are shown when opening P12V VR, when P12V_PWGRD is " 1 "
When, state machine can enter S1 states, can open P5V VR, DEBUG LED meetings dispaly state at this time and be in S1 states, work as P5V_
When PWGRD is " 1 ", state machine can enter S2 states, and so on, DEBUG LED real-time display state machines state value.
Using the state machines state value of output as the control terminal of test LED, when detecting electric signal, LED state lamp is
It is bright.Increase regulation resistance in each LED links, by changing the resistance value size of regulation resistance, the bright journey of LED light can be adjusted
Degree.
It is as follows that electrifying timing sequence controls process：
The unlatching of P12V VR is carried out in S0 states, P12V_PWRGD can be exported by P12V VR later, at this time DEBUG
LED just shows S0 states by LED light on and off, if P12V VR all without enabled, DEBUG LED can be shown in this state it
Preceding IDLE state；If P12V VR are normally enabled, state machine can enter S1 states, and holding for P5V VR can be carried out in S1 states
It opens, P5V_PWRGD can be exported by P5V VR later, and DEBUG LED just show S1 states by LED light on and off at this time, if P5V
For VR all without enabled, DEBUG LED can be shown in the S0 states before this state；According to above-mentioned principle, show successively each
Play electricity condition.
The embodiment of the present invention preserves the state value of state machine by the way that state machine registers are arranged according to VR open states, and
Test LED is sent it to, as the control terminal of test LED light light on and off, so as to monitor service in real time according to the light on and off of LED
Device power-up state, need gradually to be measured with multimeter caused by voltage when solving server power up test non-intuitive asks
Topic realizes that server power-up state is intuitively shown, improves power up test efficiency.And the present invention effectively reduces other monitoring lists
The number of a electric signal LED reduces PCB surface product, reduces manufacturing cost.
As shown in figure 3, the embodiment of the invention also discloses a kind of server electrifying timing sequence detection system based on CPLD-FPGA
System, including：
State machine registers module, for state machine registers to be arranged；
Signal conversion module exports PWRGD signals under current state, opening current VR, and through CPLD-FPGA；
LED lights module, for when monitoring PWRGD signals, state machine registers to preserve current state value, and light
Test LED；
VR enables monitoring modular, if enabled for current VR, state machine enters NextState, and carries out under NextState
VR open；If current VR is enabled abnormal, retain current state value；
Electrify state display module, for showing each electricity condition successively.
Real-time preservation and output of the state machine registers for state machines state value, the control as test LED state
End processed.
The LED lights module：
PWRGD signal monitoring units, for when PWGRD is " 1 ", state machine registers to preserve current state value；
State value output unit, for exporting current state value, the control terminal as test LED.
Further include regulation resistance in the link of the LED, the regulation resistance is used for adjusting brightness of LED lamps.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement etc., should all be included in the protection scope of the present invention made by within refreshing and principle.
Claims (8)
1. a kind of server electrifying timing sequence detection method based on CPLD-FPGA, which is characterized in that include the following steps：
S1, setting state machine registers；
Under S2, current state, current VR is opened, and PWRGD signals are exported through CPLD-FPGA；
S3, when monitoring PWRGD signals, state machine registers preserve current state value, and light test LED；
If S4, current VR are enabled, state machine enters NextState, and carries out the unlatchings of the VR under NextState；If current VR
It is enabled abnormal, then retain current state value；
S5, each electricity condition is shown successively.
2. a kind of server electrifying timing sequence detection method based on CPLD-FPGA according to claim 1, feature exist
In, real-time preservation and output of the state machine registers for state machines state value, the control terminal as test LED state.
3. a kind of server electrifying timing sequence detection method based on CPLD-FPGA according to claim 2, feature exist
In the step S3 specifically includes following operation：
S301, when PWGRD be " 1 " when, state machine registers preserve current state value；
S302, output current state value, the control terminal as test LED.
4. a kind of server electrifying timing sequence detection method based on CPLD-FPGA according to claim 1-3 any one,
It is characterized in that, further including regulation resistance in the link of the LED, the regulation resistance is used for adjusting brightness of LED lamps.
5. a kind of server electrifying timing sequence detecting system based on CPLD-FPGA, which is characterized in that including：
State machine registers module, for state machine registers to be arranged；
Signal conversion module exports PWRGD signals under current state, opening current VR, and through CPLD-FPGA；
LED lights module, for when monitoring PWRGD signals, state machine registers to preserve current state value, and light test
LED；
VR enables monitoring modular, if enabled for current VR, state machine enters NextState, and carries out the VR under NextState
It opens；If current VR is enabled abnormal, retain current state value；
Electrify state display module, for showing each electricity condition successively.
6. a kind of server electrifying timing sequence detecting system based on CPLD-FPGA according to claim 5, feature exist
In, real-time preservation and output of the state machine registers for state machines state value, the control terminal as test LED state.
7. a kind of server electrifying timing sequence detecting system based on CPLD-FPGA according to claim 6, feature exist
In the LED lights module and includes：
PWRGD signal monitoring units, for when PWGRD is " 1 ", state machine registers to preserve current state value；
State value output unit, for exporting current state value, the control terminal as test LED.
8. a kind of server electrifying timing sequence detecting system based on CPLD-FPGA according to claim 5-7 any one,
It is characterized in that, further including regulation resistance in the link of the LED, the regulation resistance is used for adjusting brightness of LED lamps.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810287686.5A CN108804275A (en) | 2018-04-03 | 2018-04-03 | A kind of server electrifying timing sequence detection method and system based on CPLD-FPGA |
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| CN201810287686.5A CN108804275A (en) | 2018-04-03 | 2018-04-03 | A kind of server electrifying timing sequence detection method and system based on CPLD-FPGA |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109633349A (en) * | 2018-12-11 | 2019-04-16 | 郑州云海信息技术有限公司 | A kind of device of quick detection abnormal voltage position |
| CN110032264A (en) * | 2019-04-16 | 2019-07-19 | 苏州浪潮智能科技有限公司 | A kind of progress control method of server, equipment and storage medium |
| CN110737234A (en) * | 2019-10-21 | 2020-01-31 | 江苏云涌电子科技股份有限公司 | internal network safety monitoring device |
| CN111258380A (en) * | 2020-01-20 | 2020-06-09 | 江苏龙威中科技术有限公司 | COM-E functional mainboard based on Loongson 2K1000 main processing chip |
| US11579673B2 (en) * | 2021-04-28 | 2023-02-14 | Quanta Compter Inc. | Systems and methods for storing FSM state data for a power control system |
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| CN109633349A (en) * | 2018-12-11 | 2019-04-16 | 郑州云海信息技术有限公司 | A kind of device of quick detection abnormal voltage position |
| CN110032264A (en) * | 2019-04-16 | 2019-07-19 | 苏州浪潮智能科技有限公司 | A kind of progress control method of server, equipment and storage medium |
| CN110737234A (en) * | 2019-10-21 | 2020-01-31 | 江苏云涌电子科技股份有限公司 | internal network safety monitoring device |
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| CN111258380A (en) * | 2020-01-20 | 2020-06-09 | 江苏龙威中科技术有限公司 | COM-E functional mainboard based on Loongson 2K1000 main processing chip |
| US11579673B2 (en) * | 2021-04-28 | 2023-02-14 | Quanta Compter Inc. | Systems and methods for storing FSM state data for a power control system |
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Application publication date: 20181113 |