CN108776645A - A kind of Embedded Multi-task managing device - Google Patents
A kind of Embedded Multi-task managing device Download PDFInfo
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- CN108776645A CN108776645A CN201810549736.2A CN201810549736A CN108776645A CN 108776645 A CN108776645 A CN 108776645A CN 201810549736 A CN201810549736 A CN 201810549736A CN 108776645 A CN108776645 A CN 108776645A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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Abstract
The invention discloses a kind of Embedded Multi-task managing devices, program storage, data storage A, checksum memory and the FPGA controller being electrically connected therewith including MCU processor and respectively, optical fiber interface, 1553B interfaces, LVDS interface, RS422 interfaces, the data storage B being electrically connected respectively with FPGA controller, and to power module that each memory, interface, processor, controller are powered.External interface of the present invention is abundant, from the 1553B buses, the LVDS buses of RS422 buses to high speed and optical fiber of low speed, covers currently used all communication interfaces, meets General design requirement；Transmission bandwidth is high, and from 1Mbps to 4.25Gbps, transmission bandwidth improves 3 magnitudes；Scalability is strong, the memory capacity of program storage, data storage A, checksum memory, data storage B, optical fiber interface, 1553B interfaces, LVDS interface, RS422 interfaces quantity can be extended or back up according to actual needs, to meet the design needs of different function radar.
Description
Technical field
The present invention relates to a kind of spaceborne phase array radar task management technology more particularly to a kind of Embedded Multi-tasks
Managing device.
Background technology
Task management plate is one of important composition single machine of spaceborne phase array radar, main to complete radar control instruction solution
Analysis, transmission and control function.In particular, task management plate is responsible for and Satellite Management Platform communication, what receiving platform was sent
Control instruction is parsed and is forwarded, and is controlled next stage digital transmitting and receiving unit, and collects the BIT states of radar each unit
Return to Satellite Management platform.Since the function before task management plate is relatively simple, 8 8-digit microcontroller of generally use in design
CPLD or low side FPGA is coordinated to complete.The external interface of task management plate mainly based on 1553B buses and RS422 buses, and
The traffic rate of 1553B buses only has 1Mbps, the traffic rate of RS422 buses to be also no more than 10Mbps, and the two belongs to low speed
Communication bus.
However, as spaceborne phase array radar function is increasingly complicated, task management plate is promoted not only to improve transmission bandwidth,
Abundant interface type, and should also have data processing, signal processing ability.Meanwhile it constantly replacing hardware design and being unfavorable for
The reliability for ensureing space product design, so the versatility of Hardware platform design, scalability have become space industry hardware
The inexorable trend of design.
Invention content
Technical problem to be solved by the present invention lies in：Existing spaceborne task management device interface is single, communication bandwidth, leads to
It is insufficient with property and extended capability, provide a kind of Embedded Multi-task managing device.
The present invention is that solution above-mentioned technical problem, the present invention include MCU processor and divide by the following technical programs
Program storage, data storage A, checksum memory and the FPGA controller not being electrically connected therewith are controlled with FPGA respectively
Optical fiber interface, 1553B interfaces, LVDS interface, RS422 interfaces, the data storage B of device electric connection, and to each storage
The power module that device, interface, processor, controller are powered；
Expansion interface of the FPGA controller as MCU processor, the FPGA controller pass through 1553B interfaces
The control command and transmission working status parameter of Satellite Management platform give Satellite Management platform, the FPGA controller to pass through
The pps pulse per second signal of RS422 interface Satellite Management platforms simultaneously transmits and surveys high data and give Satellite Management platform, the FPGA controls
Treated that echo data gives Satellite Management platform, the FPGA controller to pass through optical fiber interface by LVDS interface transmission for device processed
Raw radar data is received, row distance of going forward side by side compensation, process of pulse-compression, the data storage B is for storing from next
The raw radar data of the digital Transmit-Receive Unit of grade；
Described program memory is used for storage program area, application program and intermediate data, and the data storage A is used for
The running data of temporary program, temporary data can lose after power down, and the checksum memory is used to store the mistake of operation
Error detection and the check code for correcting EDAC.
The MCU processor is a piece of AT697F processors, and program storage is two panels 3DFO64M16VS1281 chips,
FPGA controller is a piece of XQ5VX100T controllers, and data storage A is a piece of AT68166F chips, checksum memory one
Piece AT60142FT chips, data storage B are two panels 3DSR32M32VS8504 chips.
The AT697F processors pass through address bus ADDR2~ADDR23, data/address bus DATA0~DATA31, FLASH
Piece selects control line FLASH_CS0, FLASH write line FLASH_WE, FLASH to read control line FLASH_OE, FLASH state instruction
Line BRDYN is connected with the corresponding pin of 3DFO64M16VS1281 chips, and XQ5VX100T controllers reset control line by FLASH
FLASH_RST, FLASH byte control line FLASH1_BYTE, FLASH2_BYTE and 3DFO64M16VS1281 chip corresponding pin
It is connected, realizes the access of 16M byte programs.
The AT697F processors pass through address bus ADDR2~ADDR20, data/address bus DATA0~DATA31, SRAM
Write controlling bus SRAM_WE0~SRAM_WE3, SRAM pieces select control line SRAM_CS0, SRAM read control line SRAM_OE0 with
The corresponding pin of AT68166F chips is connected, and realizes the access of 2M byte datas.
The AT697F processors by address bus ADDR2~ADDR20, data/address bus CBDATA0~CBDATA7,
SRAM write control line SRAM_WE0, SRAM piece selects control line SRAM_CS0, SRAM to read control line SRAM_OE0 and AT60142FT core
The corresponding pin of piece is connected, and realizes the access of 512K byte verification datas.
The AT697F processors pass through address bus ADDR0~ADDR27, data/address bus DATA0~DATA31, SRAM
Write controlling bus SRAM_WE0~SRAM_WE3, SRAM pieces select controlling bus SRAM_CS0~SRAM_CS4, SRAM to read control always
Line SRAM_OE0~SRAM_OE3, control line PIO3_MCU_FPGA, control line PIO4_MCU_FPGA, control line PIO5_MCU_
FPGA, control line PIO6_MCU_FPGA, DONE signal wire, PROGRAM signal wires, V4RST signal wires and XQ5VX100T are controlled
The corresponding pin of device is connected, and realizes communication and control with XQ5VX100T controllers.
The XQ5VX100T controllers pass through address bus SRAM_ADDR_A0~SRAM_ADDR_A16, data/address bus
SRAM_DATA_A0~SRAM_DATA_A31, SRAM pieces select controlling bus SRAM_CS_N_A0~SRAM_CS_N_A7, read control
Line SRAM_OE_N_A, write line SRAM_WE_N_A and SRAM_HA0_A, SRAM_LA0_A, SRAM_LB_N_A, SRAM_
UB_N_A signal wires are connected with the corresponding pin of a piece of 3DSR32M32VS8504 chips, while passing through address bus SRAM_
ADDR_B0~SRAM_ADDR_B16, data/address bus SRAM_DATA_B0~SRAM_DATA_B31, SRAM pieces select controlling bus
SRAM_CS_N_B0~SRAM_CS_N_B7, control line SRAM_OE_N_B, write line SRAM_WE_N_B and SRAM_ are read
Pair of HA0_B, SRAM_LA0_B, SRAM_LB_N_B, SRAM_UB_N_B signal wire and another 3DSR32M32VS8504 chip
It answers pin to be connected, realizes the access of 8M byte datas.
The two-way tail fiber type optical fiber transceiver module HTS8253-FD- of optical module model double-fiber that the optical fiber interface uses
S001, traffic rate are up to 4.25Gbps.
The 1553B interfaces include 16 bidirectional bus transceivers of a piece of B65170S6RH bus control units and three pieces
B54ACS164245S, the LVDS interface include a piece of lvds driver DS90LV031A and a piece of LVDS receiver
DS90LV032A, the RS422 interfaces include a piece of RS422 drivers DS26LV31W and a piece of RS422 receivers
DS26LV32W。
Power module output+the 5V ,+3.3V ,+2.5V ,+1.8V ,+1.2V and+1.0V totally six kinds of voltage values, wherein
The operating voltage of MCU processor is+3.3V and+1.8V, the operating voltage of FPGA controller is+3.3V ,+2.5V ,+1.2V and+
1.0V, program storage, data storage A, checksum memory, optical fiber interface, LVDS interface, RS422 interfaces, data storage
The operating voltage of B is+3.3V, and the operating voltage of 1553B interfaces is+5V and+3.3V.
Use 32 embeded processors of anti-irradiation high-speed for core, outside extension possesses 330,000 logic units
Virtex-5 Series FPGAs, fast, resourceful, the powerful task management plate general hardware platform of structure processing speed.
The present invention has the following advantages compared with prior art：External interface of the present invention is abundant, from the 1553B buses of low speed,
RS422 buses cover currently used all communication interfaces, meet General design to the LVDS buses and optical fiber of high speed
It is required that；Transmission bandwidth is high, and from 1Mbps to 4.25Gbps, transmission bandwidth improves 3 magnitudes；Scalability is strong, program storage
The memory capacity of device, data storage A, checksum memory, data storage B, optical fiber interface, 1553B interfaces, LVDS interface,
The quantity of RS422 interfaces can be extended or back up according to actual needs, to meet the design needs of different function radar.
Description of the drawings
Fig. 1 is the structure diagram of the present invention；
Fig. 2 is the controlling switch structural schematic diagram of AT697F processor external connections；
Fig. 3 is the electric power thus supplied schematic diagram of AT697F processors；
Fig. 4 is the circuit diagram of a piece of 3DFO64M16VS1281 chips；
Fig. 5 is the circuit diagram of another 3DFO64M16VS1281 chip；
Fig. 6 is the circuit diagram of data storage A；
Fig. 7 is the circuit diagram of checksum memory；
Fig. 8 is FPGA and AT697 processor connection diagrams；
Fig. 9 is the connection diagram of FPGA and data storage B；
Figure 10 is the connection diagram of FPGA and external interface circuit；
Figure 11 is the electric power thus supplied schematic diagram of FPGA；
Figure 12 is the circuit diagram of a piece of 3DSR32M32VS8504 chips；
Figure 13 is the circuit diagram of another 3DSR32M32VS8504 chip；
Figure 14 is the circuit diagram of optical fiber interface；
Figure 15 is the circuit diagram of B65170S6RH；
Figure 16 is the circuit diagram of a piece of B54ACS164245S；
Figure 17 is the circuit diagram of second B54ACS164245S；
Figure 18 is the circuit diagram of third piece B54ACS164245S；
Figure 19 is the circuit diagram of DS90LV031A；
Figure 20 is the circuit diagram of DS90LV032A；
Figure 21 is the circuit diagram of DS26LV31W；
Figure 22 is the circuit diagram of DS26LV32W.
Specific implementation mode
It elaborates below to the embodiment of the present invention, the present embodiment is carried out lower based on the technical solution of the present invention
Implement, gives detailed embodiment and specific operating process, but protection scope of the present invention is not limited to following implementation
Example.
As shown in Figure 1, the present embodiment includes MCU processor 1 and the program storage being electrically connected therewith respectively 2, number
According to memory A3, checksum memory 4 and FPGA controller 5, respectively with FPGA controller 5 be electrically connected optical fiber interface 6,
1553B interfaces 7, LVDS interface 8, RS422 interfaces 9, data storage B10, and to each memory, interface, processor, control
The power module 11 that device processed is powered；
Expansion interface of the FPGA controller 5 as MCU processor 1, the FPGA controller 5 pass through 1553B interfaces 7
The control command and transmission working status parameter for receiving Satellite Management platform give Satellite Management platform, the FPGA controller 5
The pps pulse per second signal of Satellite Management platform, which is received, by RS422 interfaces 9 and transmits the high data of survey gives Satellite Management platform, it is described
For FPGA controller 5 by the transmission of LVDS interface 8 treated echo data gives Satellite Management platform, the FPGA controller 5 is logical
It crosses optical fiber interface 6 and receives raw radar data, row distance of going forward side by side compensation, process of pulse-compression, the data storage B10 is used for
Store the raw radar data from next stage digital transmitting and receiving unit；
Described program memory 2 is used for storage program area, application program and intermediate data, and the data storage A3 is used
Temporary data can lose after the temporary running data of program, power down, and the checksum memory 4 is used to store operation
The check code of error detection and correction EDAC.
The MCU processor 1 of the present embodiment is a piece of AT697F processors, and program storage 2 is two panels
3DFO64M16VS1281 chips, FPGA controller 5 are a piece of XQ5VX100T controllers, and data storage A3 is a piece of
AT68166F chips, checksum memory 4 are a piece of AT60142FT chips, and data storage B10 is two panels
3DSR32M32VS8504 chips.
AT697F processors are the high-performance processor based on 32 SPARC V8 frameworks of radioresistance, Flouride-resistani acid phesphatase accumulated dose
Ability is more than 300Krad (si), and anti-single particle overturns (SEU) and is better than 1E-5 mistakes/device/day, and anti-single particle latch is better than
70MeV/cm2/mg；Chip interior carries the floating-point calculation component of 32-bit/64-bit, five rank pipeline processes, and supports
Error detection and correction (Error Detect And Correct, EDAC) function of internal memory operation, can to 32 position datawires into
Row entangles two dislocations of a dislocation and inspection.Can satellite load etc. have compared with highly anti-radiation requirement and weapon, ground, naval vessel etc. have it is higher can
It is applied in the environment that property requires, circuit diagram is as shown in Figures 2 and 3.
Fig. 2 is the controlling switch of AT697F processor external connections, including address bus ADDR2~ADDR20, data are total
Line DATA0~DATA31 and other controlling switch.Wherein, pin 180 is crystal oscillator input clock signal, clock frequency 60MHz；
Pin 171 is external reset input pin, and low level is effective；Pin 168 is internal WatchDog Timer output signal, is also used for
Processor is resetted.Fig. 3 is the electric power thus supplied of AT697F processors.AT697F processor operating voltages include VCC1 and
Two kinds of VCC2, VCC1 are+3.3V, and VCC2 is+1.8V.
Program storage 2 is used for storage program area, application program and intermediate data, belongs to nonvolatile memory.
3DFO64M16VS1281 chips are a FLASH memories for meeting space product requirement, and capacity is 8M bytes, data line width
For 16bit.The present embodiment is communicated using two panels composition 32bit bit wides with AT697F, and Fig. 4 is a piece of 3DFO64M16VS1281 cores
The circuit diagram of piece, Fig. 5 are the circuit diagram of another 3DFO64M16VS1281.
AT697F processors pass through its address bus ADDR2~ADDR23, data/address bus DATA0~DATA31, FLASH pieces
Control line FLASH_CS0, FLASH write line FLASH_WE, FLASH is selected to read control line FLASH_OE, FLASH state instruction line
BRDYN is connected with a piece of 3DFO64M16VS1281 chips corresponding pin in Fig. 4, and XQ5VX100T controllers are multiple by FLASH
Another in position control line FLASH_RST, FLASH byte control line FLASH1_BYTE, FLASH2_BYTE and Fig. 5
3DFO64M16VS1281 chip corresponding pins are connected, and realize the access of 16M byte programs.
Data storage A3 is used for keeping in the running data of program, and temporary data can lose after power down.
AT68166F chips are the SRAM memories of a Flouride-resistani acid phesphatase, and Flouride-resistani acid phesphatase accumulated dose ability is more than 300krads (Si), anti-simple grain
Sub- latch is better than 80MeV/cm2/mg, can meet the requirement of space flight SRAM.The capacity of monolithic AT68166F chips is 16Mbit,
Data bit width can be configured to 32-bit, 16-bit and 8-bit as needed, and SRAM is configured to 32-bit in the present embodiment,
Circuit diagram is as shown in Figure 6.AT697F processors by its address bus ADDR2~ADDR20, data/address bus DATA0~
DATA31, SRAM write controlling bus SRAM_WE0~SRAM_WE3, SRAM pieces select control line SRAM_CS0, SRAM to read control line
SRAM_OE0 is connected with AT68166F chip corresponding pins, realizes the access of 2M byte datas.
Since SRAM device is easy to be influenced to generate error bit by single particle effect, to ensure the reliability of read-write data,
AT697F processors specially devise the EDAC functions to external memory access, can correct a mistake in 32 words, inspection
Survey two mistakes in 32 words.A piece of 8 checksum memories 4 of exterior arrangement are needed using EDAC functions, for storing EDAC
Check code.AT60142FT memories are 8 SRAM memories of a Flouride-resistani acid phesphatase, and Flouride-resistani acid phesphatase accumulated dose ability is more than
300krads (Si), anti-single particle latch are better than 80MeV/cm2/mg, can meet the requirement of space flight SRAM, circuit diagram
As shown in Figure 7.AT697F processors by its address bus ADDR2~ADDR20, data/address bus CBDATA0~CBDATA7,
SRAM write control line SRAM_WE0, SRAM piece selects control line SRAM_CS0, SRAM to read control line SRAM_OE0 and AT60142FT core
Piece corresponding pin is connected, and realizes the access of 512K byte verification datas.
Since AT697F processor universaling I/O ports only have 16, far from the design requirement for meeting spaceborne task management plate.
Simultaneously to meet software radio versatility, scalability design requirement, the present embodiment selects the control of Virtex-5 Series FPGAs
Expansion interface of the device 5XQ5VX100T controllers as AT697F processors, while the distance for being responsible for completing raw radar data is mended
Repay, pulse compression etc. processing.XQ5VX100T controllers possess 8208Kb Block RAM Blocks, 16 RocketIO GTX
Transceiver has 20 I/O Bank, maximum 680 I/O resources, each Bank that can be separately configured as LVTTL, LVCMOS, LVDS
Equal voltage modes.Abundant 36Kb dual port RAM modules resource can be programmed for the various depths from 32K × 1 to 512 × 72 in piece
Degree and width configuration.In addition, each 36Kb modules may also be configured to two independent 18Kb dual port RAM modules operations.Each
Port is all fully synchronized and independent, provides three kinds of read-while-write patterns.Block RAM can be cascaded, large-scale embedded to realize
Memory module brings great convenience for designs such as digital signal data buffering and asynchronous read and writes.RocketIO GTX transceiver energy
The enough speed with 100Mb/s to 3.75Gb/s is run, and is supported complete clock and data recovery function, is supported 8/16 or 10/20
Bit data path, optional 8B/10B or coding/decoding function based on FPGA support channel binding and clock correction, are embedded
32 CRC generations/inspections, programmable preemphasis, programmable transmitter output voltage swing, programmable receivers are balanced, programmable connect
Receive device terminal, built-in PRBS generator/checker.RocketIO GTX transceivers be used for complete optical-fibre channel data coding,
Functions, the circuit diagrams such as conversion include shown in Fig. 8~11.
AT697F processors pass through its address bus ADDR0~ADDR27, data/address bus DATA0~DATA31, SRAM write
Controlling bus SRAM_WE0~SRAM_WE3, SRAM pieces select controlling bus SRAM_CS0~SRAM_CS4, SRAM to read controlling bus
SRAM_OE0~SRAM_OE3, control line PIO3_MCU_FPGA, control line PIO4_MCU_FPGA, control line PIO5_MCU_
FPGA, control line PIO6_MCU_FPGA, DONE signal wire, PROGRAM signal wires, V4RST signal wires and XQ5VX100T are controlled
Device corresponding pin is connected, and realizes communication and control with XQ5VX100T controllers.
Data storage B10 is for storing the raw radar data from digital transmitting and receiving unit.3DSR32M32VS8504 cores
Piece is a large capacity Flouride-resistani acid phesphatase SRAM memory, and Flouride-resistani acid phesphatase accumulated dose ability is more than 100krads (Si), anti-single particle latch
Better than 110MeV/cm2/mg, the requirement of space flight SRAM can be met.Monolithic 3DSR32M32VS8504 capacity is 32Mbit, data
Bit wide is 32-bit, and Figure 12 is the circuit diagram of a piece of 3DSR32M32VS8504 chips, and Figure 13 is another
The circuit diagram of 3DSR32M32VS8504 chips.XQ5VX100T controllers by its address bus SRAM_ADDR_A0~
SRAM_ADDR_A16, data/address bus SRAM_DATA_A0~SRAM_DATA_A31, SRAM pieces select controlling bus SRAM_CS_N_
A0~SRAM_CS_N_A7, control line SRAM_OE_N_A, write line SRAM_WE_N_A and SRAM_HA0_A, SRAM_ are read
LA0_A, SRAM_LB_N_A, SRAM_UB_N_A signal wire are connected with a piece of 3DSR32M32VS8504 chips corresponding pin, simultaneously
Pass through its address bus SRAM_ADDR_B0~SRAM_ADDR_B16, data/address bus SRAM_DATA_B0~SRAM_DATA_
B31, SRAM piece select controlling bus SRAM_CS_N_B0~SRAM_CS_N_B7, read control line SRAM_OE_N_B, write line
SRAM_WE_N_B and SRAM_HA0_B, SRAM_LA0_B, SRAM_LB_N_B, SRAM_UB_N_B signal wire with another
3DSR32M32VS8504 chip corresponding pins are connected, and realize the access of 8M byte datas.
Optical fiber interface 6 is responsible for receiving raw radar data from digital transmitting and receiving unit.The optical module model double-fiber of use is double
To tail fiber type optical fiber transceiver module HTS8253-FD-S001, transmitting, reception centre wavelength are 850nm, Output optical power
>=-4.5dBm, receiving sensitivity >=-18dBm, traffic rate are up to 4.25Gbps, optical module circuit diagram such as Figure 14 institutes
Show.TD1+, TD1- in TD1+, TD1-, RD1+, RD1-, LOS1, SCL1, SDA1, CON1 and Figure 10, RD1+ in Figure 14,
RD1-, LOS1, SCL1, SDA1, CON1 corresponding pin are connected.
The orders such as the responsible control parameter for receiving Satellite Management platform of 1553B interfaces 7 and transmission working status parameter are defended
Star management platform.1553B interfaces 7 are by 1 B61580RH bus control unit and 3 16 bidirectional bus transceivers
B54ACS164245S is formed.B65170S6RH is responsible for bus A channel 1553A+/1553A-'s or channel B 1553B+/1553B-
The conversion of serial data and parallel data, B54ACS164245S are responsible for the 5V level signals of 1553B buses and the 3.3V electricity of FPGA
Conversion between ordinary mail number.The circuit diagram of B65170S6RH is as shown in figure 15, the circuit theory of 3 B54ACS164245S
Figure is as shown in Figure 16, Figure 17, Figure 18.In address bus fpga_61580_A0~fpga_61580_A15 and Figure 10 in Figure 16
Identical label correspond to be connected, control signal fpga_61580_SELECTn, fpga_61580_STRBDn, fpga_ in Figure 17
61580_MEM/REGn、fpga_61580_RD、fpga_61580_MSTCLRn、fpga_61580_READYDn、fpga_
61580_INTn、fpga_65170_RTAD0、fpga_65170_RTAD1、fpga_65170_RTAD2、fpga_65170_
Identical label is corresponding connected in Figure 10 by RTAD3, fpga_65170_RTAD4, fpga_65170_RTADP, the number in Figure 17
According to bus fpga_61580_D0~fpga_61580_D15, identical label is corresponding connected in Figure 10.Address in Figure 16 is total
Identical label is corresponding connected in Figure 15 by line 61580_A0~61580_A15, the control signal 61580_ in Figure 17
SELECTn、61580_STRBDn、61580_MEM/REGn、61580_RD、61580_MSTCLRn、61580_READYDn、
61580_INTn、61580_RTAD0、61580_RTAD1、61580_RTAD2、61580_RTAD3、61580_RTAD4、61580_
Identical label is corresponding connected in Figure 15 by RTADP, in data/address bus 61580_D0~61580_D15 and Figure 15 in Figure 17
Identical label, which corresponds to, to be connected.61580_CLK is crystal oscillator input clock, clock frequency 16MHz.
LVDS interface 8 is responsible for transmission task management plate treated that echo data gives Satellite Management platform.LVDS interface 8 by
1 lvds driver DS90LV031A and 1 LVDS receiver DS90LV032A composition, LVDS are encoded using 8B/10B, communication
Rate is 100Mbps.Figure 19 is the circuit diagram of DS90LV031A.Figure 20 is the circuit diagram of DS90LV032A.Figure 19
In DATA1, DATA2, DATA3, DATA4 label identical with Figure 10 it is corresponding be connected, BDATA1, BDATA2 in Figure 20,
BDATA3, BDATA4 label identical with Figure 10 are corresponding to be connected.DATA1, DATA2, DATA3, DATA4 are 4 tunnel transmission data lines,
BDATA1, BDATA2, BDATA3, BDATA4 are that 4 tunnels receive data line.The anode and negative terminal of lvds driver differential output signal
Connect respectively 100 Ω resistance, the anode and negative terminal of LVDS receiver differential input signal are connected 1K resistance respectively, for being isolated therefore
Hinder and protects LVDS receiver from the damage of high voltage transient.
RS422 interfaces 9 are responsible for receiving the pps pulse per second signal of Satellite Management platform and transmission is surveyed high data and put down to Satellite Management
Platform.RS422 interfaces 9 are made of 1 RS422 drivers DS26LV31W and 1 RS422 receivers DS26LV32W.Figure 21 is
The circuit diagram of DS26LV31W, Figure 22 are the circuit diagrams of DS26LV32W.RS422-CLK, RS422- in Figure 21
DATA1, RS422-CP label identical with Figure 10 are corresponding to be connected, RS422-DATA2, RS422-RD in Figure 22 and phase in Figure 10
It corresponds to and is connected with label.Wherein, RS422-CLK is synchronised clock line, RS422-DATA1 is transmission data line, and RS422-CP is
Handshake is sent, RS422-DATA2 is to receive data line, and RS422-RD is to receive handshake.RS422 driver difference is defeated
Go out the anode of signal and negative terminal is connected 56 Ω resistance respectively, the anode and negative terminal of RS422 receiver differential input signals are gone here and there respectively
Join 1K resistance, be used for isolated fault and protect RS422 drivers from the damage of high voltage transient.No input pin is all connected
10K resistance is connected to GND, to ensure to export fixed level.
Power module 11 export VCC0 (+5V), VCC1 (+3.3V), VCC2 (+1.8V), VCC3 (+2.5V), VCC4 (+
1.2V), the operating voltage of VCC5 (+1.0V) totally six kinds of voltage values, MCU processor 1 is+3.3V and+1.8V, FPGA controller 5
Operating voltage be+3.3V ,+2.5V ,+1.2V and+1.0V, program storage 2, data storage A3, checksum memory 4, light
Fine interface 6, LVDS interface 8, RS422 interfaces 9, data storage B10 operating voltage be+3.3V, the work of 1553B interfaces 7
It is+5V and+3.3V to make voltage.Wherein ,+5V voltages are generated by high current, low voltage difference LDO chips MSK5230-5.0H ,+3.3V electricity
Pressure is generated by high current, low voltage difference LDO chips MSK5232-3.3HG, and+1.8V voltages are by high current, low voltage difference LDO chips
MSK5232-1.8H is generated, and+2.5V voltages are generated by high current, low voltage difference LDO chips MSK5232-2.5HG ,+1.2V voltages by
High current, low voltage difference LDO chips MSK5251-1.2H are generated, and+1.0V voltages are by high current, low voltage difference LDO chips MSK5251-
1.0H generating.
In the present embodiment, the storage of program storage 2, data storage A3, checksum memory 4, data storage B10
Capacity, optical fiber interface 6,1553B interfaces 7, LVDS interface 8, RS422 interfaces 9 quantity can be expanded according to actual needs
Exhibition or backup, to meet the design needs of different function radar.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement etc., should all be included in the protection scope of the present invention made by within refreshing and principle.
Claims (10)
1. a kind of Embedded Multi-task managing device, which is characterized in that be electrically connected therewith including MCU processor and respectively
Program storage, data storage A, checksum memory and FPGA controller, the optical fiber being electrically connected respectively with FPGA controller
Interface, 1553B interfaces, LVDS interface, RS422 interfaces, data storage B, and to each memory, interface, processor, control
The power module that device processed is powered；
Expansion interface of the FPGA controller as MCU processor, the FPGA controller pass through 1553B interface satellites
The control command and transmission working status parameter of management platform give Satellite Management platform, the FPGA controller to pass through RS422
The pps pulse per second signal of interface Satellite Management platform simultaneously transmits and surveys high data and give Satellite Management platform, the FPGA controller logical
Cross LVDS interface transmission treated echo data gives Satellite Management platform, the FPGA controller pass through optical fiber interface receive it is former
Beginning echo data, row distance of going forward side by side compensation, process of pulse-compression, the data storage B is for storing from next stage number
The raw radar data of Transmit-Receive Unit；
Described program memory is used for storage program area, application program and intermediate data, and the data storage A is for keeping in
The running data of program, temporary data can lose after power down, and the checksum memory is used to store the mistake inspection of operation
Survey and correct the check code of EDAC.
2. a kind of Embedded Multi-task managing device according to claim 1, which is characterized in that the MCU processor is
A piece of AT697F processors, program storage are two panels 3DFO64M16VS1281 chips, and FPGA controller is a piece of
XQ5VX100T controllers, data storage A are a piece of AT68166F chips, and checksum memory is a piece of AT60142FT chips,
Data storage B is two panels 3DSR32M32VS8504 chips.
3. a kind of Embedded Multi-task managing device according to claim 2, which is characterized in that the AT697F processors
By address bus ADDR2~ADDR23, data/address bus DATA0~DATA31, FLASH pieces select control line FLASH_CS0,
FLASH write lines FLASH_WE, FLASH read control line FLASH_OE, FLASH state instruction line BRDYN with
The corresponding pin of 3DFO64M16VS1281 chips is connected, and XQ5VX100T controllers reset control line FLASH_ by FLASH
RST, FLASH byte control line FLASH1_BYTE, FLASH2_BYTE are connected with 3DFO64M16VS1281 chip corresponding pins,
Realize the access of 16M byte programs.
4. a kind of Embedded Multi-task managing device according to claim 2, which is characterized in that the AT697F processors
Pass through address bus ADDR2~ADDR20, data/address bus DATA0~DATA31, SRAM write controlling bus SRAM_WE0~SRAM_
WE3, SRAM piece select control line SRAM_CS0, SRAM reading control line SRAM_OE0 to be connected with the corresponding pin of AT68166F chips,
Realize the access of 2M byte datas.
5. a kind of Embedded Multi-task managing device according to claim 2, which is characterized in that the AT697F processors
Pass through address bus ADDR2~ADDR20, data/address bus CBDATA0~CBDATA7, SRAM write control line SRAM_WE0, SRAM
Piece selects control line SRAM_CS0, SRAM reading control line SRAM_OE0 to be connected with the corresponding pin of AT60142FT chips, realizes
The access of 512K byte verification datas.
6. a kind of Embedded Multi-task managing device according to claim 2, which is characterized in that the AT697F processors
Pass through address bus ADDR0~ADDR27, data/address bus DATA0~DATA31, SRAM write controlling bus SRAM_WE0~SRAM_
WE3, SRAM piece select controlling bus SRAM_CS0~SRAM_CS4, SRAM to read controlling bus SRAM_OE0~SRAM_OE3, control
Line PIO3_MCU_FPGA, control line PIO4_MCU_FPGA, control line PIO5_MCU_FPGA, control line PIO6_MCU_FPGA,
DONE signal wires, PROGRAM signal wires, V4RST signal wires are connected with the corresponding pin of XQ5VX100T controllers, realize with
The communication and control of XQ5VX100T controllers.
7. a kind of Embedded Multi-task managing device according to claim 2, which is characterized in that the XQ5VX100T controls
Device processed passes through address bus SRAM_ADDR_A0~SRAM_ADDR_A16, data/address bus SRAM_DATA_A0~SRAM_DATA_
A31, SRAM piece select controlling bus SRAM_CS_N_A0~SRAM_CS_N_A7, read control line SRAM_OE_N_A, write line
SRAM_WE_N_A and SRAM_HA0_A, SRAM_LA0_A, SRAM_LB_N_A, SRAM_UB_N_A signal wire with it is a piece of
The corresponding pin of 3DSR32M32VS8504 chips is connected, while passing through address bus SRAM_ADDR_B0~SRAM_ADDR_
B16, data/address bus SRAM_DATA_B0~SRAM_DATA_B31, SRAM pieces select controlling bus SRAM_CS_N_B0~SRAM_
CS_N_B7, read control line SRAM_OE_N_B, write line SRAM_WE_N_B and SRAM_HA0_B, SRAM_LA0_B,
SRAM_LB_N_B, SRAM_UB_N_B signal wire are connected with the corresponding pin of another 3DSR32M32VS8504 chip, realize
The access of 8M byte datas.
8. a kind of Embedded Multi-task managing device according to claim 2, which is characterized in that the optical fiber interface uses
The two-way tail fiber type optical fiber transceiver module HTS8253-FD-S001 of optical module model double-fiber, traffic rate is up to
4.25Gbps。
9. a kind of Embedded Multi-task managing device according to claim 2, which is characterized in that the 1553B interfaces packet
Include 16 bidirectional bus transceiver B54ACS164245S of a piece of B65170S6RH bus control units and three pieces, the LVDS interface
Including a piece of lvds driver DS90LV031A and a piece of LVDS receiver DS90LV032A, the RS422 interfaces include a piece of
RS422 drivers DS26LV31W and a piece of RS422 receivers DS26LV32W.
10. a kind of Embedded Multi-task managing device according to claim 2, which is characterized in that the power module is defeated
Go out+5V ,+3.3V ,+2.5V ,+1.8V ,+1.2V and+1.0V totally six kinds of voltage values, wherein the operating voltage of MCU processor be+
The operating voltage of 3.3V and+1.8V, FPGA controller are+3.3V ,+2.5V ,+1.2V and+1.0V, and program storage, data are deposited
Reservoir A, checksum memory, optical fiber interface, LVDS interface, RS422 interfaces, data storage B operating voltage be+3.3V,
The operating voltage of 1553B interfaces is+5V and+3.3V.
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