CN108769694B - Method and device for Alpha channel coding based on FPGA - Google Patents
Method and device for Alpha channel coding based on FPGA Download PDFInfo
- Publication number
- CN108769694B CN108769694B CN201810550868.7A CN201810550868A CN108769694B CN 108769694 B CN108769694 B CN 108769694B CN 201810550868 A CN201810550868 A CN 201810550868A CN 108769694 B CN108769694 B CN 108769694B
- Authority
- CN
- China
- Prior art keywords
- coding
- result
- alpha channel
- rle
- huffman
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 44
- 238000012545 processing Methods 0.000 claims abstract description 77
- 238000007906 compression Methods 0.000 claims description 40
- 230000006835 compression Effects 0.000 claims description 40
- 238000004590 computer program Methods 0.000 claims description 7
- 230000008569 process Effects 0.000 abstract description 15
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000004422 calculation algorithm Methods 0.000 description 6
- 238000004364 calculation method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000001133 acceleration Effects 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000013144 data compression Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002085 persistent effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 238000002054 transplantation Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/20—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video object coding
- H04N19/21—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video object coding with binary alpha-plane coding for video objects, e.g. context-based arithmetic encoding [CAE]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The application discloses an Alpha channel coding method based on an FPGA, which comprises the following steps: sending the received Alpha channel data to an RLE coding kernel program in an FPGA board card; processing Alpha channel data to obtain a processing result; sending the RLE coding result and the processing result to a Huffman coding kernel program in the FPGA board card; and generating a WebP file according to the Huffman coding result. According to the method, the RLE coding module and the Huffman coding module are transplanted to the FPGA board card, so that the RLE coding process and the Huffman coding process of Alpha channel data are accelerated in parallel, and the Alpha channel coding speed is increased. The application also provides a device and equipment for Alpha channel coding based on the FPGA and a computer readable storage medium, and the device and equipment have the beneficial effects.
Description
Technical Field
The present application relates to the field of WebP image compression coding, and in particular, to a method, an apparatus, a device, and a computer-readable storage medium for Alpha channel coding based on an FPGA.
Background
WebP is a new image format developed by Google and has been supported by Chrome, Opera, and Android, making Web pages faster by making images smaller. WebP has the advantages that the WebP has a better image data compression algorithm, can bring smaller picture volume, has the image quality which is identified by naked eyes without difference, has lossless and lossy compression modes, Alpha transparency and animation characteristics, and has quite excellent, stable and uniform conversion effects on JPEG and PNG.
ARGB is a color model, namely RGB color model with Alpha (transparency) channel attached, and is commonly used in 32-bit bitmap memory structure. PNG is an image format using RGBA, and in the PNG to WebP image compression technology, in addition to lossy WebP (RGB colors) and lossless WebP (lossless RGB supporting Alpha), there is another WebP mode that allows both lossy coding using RGB channels and lossless coding using Alpha channels to be called: alpha is supported for lossy WebP, which is not available with any other existing image format.
Currently, a website administrator needing transparency must encode an image into a lossless PNG format, so that the size of the image becomes large; WebP Alpha encodes the low bit of each pixel of an image, and the size of the image can be effectively reduced. Compared with lossy WebP coding (quality 90), lossless compression using the Alpha channel only increases 22% bytes, saving on average 60-70% of file size. This has become an important feature to attract mobile stations with rich icon resources.
However, in the process of performing WebP lossless compression on Alpha data, each Alpha data of the traversal image needs to be subjected to lossless compression coding and written into the WebP image file, which increases the calculation amount of the WebP image compression coding, so that the speed of the WebP image compression coding is slow, which is also a bottleneck of the calculation performance of the WebP lossless compression.
Therefore, how to increase the speed of Alpha channel WebP image compression encoding is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The application aims to provide a method, a device and equipment for Alpha channel coding based on an FPGA (field programmable gate array) and a computer readable storage medium, which are used for improving the speed of the WebP image compression coding of the Alpha channel.
In order to solve the above technical problem, the present application provides a method for Alpha channel coding based on an FPGA, including:
sending the received Alpha channel data to an RLE coding kernel program in an FPGA board card, so that the RLE coding kernel program performs RLE coding on the Alpha channel data to obtain an RLE coding result;
processing the Alpha channel data to obtain a processing result; wherein the processing operations include frequency statistics and frequency compression;
sending the RLE coding result and the processing result to a Huffman coding kernel program in the FPGA board card so that the Huffman coding kernel program carries out Huffman coding on the processing result and the RLE coding result to obtain a Huffman coding result;
and reading the Huffman coding result, and generating a WebP file according to the Huffman coding result.
Optionally, the processing operation performed on the Alpha channel data to obtain a processing result includes:
sending the received Alpha channel data to an RLE coding kernel program in an FPGA board card, so that the RLE coding kernel program performs frequency statistics while performing RLE coding on the Alpha channel data to obtain a frequency statistical result;
and performing frequency compression on the frequency statistical result to obtain the processing result.
Optionally, performing frequency compression on the frequency statistical result to obtain the processing result, including:
creating a first Huffman tree according to the frequency statistical result;
carrying out run-length coding on the first Huffman tree to obtain a run-length coding result;
and creating a second Huffman tree according to the run coding result, and taking the second Huffman tree as the processing result.
The application also provides a device for Alpha channel coding based on FPGA, which comprises:
the first sending module is used for sending the received Alpha channel data to an RLE coding kernel program in the FPGA board card so that the RLE coding kernel program performs RLE coding on the Alpha channel data to obtain an RLE coding result;
the processing module is used for processing the Alpha channel data to obtain a processing result; wherein the processing operations include frequency statistics and frequency compression;
the second sending module is used for sending the RLE coding result and the processing result to a Huffman coding kernel program in the FPGA board card so that the Huffman coding kernel program can carry out Huffman coding on the processing result and the RLE coding result to obtain a Huffman coding result;
and the receiving module is used for reading the Huffman coding result and generating a WebP file according to the Huffman coding result.
Optionally, the processing module includes:
the device comprises a sending unit, a receiving unit and a processing unit, wherein the sending unit is used for sending the received Alpha channel data to an RLE coding kernel program in an FPGA board card so that the RLE coding kernel program carries out frequency statistics while carrying out RLE coding on the Alpha channel data to obtain a frequency statistical result;
and the compression unit is used for carrying out frequency compression on the frequency statistical result to obtain the processing result.
Optionally, the compressing unit includes:
the first creating subunit is used for creating a first Huffman tree according to the frequency statistical result;
the run-length coding subunit is used for carrying out run-length coding on the first Huffman tree to obtain a run-length coding result;
and the second creating subunit is used for creating a second Huffman tree according to the run coding result and taking the second Huffman tree as the processing result.
The present application further provides an FPGA-based Alpha channel encoding device, which includes:
a memory for storing a computer program;
a processor for implementing the steps of the method for FPGA-based Alpha channel coding as described in any one of the above when executing the computer program.
The present application further provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method for FPGA-based Alpha channel coding as described in any of the above.
According to the method for coding the Alpha channel based on the FPGA, the received Alpha channel data are sent to an RLE coding kernel program in an FPGA board card, so that the RLE coding kernel program performs RLE coding on the Alpha channel data to obtain an RLE coding result; processing Alpha channel data to obtain a processing result; wherein the processing operation comprises frequency statistics and frequency compression; sending the RLE coding result and the processing result to a Huffman coding kernel program in the FPGA board card so that the Huffman coding kernel program can carry out Huffman coding on the processing result and the RLE coding result to obtain a Huffman coding result; and reading a Huffman coding result, and generating a WebP file according to the Huffman coding result.
According to the technical scheme provided by the application, the RLE coding module and the Huffman coding module are transplanted to the FPGA board card, so that after the host sends the Alpha channel data to the RLE coding kernel program in the FPGA board card, the RLE coding kernel program can perform RLE coding on the Alpha channel data to obtain an RLE coding result; when the host terminal sends the RLE coding result and the processing result to the Huffman coding kernel program in the FPGA board card, the Huffman coding kernel program performs Huffman coding on the processing result and the RLE coding result to obtain the Huffman coding result, parallel acceleration of the RLE coding process and the Huffman coding process of Alpha channel data is realized, and further the speed of compression coding of the WebP image of the Alpha channel is greatly improved. The application also provides a device, equipment and a computer readable storage medium for Alpha channel coding based on the FPGA, which have the beneficial effects and are not repeated herein.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a method for Alpha channel coding based on an FPGA according to an embodiment of the present disclosure;
FIG. 2 is a function implementation flow of Alpha channel encoding in the prior art;
fig. 3 is a flow chart of function implementation of Alpha channel coding based on FPGA according to an embodiment of the present disclosure;
fig. 4 is a structural diagram of an apparatus for Alpha channel coding based on FPGA according to an embodiment of the present disclosure;
FIG. 5 is a block diagram of another FPGA-based Alpha channel encoding apparatus according to an embodiment of the present disclosure;
fig. 6 is a structural diagram of an Alpha channel encoding device based on an FPGA according to an embodiment of the present disclosure.
Detailed Description
The core of the application is to provide a method, a device and equipment for Alpha channel coding based on FPGA and a computer readable storage medium, which are used for improving the speed of the WebP image compression coding of the Alpha channel.
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a flowchart of an FPGA-based Alpha channel coding method according to an embodiment of the present disclosure.
The method specifically comprises the following steps:
s101: sending the received Alpha channel data to an RLE coding kernel program in an FPGA board card so that the RLE coding kernel program performs RLE coding on the Alpha channel data to obtain an RLE coding result;
based on the prior art that in the process of performing WebP lossless compression on Alpha data, each Alpha data needing to traverse an image is subjected to lossless compression coding and written into a WebP image file, the calculation amount of the WebP image compression coding is increased, and the speed of the WebP image compression coding is slower;
compared with a general processor CPU, the GPU can improve the calculation speed of a calculation intensive program in WebP image compression coding, but the energy efficiency improvement and application range of the GPU are limited by the characteristics of high energy consumption, small cache and the like of the GPU. The FPGA heterogeneous platform has become one of the best solutions for improving the performance of the data center server and reducing the power consumption of the Internet company due to the characteristics of low power consumption, programmability, high parallelism and the like. The FPGA heterogeneous computing platform adopts a high-level comprehensive programming model, researches and optimizes a computationally intensive and complex algorithm based on an OpenCL language, completes efficient transplantation and deployment of the algorithm on the FPGA platform, and can greatly improve the computing performance of the complex algorithm by fully utilizing board card hardware flow design and task level parallelism;
the FPGA is used as a heterogeneous acceleration coprocessor, has the characteristics of good parallelism, low power consumption, customization and the like, not only has good calculation parallelism and access parallelism, but also can realize deep flow parallelism through a deeply customized hardware circuit structure, so that the method adopts the FPGA to carry out heterogeneous acceleration, and realizes the RLE coding step and the Huffman coding step which are time-consuming in algorithm and low in data dependence (suitable for parallel processing) at the FPGA end, thereby obtaining a good performance acceleration effect;
it should be noted that, in the prior art, the encoding of the Alpha channel is usually completed through the flow shown in fig. 2, LZ77 is adopted to encode palette data and image data, and considering that the Alpha data of an image has the characteristic of a larger number of consecutive identical pixels, when the initial Alpha data is compressed, the compression effect of RLE encoding is better than that of LZ77 encoding, and the algorithm principle is simpler than that of LZ77, so in the present application, the initial Alpha data is compressed by RLE encoding, and a palette and palette encoding part is created for LZ77 encoding, and all operations related to the palette after LZ77 encoding are discarded, which has no meaning, and can be directly deleted, thereby achieving the effect of simplifying the overall flow of Alpha channel encoding, and the simplified Alpha channel encoding flow is shown in fig. 3.
S102: processing Alpha channel data to obtain a processing result;
processing operations referred to herein include frequency statistics and frequency compression;
optionally, the processing operation performed on the Alpha channel data to obtain the processing result may be performed in the host;
preferably, because the Alpha channel data needs to be traversed once when RLE encoding is performed on the Alpha channel data in the FPGA board, and the Alpha channel data also needs to be traversed once when frequency statistics is performed on the Alpha channel data, in order to save time for repeatedly traversing the Alpha channel data, the processing operation performed on the Alpha channel data to obtain the processing result may specifically be:
sending the received Alpha channel data to an RLE coding kernel program in an FPGA board card, so that the RLE coding kernel program performs frequency statistics while performing RLE coding on the Alpha channel data to obtain a frequency statistical result;
and performing frequency compression on the frequency statistical result to obtain a processing result.
Optionally, the frequency compression performed on the frequency statistical result to obtain the processing result may specifically be:
creating a first Huffman tree according to the frequency statistical result;
run-length coding is carried out on the first Huffman tree to obtain a run-length coding result;
and creating a second Huffman tree according to the run coding result, and taking the second Huffman tree as a processing result.
The Huffman tree establishing process is relatively complex in logic, small in data volume and not suitable for FPGA (field programmable gate array) to perform parallel processing, so that the task of establishing the Huffman tree is distributed to a host end to be done, a Huffman coding part is done by a Huffman coding kernel program in an FPGA board card, and the speed of Alpha channel WebP (Web Page) image compression coding is further increased.
S103: sending the RLE coding result and the processing result to a Huffman coding kernel program in the FPGA board card so that the Huffman coding kernel program can carry out Huffman coding on the processing result and the RLE coding result to obtain a Huffman coding result;
s104: and reading a Huffman coding result, and generating a WebP file according to the Huffman coding result.
At the moment, the host terminal performs subsequent function processing of the non-Alpha coding part to generate a WebP image file, and the Alpha channel WebP image compression coding process is ended.
Based on the technical scheme, according to the method for Alpha channel coding based on the FPGA, the RLE coding module and the Huffman coding module are transplanted to the FPGA board card, so that after the host sends the Alpha channel data to the RLE coding kernel program in the FPGA board card, the RLE coding kernel program can perform RLE coding on the Alpha channel data to obtain an RLE coding result; when the host terminal sends the RLE coding result and the processing result to the Huffman coding kernel program in the FPGA board card, the Huffman coding kernel program performs Huffman coding on the processing result and the RLE coding result to obtain the Huffman coding result, parallel acceleration of the RLE coding process and the Huffman coding process of Alpha channel data is realized, and further the speed of compression coding of the WebP image of the Alpha channel is greatly improved.
Referring to fig. 4, fig. 4 is a structural diagram of an apparatus for Alpha channel coding based on FPGA according to an embodiment of the present disclosure.
The apparatus may include:
the first sending module 100 is configured to send the received Alpha channel data to an RLE coding kernel program in the FPGA board card, so that the RLE coding kernel program performs RLE coding on the Alpha channel data to obtain an RLE coding result;
the processing module 200 is configured to perform a processing operation on Alpha channel data to obtain a processing result; wherein the processing operation comprises frequency statistics and frequency compression;
the second sending module 300 is configured to send the RLE coding result and the processing result to a Huffman coding kernel program in the FPGA board card, so that the Huffman coding kernel program performs Huffman coding on the processing result and the RLE coding result to obtain a Huffman coding result;
and the receiving module 400 is configured to read the Huffman coding result and generate a WebP file according to the Huffman coding result.
Referring to fig. 5, fig. 5 is a block diagram of another FPGA-based Alpha channel coding apparatus according to an embodiment of the present disclosure.
The processing module 200 may include:
the sending unit is used for sending the received Alpha channel data to an RLE coding kernel program in the FPGA board card so that the RLE coding kernel program carries out frequency statistics while carrying out RLE coding on the Alpha channel data to obtain a frequency statistical result;
and the compression unit is used for carrying out frequency compression on the frequency statistical result to obtain a processing result.
The compression unit may include:
the first creating subunit is used for creating a first Huffman tree according to the frequency statistical result;
the run-length coding subunit is used for carrying out run-length coding on the first Huffman tree to obtain a run-length coding result;
and the second creating subunit is used for creating a second Huffman tree according to the run coding result and taking the second Huffman tree as the processing result.
The above components of the apparatus can be practically applied to the following embodiments:
the first sending module sends the received Alpha channel data to an RLE coding kernel program in the FPGA board card so that the RLE coding kernel program performs RLE coding on the Alpha channel data to obtain an RLE coding result;
the sending unit sends the received Alpha channel data to an RLE coding kernel program in an FPGA board card, so that the RLE coding kernel program carries out frequency statistics while carrying out RLE coding on the Alpha channel data to obtain a frequency statistical result; the first creating subunit creates a first Huffman tree according to the frequency statistical result; the run-length coding subunit performs run-length coding on the first Huffman tree to obtain a run-length coding result; the second creating subunit creates a second Huffman tree according to the run coding result and takes the second Huffman tree as a processing result;
the second sending module sends the RLE coding result and the processing result to a Huffman coding kernel program in the FPGA board card so that the Huffman coding kernel program can carry out Huffman coding on the processing result and the RLE coding result to obtain a Huffman coding result;
and the receiving module reads the Huffman coding result and generates a WebP file according to the Huffman coding result.
Referring to fig. 6, fig. 6 is a structural diagram of an Alpha channel coding device based on an FPGA according to an embodiment of the present application.
FPGA-based Alpha channel encoding apparatus 500 may vary significantly depending on configuration or performance, and may include one or more processors (CPUs) 522 (e.g., one or more processors) and memory 532, one or more storage media 530 (e.g., one or more mass storage devices) storing applications 542 or data 544. Memory 532 and storage media 530 may be, among other things, transient storage or persistent storage. The program stored on the storage medium 530 may include one or more units (not shown), each of which may include a series of instruction operations for the apparatus. Still further, central processor 522 may be configured to communicate with storage medium 530 to execute a series of instruction operations in storage medium 530 on FPGA-based Alpha channel encoding apparatus 500.
The FPGA-based Alpha channel encoding apparatus 500 may also include one or more power supplies 526, one or more wired or wireless network interfaces 550, one or more input-output interfaces 558, and/or one or more operational devices 541, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, etc.
The steps in the method for FPGA-based Alpha channel coding described in fig. 1 are implemented by an FPGA-based Alpha channel coding device based on the structure shown in fig. 6.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described apparatuses, devices and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus, device and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of modules is merely a division of logical functions, and an actual implementation may have another division, for example, a plurality of modules or components may be combined or integrated into another apparatus, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.
Modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
In addition, functional modules in the embodiments of the present application may be integrated into one processing module, or each of the modules may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.
The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a function calling device, or a network device) to execute all or part of the steps of the method of the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The method, the apparatus, the device and the computer readable storage medium for Alpha channel coding based on the FPGA provided in the present application are described in detail above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (6)
1. A method for Alpha channel coding based on FPGA is characterized by comprising the following steps:
sending the received Alpha channel data to an RLE coding kernel program in an FPGA board card, so that the RLE coding kernel program performs RLE coding on the Alpha channel data to obtain an RLE coding result;
processing the Alpha channel data to obtain a processing result;
sending the RLE coding result and the processing result to a Huffman coding kernel program in the FPGA board card so that the Huffman coding kernel program carries out Huffman coding on the processing result and the RLE coding result to obtain a Huffman coding result;
reading the Huffman coding result, and generating a WebP file according to the Huffman coding result;
wherein, processing the Alpha channel data to obtain a processing result comprises:
sending the received Alpha channel data to an RLE coding kernel program in an FPGA board card, so that the RLE coding kernel program performs frequency statistics while performing RLE coding on the Alpha channel data to obtain a frequency statistical result;
and performing frequency compression on the frequency statistical result to obtain the processing result.
2. The method of claim 1, wherein frequency compressing the frequency statistics to obtain the processing result comprises:
creating a first Huffman tree according to the frequency statistical result;
carrying out run-length coding on the first Huffman tree to obtain a run-length coding result;
and creating a second Huffman tree according to the run coding result, and taking the second Huffman tree as the processing result.
3. An apparatus for Alpha channel coding based on FPGA, comprising:
the first sending module is used for sending the received Alpha channel data to an RLE coding kernel program in the FPGA board card so that the RLE coding kernel program performs RLE coding on the Alpha channel data to obtain an RLE coding result;
the processing module is used for processing the Alpha channel data to obtain a processing result;
the second sending module is used for sending the RLE coding result and the processing result to a Huffman coding kernel program in the FPGA board card so that the Huffman coding kernel program can carry out Huffman coding on the processing result and the RLE coding result to obtain a Huffman coding result;
the receiving module is used for reading the Huffman coding result and generating a WebP file according to the Huffman coding result;
wherein the processing module comprises:
a sending unit, configured to send the received Alpha channel data to an RLE coding kernel program in an FPGA board card, so that the RLE coding kernel program performs frequency statistics while performing RLE coding on the Alpha channel data, and obtains a frequency statistical result;
and the compression unit is used for carrying out frequency compression on the frequency statistical result to obtain the processing result.
4. The apparatus of claim 3, wherein the compression unit comprises:
the first creating subunit is used for creating a first Huffman tree according to the frequency statistical result;
the run-length coding subunit is used for carrying out run-length coding on the first Huffman tree to obtain a run-length coding result;
and the second creating subunit is used for creating a second Huffman tree according to the run coding result and taking the second Huffman tree as the processing result.
5. An Alpha channel coding device based on FPGA is characterized by comprising:
a memory for storing a computer program;
processor for implementing the steps of the method for FPGA-based Alpha channel coding according to claim 1 or 2 when executing said computer program.
6. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a processor, carries out the steps of the method of FPGA-based Alpha channel coding according to one of claims 1 or 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810550868.7A CN108769694B (en) | 2018-05-31 | 2018-05-31 | Method and device for Alpha channel coding based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810550868.7A CN108769694B (en) | 2018-05-31 | 2018-05-31 | Method and device for Alpha channel coding based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108769694A CN108769694A (en) | 2018-11-06 |
| CN108769694B true CN108769694B (en) | 2021-11-09 |
Family
ID=64001571
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810550868.7A Active CN108769694B (en) | 2018-05-31 | 2018-05-31 | Method and device for Alpha channel coding based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108769694B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109901884B (en) * | 2019-01-17 | 2022-05-17 | 京微齐力(北京)科技有限公司 | Method and device for high-level synthesis and code stream generation of FPGA |
| CN110062241A (en) * | 2019-05-22 | 2019-07-26 | 苏州浪潮智能科技有限公司 | A kind of compression method, system and the associated component of Alpha channel data |
| CN112135142B (en) * | 2019-06-25 | 2022-06-07 | Oppo广东移动通信有限公司 | Picture decoding method and related product |
| CN110933418B (en) * | 2019-11-26 | 2021-12-21 | 支付宝(杭州)信息技术有限公司 | Video data processing method, device, medium and apparatus |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107124615A (en) * | 2017-05-15 | 2017-09-01 | 郑州云海信息技术有限公司 | A kind of method and device of WebP lossy compression methods |
| CN107154062A (en) * | 2017-05-12 | 2017-09-12 | 郑州云海信息技术有限公司 | A kind of implementation method of WebP Lossy Compression Algorithms, apparatus and system |
| CN107507125A (en) * | 2017-08-31 | 2017-12-22 | 郑州云海信息技术有限公司 | Alpha passage palettes generation method, system and host side in a kind of WebP compression of images |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9245353B2 (en) * | 2012-10-22 | 2016-01-26 | Gurulogic Microsystems Oy | Encoder, decoder and method |
-
2018
- 2018-05-31 CN CN201810550868.7A patent/CN108769694B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107154062A (en) * | 2017-05-12 | 2017-09-12 | 郑州云海信息技术有限公司 | A kind of implementation method of WebP Lossy Compression Algorithms, apparatus and system |
| CN107124615A (en) * | 2017-05-15 | 2017-09-01 | 郑州云海信息技术有限公司 | A kind of method and device of WebP lossy compression methods |
| CN107507125A (en) * | 2017-08-31 | 2017-12-22 | 郑州云海信息技术有限公司 | Alpha passage palettes generation method, system and host side in a kind of WebP compression of images |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108769694A (en) | 2018-11-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108769694B (en) | Method and device for Alpha channel coding based on FPGA | |
| CN108900843B (en) | Monochrome image compression method, apparatus, medium, and electronic device | |
| CN102841901A (en) | Web page display method and device | |
| CN107680144B (en) | WebP file conversion method and device | |
| CN109842803A (en) | A kind of method and device of compression of images | |
| US9966971B2 (en) | Character conversion | |
| US20160124683A1 (en) | In-memory data compression complementary to host data compression | |
| CN107105266A (en) | A kind of coding/decoding method, the apparatus and system of PNG images | |
| CN110728725B (en) | Hardware-friendly real-time system-oriented lossless texture compression method | |
| CN109982085A (en) | A kind of method of high precision image mixing compression | |
| CN110399511A (en) | Image cache method, equipment, storage medium and device based on Redis | |
| JP2018110390A (en) | Method and device for coding and decoding pixel list | |
| CN105096367A (en) | Method and device of optimizing Canvas rendering performance | |
| CN113220651B (en) | Method, device, terminal equipment and storage medium for compressing operation data | |
| CN111243072A (en) | WebVR three-dimensional display method, device and system and readable storage medium | |
| CN112332854A (en) | Hardware implementation method and device of Huffman coding and storage medium | |
| CN108933599B (en) | Huffman coding implementation method, system, equipment and computer storage medium | |
| CN113658281A (en) | Device and method for efficiently processing PNG (portable network graphics) picture | |
| US20200084462A1 (en) | Multi-pixel caching scheme for lossless encoding | |
| CN116405692A (en) | Transmission method based on cloud matting and related equipment | |
| CN203260032U (en) | Webpage resource data real-time loading system | |
| US12041259B2 (en) | Data processing methods and systems, and electronic devices | |
| CN108932315A (en) | A kind of method and relevant apparatus of data decompression | |
| CN114419203A (en) | File processing method and device | |
| CN110545446A (en) | desktop image encoding and decoding methods, related devices and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |