CN108767017A - A kind of semiconductor devices and preparation method - Google Patents
A kind of semiconductor devices and preparation method Download PDFInfo
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- CN108767017A CN108767017A CN201810351145.4A CN201810351145A CN108767017A CN 108767017 A CN108767017 A CN 108767017A CN 201810351145 A CN201810351145 A CN 201810351145A CN 108767017 A CN108767017 A CN 108767017A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
Abstract
A kind of semiconductor devices and preparation method, due to replacing traditional schottky junction anode using the composite anode structure of first anode ohm knot and second plate MIS knots, the rectification characteristic that traditional schottky junction is substituted using the MIS raceway groove modulating properties tied, realizes two parameter index reverse leakage current (I of semiconductor devicesR) and positive cut-in voltage (VoN) promoted simultaneously.Meanwhile in the preparation method of the application, process program used in entire manufacturing process and condition can be realized by the technique of standard Fab, and technical process is simple, the number of windowing when reducing conventional semiconductor devices terminal optimized design.
Description
Technical field
The present invention relates to field of manufacturing semiconductor devices more particularly to a kind of semiconductor devices and preparation methods.
Background technology
Nearly ten years, wide bandgap semiconductor power electronic devices has become one of research emphasis of semiconductor applications.
AIGaN/GaN Schottky-barrier diodes (Schottky Barrier Diode, SBD) have high pressure, high current, powerful
Advantage has irreplaceable role in mesohigh rectification field, especially with the deployment of electric vehicle, high ferro and 5G,
Fast charging and discharging and the demand of power transformation increasingly increase, and the demand of SBD is also growing day by day.Some that 1999 deliver about
In the research paper of GaN base SBD, the basic structure and SiO of the device are elaborated2Influence of the field plate structure to device performance,
And the breakdown reverse voltage for -250~-450V that reported for work, and 10 when -100V-5A/c m2Reverse leakage current, thus pulled open state
The prelude of inside and outside research institution and semiconductor company broad scale research GaN base SBD.
The most crucial parameter for weighing SBD performances is reverse leakage current (IR) and positive cut-in voltage (VoN).It is lower reversed
Electric leakage is to realize the basis of SBD device high voltage, and reduce one of the approach of device power consumption.Smaller cut-in voltage, can be with
So that device is entered the working condition of rectification as early as possible, reduces the power consumption generated when buffering.To reduce reverse leakage current (IR) and promoted
Pressure resistance all uses the technical solutions such as dielectric layer terminal (Termination) and height barrier metal stacking in preparation process.For drop
Low forward direction cut-in voltage (VoN), then the AlGaN potential barrier of Schottky (Schottky) contacts lower section is thinned using etching, to
The Schottky contact berriers of SBD are reduced, realize the purpose for reducing device cut-in voltage.But these methods are all to be promoted
But another parameter index is reduced while one parameter index, cannot achieve the reverse leakage current (I for making SBDR) and it is positive
Cut-in voltage (VoN) two parameter indexes while promoted.
Invention content
The application technical problems to be solved are, can not realize the reverse leakage current for making SBD simultaneously for the prior art
(IR) and positive cut-in voltage (VoN) two parameter indexes while the problem of being promoted, a kind of semiconductor devices and preparation side are provided
Method.
According in a first aspect, provide a kind of semiconductor devices in a kind of embodiment, including：
III-V nitride semiconductor layer, the III-V nitride semiconductor layer include at least substrate, buffer layer, ditch
Channel layer, barrier layer；
The substrate is located at the bottom of the III-V nitride semiconductor layer, and the buffer layer is located on substrate and leads to
The channel layer is crossed with the barrier layer to be isolated；
Passivation layer and dielectric layer；
The dielectric layer is kept apart with the barrier layer by the passivation layer；
First anode electrode is ohm junction structure, is configured on the barrier layer with Ohmic contact by ohmic metal；
Second plate electrode is electrically connected with the first anode electrode；The second plate electrode is MIS junction structures,
The MIS junction structures are configured by anode metal on the dielectric layer, and by the dielectric layer be isolated the anode metal with
The barrier layer is constituted；
Cathode electrode is ohm junction structure, is configured on the barrier layer with Ohmic contact by the ohmic metal, with
The second plate electrode and the first anode electrode are connectionless.
Further, the dielectric layer bottom of the MIS knots is located at from a certain position on the barrier layer or inside barrier layer；
Further, the anode metal is made of TiN, Ni, Au, W, at least one of materials such as Pt or Pd；
The passivation layer is by SiNx、SiO2、SiON、Al2O3Or at least one of materials such as AlN are constituted；
The barrier layer is by AlxGa1-xN,InxGa1-xN,InxAl1-xN, or InxAlyGa1-x-yAt least one in the materials such as N
Kind is constituted.
The dielectric layer is by SiO2, SiNx、Al2O3、AlN、HfO2、MgO、Sc2O3、Ga2O3、AlHfOxOr HfSiON materials
At least one of constitute.
Further, the semiconductor devices further includes protective layer, is formed on the outside of the semiconductor devices, for sealing
The semiconductor devices, the protective layer are made of at least one of the compound of silicon or polyimides.
Further, the semiconductor devices further includes Two-dimensional electron gas-bearing formation, is formed in the channel layer and the barrier layer
Contact surface be biased to channel layer side.
Further, the AlN that 0.7nm~2nm thickness can be inserted between the barrier layer and the channel layer, for promoting ditch
The mobility of electronics in road.
According to second aspect, a kind of preparation method of semiconductor devices is provided in a kind of embodiment, including：
It is sequentially prepared buffer layer, channel layer, barrier layer and cap layers, and the deposit passivation layer in the cap layers on substrate；
First window is opened on the passivation layer, the bottom of the first window is located on the barrier layer or barrier layer
It is internal；
The preparation media layer on the passivation layer and the first window；
Thus the deposition anode metal layer on the dielectric layer forms in first window and the anode is isolated by dielectric layer
Metal layer and the barrier layer and the MIS junction structures constituted, i.e., the second plate electrode of the described semiconductor devices；
The second window and third window are opened in the anode metal layer；The bottom of second window and the third window
Portion is located on the barrier layer, inside barrier layer or three kinds of barrier layer bottom situation any one；
Deposit ohmic metal contacts in second window and the third window, and ohm is formed by the ohmic metal
Contact configuration is on the barrier layer, respectively as the first anode electrode and cathode electrode of the semiconductor devices, and by institute
The first anode electrode and the second plate electrode for stating semiconductor devices are electrically connected collectively as the semiconductor
The anode electrode of device.
Further, the method further includes preparing protective layer in the outer surface of the semiconductor devices.
Further, the ohmic metal is passed through by metals such as Ti/Al/Ti/TiN, Ti/Al/Ni/Au or Ti/Al/Mo/Au
Stacking is constituted.
According to a kind of semiconductor devices and preparation method of above-described embodiment, due to the channel modulation characteristic using MIS knots
Instead of the rectification characteristic of traditional schottky junction, to, instead of the electric leakage of schottky junction, be tied with MIS with the electric leakage of MIS knots
Unlatching instead of schottky junction unlatching.Because MIS structure has preferable raceway groove ability of regulation and control, may be implemented extremely low reversed
Electric leakage；The cut-in voltage of MIS knots can accurately be regulated and controled by the thickness of barrier layer simultaneously.In this way, ensureing the semiconductor
While device is had compared with Low dark curient, also there is smaller cut-in voltage.
Meanwhile in the preparation method of the application, technique and condition can pass through standard used in entire manufacturing process
The technique of Fab is realized, and technical process is simple, when avoiding semiconductor devices optimization design the step of multiple windowing.
Description of the drawings
Fig. 1 is the cross-section structure signal of Schottky-barrier diode (SBD) in the prior art；
Fig. 2 is the cross-sectional view of an embodiment of the present invention semiconductor devices；
Fig. 3 is the flow chart of an embodiment of the present invention semiconductor devices preparation method；
Fig. 4 (a)~(i) sequentially shows the main technique step of semiconductor devices preparation method preferred embodiment of the present invention
Suddenly, wherein：
(a) it is the processing step schematic diagram of grown buffer layer, channel layer, barrier layer and cap layers successively on substrate；
(b) in the processing step schematic diagram of cap layers surface deposit passivation layer；
(c) it is the processing step schematic diagram for opening first window on the passivation layer；
(d) it is the processing step schematic diagram of the metallization medium layer on passivation layer and first window；
(e) it is the processing step schematic diagram of the deposition anode metal layer on dielectric layer；
(f) it is the processing step schematic diagram that the second window and third window are opened in anode metal layer surface；
(g) it is the processing step schematic diagram of the deposit ohmic metal layer in anode metal layer and the second window, third window；
(h) it is electrode patterning processing step schematic diagram；
(i) it is the processing step schematic diagram for preparing protective layer；
Fig. 5 is the cross-sectional view of another embodiment semiconductor devices of the present invention.
Specific implementation mode
Below by specific implementation mode combination attached drawing, invention is further described in detail.Wherein different embodiments
Middle similar component uses associated similar element numbers.In the following embodiments, many datail descriptions be in order to
The application is better understood.However, those skilled in the art can be without lifting an eyebrow recognize, which part feature
It is dispensed, or can be substituted by other elements, material, method in varied situations.In some cases, this Shen
Please it is relevant some operation there is no in the description show or describe, this is the core in order to avoid the application by mistake
More descriptions are flooded, and to those skilled in the art, these relevant operations, which are described in detail, not to be necessary, they
It can completely understand relevant operation according to the general technology knowledge of description and this field in specification.
It is formed respectively in addition, feature described in this description, operation or feature can combine in any suitable way
Kind embodiment.Meanwhile each step in method description or action can also can be aobvious and easy according to those skilled in the art institute
The mode carry out sequence exchange or adjustment seen.Therefore, the various sequences in the description and the appended drawings are intended merely to clearly describe a certain
A embodiment is not meant to be necessary sequence, and wherein some sequentially must comply with unless otherwise indicated.
It is herein component institute serialization number itself, such as " first ", " second " etc., is only used for distinguishing described object,
Without any sequence or art-recognized meanings.And " connection ", " connection " described in the application, unless otherwise instructed, include directly and
It is indirectly connected with (connection).
Schottky is tied：Schottky junction is a kind of interface of simple metal and semiconductor, similar to PN junction, is had
Rectification characteristic.
Ohm knot：That is Ohmic contact, a kind of interface of simple metal and semiconductor are that abutment does not generate significantly
Additional impedance and it will not make equilibrium carrier concentration inside semiconductor that significant change occur.
MIS is tied：Contact structures (the Metal-insulator-semiconductor of metal-insulator semiconductor
Junction), contacted by insulator between metal and semiconductor.
Composite anode：The metal of semiconductor devices anode and the interface of semiconductor are connect using two or more mode
It touches.
PVD：Full name Physical Vapor Deposition, physical vapour deposition (PVD) are most common in semiconductor technology
The mode of metal deposit.
LPCVD：Full name Low Pressure Chemical Vapor Deposition, low-pressure chemical vapor deposition are
One of the major way that high quality dielectric film deposits in semiconductor technology.
MOCVD：Full name Metal-organic Chemical Vapor Deposition, metallo-organic compound chemistry
Gaseous phase deposition, a kind of novel vapour phase epitaxy growing technology to grow up on the basis of vapor phase epitaxial growth (VPE) are main to use
In the growth of the compound semiconductors such as GaN/SiC.
PEVCD：Full name Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical
Vapor deposition is one of the major way that high quality dielectric film deposits in semiconductor technology, is mainly used for last part technology sheath
Deposition.
RIE：Full name is Reactive Ion Etching, reactive ion etching, a kind of microelectronics dry corrosion process.
IPC：Full name Inductively Coupled Plasma, plasma inductive coupling, a kind of microelectronics dry method are rotten
Etching technique.
Yellow light：The chips such as silicon chip are subjected to gluing, soft roars of laughter, exposure, development, hard baking, it is made to make certain figure by lithography, it is this
Technique is yellow light.
Referring to FIG. 1, for the cross-section structure signal of Schottky-barrier diode (SBD) in the prior art.Including giving birth to successively
Buffer layer 102, channel layer 103, barrier layer 105, cap layers 106, passivation layer 107, dielectric layer 108, the anode being longer than on substrate 101
Metal layer 109 and anode A11, cathode C11.The anode of SBD is anode A11, in anode A11The anode metal 109 and barrier layer of lower section
105 contact surface is traditional schottky junction (Schottky) 112.Wherein, the cathode of SBD is cathode C11。
In embodiments of the present invention, traditional Schottky inactivity of yang-qi is replaced by using ohm knot and the MIS composite construction tied
Pole changes the conducting principle of semiconductor devices from structural nature, realizes two parameter reverse leakage current (I of semiconductorR) and
Positive cut-in voltage (VoN) while promoting index.
Embodiment one：
Referring to FIG. 2, the cross-section structure signal of the semiconductor devices provided for the present embodiment, specifically include sequentially generate in
Buffer layer 202, channel layer 203, barrier layer 205, cap layers 206, passivation layer 207, dielectric layer 208, anode metal on substrate 201
209 and protective layer 210.
Wherein, the anode of semiconductor devices includes first anode A21With second plate A22, the cathode of semiconductor devices is the moon
Pole C21。
It is prepared specifically, the common substrate material such as GaN, SiC or Si can be used in substrate 201, thickness is according to practical need
It sets.Buffer layer 202 can be used the combination of the one or more of which such as superlattices, AlN and AlGaN and constitute.Channel layer 203 can be adopted
It is that material is constituted with GaN, thickness is 3~5 μm.Al can be used in barrier layer 205xGa1-xN,InxGa1-xN,InxAl1-xN, and
InxAlyGa1-x-yAt least one of materials such as N constitute (general 0.15<x<0.3,x+y<0.3), preferably Al0.25Ga0.75N、
In0.2Ga0.8N, AlN or In0.2Al0.8At least one of materials such as N are constituted, and thickness can 10~30nm.In 203 He of channel layer
The contact surface of barrier layer 205 is biased to 203 side of channel layer and is formed with two-dimensional electron gas 204 (2DEG), to promote the migration of 2DEG
Rate can be inserted AlN layers between channel layer 203 and barrier layer 205, and thickness may be configured as 0.7~2nm.Cap layers 206 are located at
Between passivation layer 207 and barrier layer 205, the materials such as SiN, AlN or GaN composition can be used.The effect of passivation layer 207 is to protect
The material interface of semiconductor devices deposition is not oxidized or destroys, and SiN can be usedx、SiO2、SiON、Al2O3Or in AlN materials
Any or arbitrary several combinations are constituted.SiO can be used in the material of dielectric layer 2082、SiNx、Al2O3、AlN、HfO2、MgO、
Sc2O3、Ga2O3、AlHfOxWith any one of materials such as HfSiON or arbitrary several combinations compositions.
Wherein, first anode A21It is to be made of on barrier layer 205 with Ohmic contact configuration ohmic metal 211, and with the
Two anode As22Electrical connection.Second plate A22The MIS that anode metal 209 and barrier layer 205 are formed then is isolated by dielectric layer 208
Junction structure is constituted.Cathode C21It is to be configured on barrier layer 205 with Ohmic contact by ohmic metal 211.Ohmic metal 211 is by Ti/
The metals such as Al/Ti/TiN, Ti/Al/Ni/Au or Ti/Al/Mo/Au are constituted by stacking.Anode metal 209 by TiN, Ni,
At least one of materials such as Au, W, Pt and Pd are constituted；
Further, further include that protective layer 210 is used to protect semiconductor devices, SiO2, SiN can be used in materialx
Or one kind in the materials such as Polyimide (polyimides) or arbitrary several combination are constituted.
The anode of semiconductor devices in the application is due to using first anode A21With second plate A22Composite anode knot
Structure replaces traditional schottky junction anode, utilizes second plate A22The raceway groove modulating properties of MIS junction structures, instead of traditional Xiao Te
The rectification characteristic of base junction.The raceway groove modulating properties of specific MIS junction structures refer to, when this diode forward biases, cathode C21It connects
Touch low potential or zero potential, first anode A21With second plate A22The increase voltage since 0 is connect, if first anode A at this time21
With second plate A22Voltage be less than the potential barriers of MIS junction structures, channel layer 203 is in by state, and entire diode does not have at this time
There is unlatching；If first anode A21With second plate A22Increase to the potential barrier more than MIS junction structures, 203 channel of channel layer is beaten
It opens, the anode (Anode) of diode and cathode (Cathode) are equivalent to Ohmic contact at this time, and electric current can sharply increase at this time,
The limit until reaching 203 ducting capacity of channel layer；When this diode reverse biased, cathode C21High potential, first anode A21
With second plate A22Zero potential or low potential are connect, MIS knots are in by state at this time, and 203 raceway groove of channel layer is not turned on, and device is not
Work；Because MIS structure has preferable raceway groove ability of regulation and control, extremely low reverse leakage may be implemented；The unlatching electricity of MIS knots simultaneously
Pressure can accurately be regulated and controled by the thickness of barrier layer.Therefore, from the analysis above, we can see that, the semiconductor devices based on this structure can
To realize positive rectification, reversely by working characteristics, promote reverse leakage current (I at the same timeR) and positive cut-in voltage (VoN)
While parameter index, the characteristic of SBD is also fully met.It is described by process above, it can be seen that the application proposes new
Type semiconductor design scheme solves the contradiction between semiconductor cut-in voltage and reverse leakage current optimization, comprehensively well
The overall performance for improving semiconductor.
Embodiment two：
Description based on above-described embodiment, the present invention give the preparation method of above-mentioned semiconductor device, such as Fig. 3 institutes
Show, includes the following steps：
S101, it is sequentially prepared buffer layer, channel layer, barrier layer and cap layers, and the deposit passivation layer in cap layers on substrate；
S102, first window is opened on the passivation layer, the bottom of the first window is located on barrier layer or the inside of barrier layer.
S103, the preparation media layer on passivation layer and first window.
S104, the deposition anode metal layer on dielectric layer.It is formed in first window as a result, by dielectric layer isolation anode gold
The MIS junction structures for belonging to layer and barrier layer and constituting, i.e. the second plate electrode of semiconductor devices.Wherein, anode metal can be by
At least one of materials such as TiN, Ni, Au, W, Pt or Pd are constituted；
S105, the second window and third window are opened in anode metal layer, the bottom of the second window and third window can
On barrier layer, inside barrier layer or barrier layer bottom.
S106, the deposit ohmic metal in anode metal layer surface and the second window and third window
After S107, metal patternization, high temperature alloy is carried out, to form good ohm in the second window and third window
Contact, respectively as the first anode electrode and cathode electrode of semiconductor devices, and by the first anode electrode of semiconductor devices
It is electrically connected with second plate electrode.Ohmic metal can be Ti/Al/Ti/TiN, Ti/Al/Mo/Au or Ti/Al/Ni/Au
Etc. common metal stack；
Further, it may additionally include the outside deposition protective layer of semiconductor devices.
By the above process, the composite anode semiconductor devices including the first anode and second plate is prepared, it can also root
According to need carry out multilayer wiring.This application involves manufacturing process used in process program and condition can pass through standard Fab
Technique realize that and technical process is simple, it is non-when avoiding the terminal optimized design of conventional semiconductors the step of multiple windowing
Often it is suitble to the exploitation of inexpensive volume production and high volume applications.
Based on the above method, the application gives the specific preparation process of above-mentioned semiconductor device, as shown in figure 4, packet
Include following steps：
S101, it is sequentially prepared buffer layer, channel layer, barrier layer and cap layers, and the deposit passivation layer in cap layers on substrate；
As shown in Fig. 4 (a), using MOCVD techniques on substrate 301 successively grown buffer layer 302, channel layer 303, two dimension
Electron gas 304, barrier layer 305 and cap layers 306.
Wherein, two-dimensional electron gas 304 (2DEG) is formed in 303 side of channel layer.Substrate 301 may be used in the present embodiment
The materials such as GaN, SiC or Si are constituted, and thickness can be selected according to specific needs.Superlattices, AlN or change may be used in buffer layer 302
One kind and multiple combinations in the materials such as the AlGaN of component are constituted, and thickness may be configured as between 3~5 μm.Barrier layer 305
Al may be usedxGa1-xN,InxGa1-xN,InxAl1-xN, and InxAlyGa1-x-yThe materials such as N are constituted, and thickness may be configured as 10~
Between 30nm.Two-dimensional electron gas 304 is to be biased to 303 side of channel layer in the contact surface of channel layer 303 and barrier layer 305 to be formed,
To promote the mobility of 2DEG, AlN layers can be inserted between channel layer 303 and barrier layer 305, thickness may be configured as 1nm.
SiN may be used in cap layers 306x, the materials such as AlN or GaN constitute, thickness may be configured as between 2~5nm.
As shown in Fig. 4 (b), can by the techniques such as PECVD, LPCVD or ALD cap layers 306 surface deposit passivation layer
307, SiN may be used in passivation layer 307x、SiO2、SiON、Al2O3Or one kind in the materials such as AlN or arbitrary several combination structures
At.Passivation layer 307 can be passivated and protection materials surface.
S102, first window is opened on the passivation layer, the bottom of the first window is located on barrier layer or the inside of barrier layer.
As shown in Fig. 4 (c), then by yellow light define MIS tie institution regional, by dry etching, wet etching or in which
Technique of any one or a few combination open the first window in MIS junction structures regions, first window bottom is up to barrier layer
On 305, inside barrier layer 305, preferably first window bottom is arranged from the region within 305 bottom 5nm of barrier layer.
S103, the preparation media layer in passivation layer and first window.
As shown in Fig. 4 (d), by techniques such as PECVD, LPCVD or ALD in the surface of passivation layer 307 and first window
SiN may be used in upper metallization medium layer 308, dielectric layer 308x、SiO2、SiON、Al2O3Or one kind or arbitrary in the materials such as AlN
Several combinations are constituted.
S104, the deposition anode metal layer on dielectric layer.
As shown in Fig. 4 (e), by the techniques such as evaporation, PVD, CVD on the surface of dielectric layer 308 deposited metal layer 309.
Anode metal layer 309 can be made of TiN, Ni, Au, W, at least one of materials such as Pt or Pd, and thickness could be provided as
100nm。
S105, the second window and third window are opened in anode metal layer, the bottom of the second window and third window can
On barrier layer, inside barrier layer or barrier layer bottom.
As shown in Fig. 4 (f), first pass through yellow light and define ohm tie region, and by dry etching, wet etching or in which
The mode of any one or the combination of several of them opens the second window and third window of ohm knot, the second window in metal layer 309
With third window depth up to any one position on barrier layer 305, inside 305 inside of barrier layer or barrier layer 305.It is preferred that the
Two windows and third bottom of window are arranged on barrier layer 305.
S106, the deposit ohmic metal in anode metal layer surface and the second window and third window.
As shown in Fig. 4 (g), the metals such as ohmic metal Ti/Al/Ti/TiN, Ti/Al/Ni/Au or Ti/Al/Mo/Au are logical
Stacking is crossed to be constituted.The deposit ohmic metal 310 by way of PVD or vapor deposition.Deposited metal layer is to be sequentially depositing from top to bottom
Each layer metal, for example, its sedimentary sequence of Ti/Al/Mo/Au metal stacks is Ti layers first, at Al layers, then Mo layers, be finally Au
Layer.
S107, metal patternization form electrode and high temperature alloy
As shown in Fig. 4 (h), metal patternization removes extra ohmic metal layer 310, and usable photoetching adds the method for etching to go
It removes, lift-off techniques can also be used to remove.Then, by high temperature alloy, make between ohmic metal 310 and barrier layer 305
It is formed and good Ohmic contact is connected.Alloy temperature may be set to 850 DEG C., atmosphere is nitrogen environment.Material is thus formed partly lead
The cathode C of body device41Ohm junction structure and semiconductor devices with first anode A41With second plate A42It collectively forms
Composite anode.
Further, further include the protective layer for preparing semiconductor device surface.
It is thicker in the outside deposition of semiconductor devices by modes such as PECVD, LPCVD or ALD as shown in Fig. 4 (i)
SiO2、SiNxOr one kind in the materials such as Polyimide or arbitrary several combination, thickness may be set to 1um, and then formation guarantor
Sheath 311, then opening needs metal to be used on protective layer 311 by way of etching or developing, and has been used as semiconductor device
The electrode contact point of part.
Embodiment three：
Further, it is improved as the another kind of previous embodiment, as shown in figure 5, for the cross-sectional view of SBD, tool
Body includes sequentially generating in the buffer layer 402 on substrate 401, channel layer 403, barrier layer 405, cap layers 406, passivation layer 407, Jie
Matter layer 408, anode metal 409 and protective layer 410.
Wherein, the anode of semiconductor devices includes first anode A31With second plate A32, the cathode of semiconductor devices is the moon
Pole C31。
It is prepared specifically, the common substrate material such as GaN, SiC or Si can be used in substrate 401, thickness is according to practical need
It sets.Buffer layer 402 can be used the combination of the one or more of which such as superlattices, AlN and AlGaN and constitute.Channel layer 403 can be adopted
It is that material is constituted with GaN, thickness is 3~5 μm.Al can be used in barrier layer 405xGa1-xN,InxGa1-xN,InxAl1-xN, and
InxAlyGa1-x-yThe materials such as N constitute, thickness can 10~30nm, wherein the content range of Al may be set to 15%~30% it
Between.It is biased to 403 side of channel layer in the contact surface of channel layer 403 and barrier layer 405 and is formed with two-dimensional electron gas 404 (2DEG),
To promote the mobility of 2DEG, AlN layers can be inserted between channel layer 403 and barrier layer 405, thickness may be configured as 0.7
~2nm.The materials such as SiN, AlN or GaN composition can be used between passivation layer 407 and barrier layer 405 in cap layers 406.Passivation layer
407 effect is to protect the material interface of semiconductor devices deposition not oxidized or destroy, and SiN can be usedx、SiO2、SiON、
Al2O3Or any one of AlN materials or arbitrary several combinations are constituted.SiO can be used in the material of dielectric layer 4082、SiNx、
Al2O3、AlN、HfO2、MgO、Sc2O3、Ga2O3、AlHfOxWith any one of materials such as HfSiON or arbitrary several combinations compositions.
Wherein, first anode A31It is to be made of on barrier layer 405 with Ohmic contact configuration ohmic metal 411, and with the
Two anode As32Electrical connection.Second plate A32The MIS junctions of anode metal 409 and barrier layer 405 are then isolated by dielectric layer 408
Structure is constituted.Cathode C31It is to be configured on barrier layer 405 with Ohmic contact by ohmic metal 411.Ohmic metal 411 is by Ti/Al/
The metals such as Ti/TiN, Ti/Al/Ni/Au or Ti/Al/Mo/Au are constituted by stacking.Anode metal 409 by TiN, Ni, Au, W,
At least one of materials such as Pt and Pd are constituted；
Further, further include that protective layer 410 is used to protect semiconductor devices, SiO2, SiN can be used in materialx
Or one kind in the materials such as Polyimide (polyimides) or arbitrary several combination are constituted.
Use above specific case is illustrated the present invention, is merely used to help understand the present invention, not limiting
The system present invention.For those skilled in the art, according to the thought of the present invention, can also make several simple
It deduces, deform or replaces.
Claims (10)
1. a kind of semiconductor devices, which is characterized in that including：
III-V nitride semiconductor layer, the III-V nitride semiconductor layer include at least substrate, buffer layer, raceway groove
Layer, barrier layer；
The substrate is located at the bottom of the III-V nitride semiconductor layer, and the buffer layer is located on substrate and passes through institute
Channel layer is stated with the barrier layer to be isolated；
Passivation layer and dielectric layer；
The dielectric layer is kept apart with the barrier layer by the passivation layer；
First anode electrode is ohm junction structure, is configured on the barrier layer with Ohmic contact by ohmic metal；
Second plate electrode is electrically connected with the first anode electrode；The second plate electrode is MIS junction structures, described
MIS junction structures are configured by anode metal on the dielectric layer, and by the dielectric layer be isolated the anode metal with it is described
Barrier layer is constituted；
Cathode electrode is ohm junction structure, is configured on the barrier layer with Ohmic contact by the ohmic metal, and described
Second plate electrode and the first anode electrode are connectionless.
2. device as described in claim 1, which is characterized in that the dielectric layer bottom of the MIS knots is located at from the barrier layer
A certain position inside upper or barrier layer.
3. device as described in claim 1, which is characterized in that
The anode metal is made of TiN, Ni, Au, W, at least one of materials such as Pt or Pd；
The passivation layer is by SiNx、SiO2、SiON、Al2At least one of materials such as O3 or AlN are constituted；
The barrier layer is by AlxGa1-xN,InxGa1-xN,InxAl1-xN, or InxAlyGa1-x-yAt least one of the materials such as N structure
At.
4. device as described in claim 1, which is characterized in that the dielectric layer is by SiO2, SiNx、Al2O3、AlN、HfO2、
MgO、Sc2O3、Ga2O3、AlHfOxOr at least one of HfSiON materials are constituted.
5. device as described in claim 1, which is characterized in that further include：
Protective layer is formed on the outside of the semiconductor devices, and for sealing the semiconductor devices, the protective layer is by silicon
At least one of compound or polyimides are constituted.
6. device as described in claim 1, which is characterized in that further include：
Two-dimensional electron gas-bearing formation, the contact surface for being formed in the channel layer and the barrier layer are biased to channel layer side.
7. device as described in claim 1, which is characterized in that can be inserted between the barrier layer and the channel layer
The AlN of 0.7nm~2nm thickness, the mobility for promoting electronics in raceway groove.
8. a kind of preparation method of semiconductor devices, which is characterized in that including：
It is sequentially prepared buffer layer, channel layer, barrier layer and cap layers, and the deposit passivation layer in the cap layers on substrate；
First window is opened on the passivation layer, the bottom of the first window is located on the barrier layer or in barrier layer
Portion；
The preparation media layer on the passivation layer and the first window；
Thus the deposition anode metal layer on the dielectric layer forms in first window and the anode metal is isolated by dielectric layer
Layer and the barrier layer and the MIS junction structures that constitute, i.e., the second plate electrode of the described semiconductor devices；
The second window and third window are opened in the anode metal layer；The bottom position of second window and the third window
In on the barrier layer, inside barrier layer or three kinds of barrier layer bottom situation any one；
Deposit ohmic metal contacts in second window and the third window, and Ohmic contact is formed by the ohmic metal
Configuration on the barrier layer, respectively as the first anode electrode and cathode electrode of the semiconductor devices, and will it is described partly
The first anode electrode and the second plate electrode of conductor device are electrically connected collectively as the semiconductor devices
Anode electrode.
9. method as claimed in claim 8, which is characterized in that further include：
Protective layer is prepared in the outer surface of the semiconductor devices.
10. method as claimed in claim 8, which is characterized in that the ohmic metal is by Ti/Al/Ti/TiN, Ti/Al/Ni/Au
Or the metals such as Ti/Al/Mo/Au are constituted by stacking.
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Application publication date: 20181106 |