CN108763760A - A kind of system level chip based on two-stage BOOT structures - Google Patents
A kind of system level chip based on two-stage BOOT structures Download PDFInfo
- Publication number
- CN108763760A CN108763760A CN201810533154.5A CN201810533154A CN108763760A CN 108763760 A CN108763760 A CN 108763760A CN 201810533154 A CN201810533154 A CN 201810533154A CN 108763760 A CN108763760 A CN 108763760A
- Authority
- CN
- China
- Prior art keywords
- chip
- memory block
- boot
- piece
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Stored Programmes (AREA)
Abstract
The invention discloses a kind of system level chip based on two-stage BOOT structures, including Memory Controller, storage control is by on-chip bus connection processing device, ROM in on-chip bus connection sheet；Wherein Memory Controller connection memory block one and memory block two；Wherein memory block one includes serial PROM and parallel MRAM, and Memory Controller synchronization accesses serial PROM or parallel MRAM；Memory block two is parallel SRAM；ROM stores level-one BOOT instructions wherein in piece, and processor accesses the content of ROM storages in piece；Two level BOOT instructions and user program are stored wherein in memory block one；Wherein processor accesses BOOTSEL controlling switch；Memory Controller accesses ROMSEL controlling switch.The piece external storage body type of the startup address and access of electrification reset is selected by the way of hardware controls, and three kinds of electrifying startup modes of system level chip are realized based on two-stage BOOT structures.
Description
Technical field
The invention belongs to IC design technical fields；More particularly to a kind of system-level core based on two-stage BOOT structures
Piece.
Background technology
Existing SoC electrifying startups mainly use two methods：First, SoC it is external can random read take non-volatile device
Part is as program storage, and SoC reads instruction execution program directly from program storage after electrification reset；Second, SoC will be wrapped
It including the memory bank in piece and outside piece and marks off three regions, the respectively boot sections BOOT, program storage area and program executes area, on
SoC executes the instruction in the boot sections BOOT and the content of memory block is carried to execution area after reset, then jumps to program and holds
Row area executes user program.
In above two method, first method be suitable for SoC external FLASH or MRAM etc. can random read take memory
The case where as program area, these type memories support SoC to control random read take by address, and SoC can be deposited directly from these
Chu Tizhong reads instruction execution program.Second method be chiefly used in external serial PROM of SoC etc. can not random read take memory
The case where as program storage area, this kind of memory bank do not have address input, can only be handled according to input clock SOD serial output data
Device can not random fetching access this kind of memory bank, therefore can only will be in program storage area by the BOOT guiding mechanisms in piece
Program be transported to it is other can the program of random fetching execute area to realize load and startup.To meet a variety of different applications
Demand, designer often sets the program in the boot sections BOOT, and the program of external program memory block fixed size is (each to cover
Kind application demand, the generally data volume according to the size setting carrying of the maximum program of application) it is carried to program execution area, it deposits
It is inefficient and using underaction the problem of.
Above two method can solve the application demand of chip in some cases, but two methods exist centainly
Limitation and deficiency.In some cases, user needs SoC that can support a variety of electrifying startup modes, such as space application SoC
The case where, user space environment using when program and data can be stored in the non-volatile memory banks of serial or parallel,
SoC is loaded by BOOT after resetting and is completed electrifying startup, based on the considerations of the reliability and program backup that space uses, general feelings
Chip is also needed under condition to support a variety of BOOT modes and chip program is stored in different memory banks.And carry out ground in chip
When face is debugged, can generally it tend to using more directly efficient NOBOOT direct-execution modes.In different application scene
Under, user needs SoC to support a variety of BOOT load modes and electrifying startup mode, and needs highly efficient flexible BOOT loads
Mode is with easy to use.
There is the patent of many research BOOT methods at present, however, for compliant serial memory BOOT loads, parallel memorizing
The design structure of device BOOT loads and NOBOOT immediate execution modes, there is presently no discoveries.
Invention content
The present invention provides a kind of system level chips based on two-stage BOOT structures；On being selected by the way of hardware controls
The piece external storage body type of the startup address and access of reset, and realize the three of system level chip based on two-stage BOOT structures
Kind electrifying startup mode.
The technical scheme is that：A kind of system level chip based on two-stage BOOT structures, including Memory Controller,
Storage control is by on-chip bus connection processing device, ROM in on-chip bus connection sheet；Wherein Memory Controller connection storage
Area one and memory block two；Wherein memory block one includes serial PROM and parallel MRAM, and Memory Controller synchronization accesses
Serial PROM or parallel MRAM；Memory block two is parallel SRAM；ROM stores level-one BOOT instructions wherein in piece, and processor is visited
Ask the content that ROM is stored in piece；Two level BOOT instructions and user program are stored wherein in memory block one；Wherein processor accesses
BOOTSEL controlling switch；Memory Controller accesses ROMSEL controlling switch.
Further, the features of the present invention also characterized in that：
Wherein the System on Chip/SoC realizes that the mode of electrifying startup is：Electrifying startup is realized by parallel MRAM, by piece
ROM and parallel MRAM realizes electrifying startup or realizes electrifying startup by ROM in piece and serial PROM.
Level-one BOOT controllers are wherein provided in on-chip bus and piece between ROM, processor is controlled by level-one BOOT
Device accesses the content of ROM storages in piece.
Wherein processor connects on-chip bus by cache memory.
Wherein Memory Controller includes the address decoding unit being connect with on-chip bus；Address decoding unit passes through storage
Two controller of area connects memory block two；Address decoding unit connects one controller of memory block by selecting switch, and memory block one is controlled
Device processed connects memory block one.
Wherein one controller of memory block includes serial PROM controllers and parallel storage controller, and it is separately connected string
Row PROM and parallel MRAM.
Wherein the System on Chip/SoC is dsp chip, MCU chip or SoC chip.
Compared with prior art, the beneficial effects of the invention are as follows：The system level chip has storage and piece external storage in piece,
And three kinds of electrifying startup modes can be realized by two-stage BOOT instruction settings, meet the needs of a variety of applications.
Further, ROM cures level-one BOOT instructions and the realization piece external storage of piece external memory storage area one and piece memory in piece
The common program load for completing system level chip of storage, and the carrying of piece external memory storage area one can be adjusted flexibly according to practical application
Program size, it is more efficiently and flexible.Wherein piece external storage directly executes Starting mode, eliminates the process of program carrying, right
For simulating, verifying and chip testing link, this pattern saves the time, improves the verifiability of chip and can test
Property.
Further, which has preferable portable and versatility, can be in dsp chip, MCU chip
With applied in the chip of the multiple types such as SoC chip and framework.
Description of the drawings
Fig. 1 is the structural diagram of the present invention；
Fig. 2 is the schematic diagram that processor selection starts address in the present invention；
Fig. 3 is the structural schematic diagram of Memory Controller in the present invention.
Specific implementation mode
Technical scheme of the present invention is further illustrated in the following with reference to the drawings and specific embodiments.
The present invention provides a kind of system level chips based on two-stage BOOT structures, as shown in Figure 1, being controlled including memory
Device, Memory Controller connect on-chip bus, cache memory (cache) are provided between on-chip bus and processor,
Level-one BOOT controllers are provided in on-chip bus and piece between ROM；Memory Controller connects two extraneous memory blocks one
With memory block two, wherein memory block one includes serial PROM and parallel MRAM, and Memory Controller synchronization can only access
One of them；Memory block two is parallel SRAM.Wherein processor accesses BOOTSEL controlling switch, Memory Controller access
ROMSEL controlling switch.
As shown in figure 3, Memory Controller includes the address decoding unit being connect with on-chip bus, address decoding unit is logical
It crosses two controller of memory block and connects parallel SRAM memory (memory block two)；Address decoding unit connects selecting switch, and selection is opened
It closes through the serial PROM of serial PROM connections, selecting switch also connects parallel MRAM by parallel storage controller.Wherein
ROMSEL controlling switch accesses in selecting switch.
The present invention operation principle be：As shown in Fig. 2, processor is determined according to the input of external pin BOOTSEL
The first address of fetching after reset.BOOTSEL is to start the first address that address is memory block one after 0 expression processor reset,
BOOTSEL is the first address that the startup address after 1 expression processor reset is ROM in piece.
As shown in figure 3, Memory Controller addressing space is divided into two parts, memory block one and memory block two, memory block one
The access control for supporting two types memory bank, it is that 0 expression is worked as that the memory bank type of current accessed, ROMSEL are selected by ROMSEL
Preceding selection accesses parallel MRAM, and ROMSEL is that the current selection of 1 expression accesses serial PROM.Under serial mode, memory block one is external
Serial PROM storage two level BOOT instructions and user program.Under parallel schema, the external parallel MRAM in memory block one can be only
User program is stored, corresponds to Parallel Executing Scheme in this case；Parallel MRAM can also store two level BOOT instructions and user's journey
Sequence corresponds to loaded in parallel pattern in this case.Two level BOOT instruction can be by as the data being stored in piece external storage body
User is programmed, and user determines the content that two level BOOT is instructed according to practical application.Two external parallel memorizing body of memory block is made
Area is executed for the program under serial and concurrent loading mode.
Since serial RROM can not be used as program area, there are three types of electrifying startup sides for the system level chip tool of the present invention
Formula：Memory block one is parallel MRAM (i.e. program directly executes), in piece in ROM and parallel MRAM (BOOT loaded in parallel) and piece
ROM and serial PROM (BOOT is serially loaded).
Memory blocks of the ROM as the internal curing of System on Chip/SoC in piece, the BOOT instructions of storage level-one, level-one BOOT instructions are
Cure content in piece, processor accesses the content of ROM in piece by level-one BOOT controllers.The effect of level-one BOOT instruction is：
Processor executes level-one BOOT instructions, and the data (two level BOOT instructions) of fixed size in memory block one are transported to memory block two
It is interior, and jump to two first address of memory block and start to execute two level BOOT instructions.
By user program, user can be programmed according to actual application demand for two level BOOT instructions.Processor executes use
The two level BOOT instructions that family is write, user program is transported to redirect behind parallel memorizing area two from configuration address in memory block one and is held
Row user program, system level chip complete program designation and proceed by work.
The first above-mentioned electrifying startup mode, after processor electrification reset directly from the external parallel MRAM in memory block one
Instruction is read, and executes user program.
Above-mentioned second of electrifying startup mode, fetching is held since ROM first address in piece after system level chip electrification reset
Row level-one BOOT programs, execution are deposited the result is that instructing the parallel MRAM external from chip memory block one to be carried to two level BOOT
Storage area two then executes two level BOOT programs and completes user program from the external parallel memorizing body in memory block one to memory block two
It carries, finally executes user program in memory block two
The third above-mentioned electrifying startup mode, fetching executes one since ROM first address in piece after processor electrification reset
Grade BOOT programs, execution are carried to memory block two the result is that instructing two level BOOT from the serial PROM of chip memory block one,
Then two level BOOT programs are executed and complete user program from the serial PROM of memory block one to the carrying of memory block two, are then being deposited
Storage area two executes user program.
Level-one BOOT controllers are read accordingly after receiving the access request that processor passes through on-chip bus from ROM in piece
Content returns to processor.Based on structure of the present invention, in chip design stage, designer answers according to system level chip
With the assessment of situation, the content of level-one BOOT instructions is determined.According to the two-stage BOOT mechanism that the present invention uses, level-one BOOT is only needed
The data for carrying the address range that can cover two level BOOT instruction, by two level BOOT come determine user program size and
Storage address.After chip is realized, level-one BOOT instructions just have cured, as long as selection load mode starts, after each electrification reset
Chip can all execute level-one BOOT from the areas Pian Nei ROM and instruct and then complete electrifying startup.
The system level chip of the present invention can be applied and multiple types and the frameworks such as dsp chip, MCU chip and SoC chip
Chip in, there is preferable portable and versatility.
The present invention is applied in the SoC chip of a compatible SPARC V8 architecture processors, which has used this hair
BOOT control structures in the piece of bright proposition, can not only meet the reliability requirement of a variety of application demands and chip, improve simultaneously
The efficiency and flexibility that chip starts under the serial loading modes of BOOT, in addition, adopted by the simulating, verifying stage in chip
The efficiency of verification is substantially increased with NOBOOT immediate execution modes.The SoC chip has completed flow, BOOT controls
Structure function is normal, three kinds of equal normal operations of electrifying startup mode.Design structure of the present invention has higher portable
Property and reusability.
Claims (7)
1. a kind of system level chip based on two-stage BOOT structures, which is characterized in that including Memory Controller, storage control
By on-chip bus connection processing device, ROM in on-chip bus connection sheet；Wherein Memory Controller connection memory block one and storage
Area two；Wherein memory block one includes serial PROM and parallel MRAM, and Memory Controller synchronization access serial PROM or
Parallel MRAM；Memory block two is parallel SRAM；
ROM stores level-one BOOT instructions wherein in piece, and processor accesses the content of ROM storages in piece；
Two level BOOT instructions and user program are stored wherein in memory block one；
Wherein processor accesses BOOTSEL controlling switch；Memory Controller accesses ROMSEL controlling switch.
2. the system level chip according to claim 1 based on two-stage BOOT structures, which is characterized in that the System on Chip/SoC is real
Now the mode of electrifying startup is：Electrifying startup is realized by parallel MRAM, electrifying startup is realized by ROM in piece and parallel MRAM
Or electrifying startup is realized by ROM in piece and serial PROM.
3. the system level chip according to claim 1 based on two-stage BOOT structures, which is characterized in that the on-chip bus
Level-one BOOT controllers are provided between ROM in piece, processor is accessed in piece by level-one BOOT controllers in ROM storages
Hold.
4. the system level chip according to claim 1 based on two-stage BOOT structures, which is characterized in that the processor is logical
Cross cache memory connection on-chip bus.
5. the system level chip according to claim 1 based on two-stage BOOT structures, which is characterized in that the memory control
Device processed includes the address decoding unit being connect with on-chip bus；Address decoding unit connects memory block by two controller of memory block
Two；Address decoding unit connects one controller of memory block by selecting switch, and one controller of memory block connects memory block one.
6. the system level chip according to claim 5 based on two-stage BOOT structures, which is characterized in that the memory block one
Controller includes serial PROM controllers and parallel storage controller, and it is separately connected serial PROM and parallel MRAM.
7. the system level chip according to claim 1 based on two-stage BOOT structures, which is characterized in that the System on Chip/SoC is
Dsp chip, MCU chip or SoC chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810533154.5A CN108763760B (en) | 2018-05-29 | 2018-05-29 | System-level chip based on two-stage BOOT structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810533154.5A CN108763760B (en) | 2018-05-29 | 2018-05-29 | System-level chip based on two-stage BOOT structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108763760A true CN108763760A (en) | 2018-11-06 |
| CN108763760B CN108763760B (en) | 2022-03-22 |
Family
ID=64003781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810533154.5A Active CN108763760B (en) | 2018-05-29 | 2018-05-29 | System-level chip based on two-stage BOOT structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108763760B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110633223A (en) * | 2019-09-18 | 2019-12-31 | 北京机电工程研究所 | Multi-level memory management method for high-speed signal platform |
| CN112256338A (en) * | 2020-10-27 | 2021-01-22 | 记忆科技(深圳)有限公司 | SOC starting method and device, computer equipment and storage medium |
| CN113535248A (en) * | 2021-06-24 | 2021-10-22 | 合肥松豪电子科技有限公司 | TP chip power-on starting method for reducing SRAM space |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5590374A (en) * | 1993-09-10 | 1996-12-31 | Fujitsu Limited | Method and apparatus for employing a dummy read command to automatically assign a unique memory address to an interface card |
| US5634076A (en) * | 1994-10-04 | 1997-05-27 | Analog Devices, Inc. | DMA controller responsive to transition of a request signal between first state and second state and maintaining of second state for controlling data transfer |
| JP2001350642A (en) * | 1995-02-07 | 2001-12-21 | Hitachi Ltd | Data processing device |
| US20080288764A1 (en) * | 2007-05-15 | 2008-11-20 | Inventec Corporation | Boot-switching apparatus and method for multiprocessor and multi-memory system |
| CN202102449U (en) * | 2011-06-07 | 2012-01-04 | 郑州信大捷安信息技术股份有限公司 | SoC (System on Chip) chip-based external program security access framework |
| CN102779050A (en) * | 2011-04-29 | 2012-11-14 | 联想（新加坡）私人有限公司 | System and method for accelerated boot performance |
| CN105518621A (en) * | 2013-07-31 | 2016-04-20 | 马维尔国际贸易有限公司 | Parallelizing boot operations |
| US20170371834A1 (en) * | 2016-06-24 | 2017-12-28 | Sk Hynix Memory Solutions Inc. | Memory system and method for accelerating boot time |
-
2018
- 2018-05-29 CN CN201810533154.5A patent/CN108763760B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5590374A (en) * | 1993-09-10 | 1996-12-31 | Fujitsu Limited | Method and apparatus for employing a dummy read command to automatically assign a unique memory address to an interface card |
| US5634076A (en) * | 1994-10-04 | 1997-05-27 | Analog Devices, Inc. | DMA controller responsive to transition of a request signal between first state and second state and maintaining of second state for controlling data transfer |
| JP2001350642A (en) * | 1995-02-07 | 2001-12-21 | Hitachi Ltd | Data processing device |
| US20080288764A1 (en) * | 2007-05-15 | 2008-11-20 | Inventec Corporation | Boot-switching apparatus and method for multiprocessor and multi-memory system |
| CN102779050A (en) * | 2011-04-29 | 2012-11-14 | 联想（新加坡）私人有限公司 | System and method for accelerated boot performance |
| CN202102449U (en) * | 2011-06-07 | 2012-01-04 | 郑州信大捷安信息技术股份有限公司 | SoC (System on Chip) chip-based external program security access framework |
| CN105518621A (en) * | 2013-07-31 | 2016-04-20 | 马维尔国际贸易有限公司 | Parallelizing boot operations |
| US20170371834A1 (en) * | 2016-06-24 | 2017-12-28 | Sk Hynix Memory Solutions Inc. | Memory system and method for accelerating boot time |
Non-Patent Citations (3)
| Title |
|---|
| TI: "《TI手册》", 31 August 2009 * |
| 杨希让: "基于ADSP-TS201S的数字信号处理器设计", 《火控雷达技术》 * |
| 蔡浩: "一种NAND FLASH自启动的新方法", 《现代电子技术》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110633223A (en) * | 2019-09-18 | 2019-12-31 | 北京机电工程研究所 | Multi-level memory management method for high-speed signal platform |
| CN110633223B (en) * | 2019-09-18 | 2021-07-13 | 北京机电工程研究所 | Multi-level memory management method for high-speed signal platform |
| CN112256338A (en) * | 2020-10-27 | 2021-01-22 | 记忆科技(深圳)有限公司 | SOC starting method and device, computer equipment and storage medium |
| CN112256338B (en) * | 2020-10-27 | 2023-12-05 | 记忆科技(深圳)有限公司 | SOC starting method and device, computer equipment and storage medium |
| CN113535248A (en) * | 2021-06-24 | 2021-10-22 | 合肥松豪电子科技有限公司 | TP chip power-on starting method for reducing SRAM space |
| CN113535248B (en) * | 2021-06-24 | 2024-05-28 | 合肥松豪电子科技有限公司 | TP chip power-on starting method for reducing SRAM space |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108763760B (en) | 2022-03-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108763760A (en) | A kind of system level chip based on two-stage BOOT structures | |
| US6415393B2 (en) | Inspection of an integrated circuit device while being mounted on a circuit board | |
| US5519715A (en) | Full-speed microprocessor testing employing boundary scan | |
| JP4475709B2 (en) | Microcomputer | |
| CN100476837C (en) | MPU FPGA verification device supporting stochastic instruction testing | |
| JP5235202B2 (en) | Test apparatus and test method | |
| JP2009537934A (en) | Apparatus and method for reducing peak power consumption during common operation of multi-NAND flash memory devices | |
| CN101639901A (en) | Feedforward neural network hardware realization method based on multicore technology | |
| GB2582790A (en) | Debugging mechanism | |
| US20020124216A1 (en) | Integrated circuit and method of operation of such a circuit | |
| CN102486749A (en) | Method and system for data driving test | |
| CN103793263B (en) | DMA transaction-level modeling method based on Power PC processor | |
| CN113950721B (en) | JTAG-based architectures that allow multi-core operation | |
| CN104459522A (en) | Chip self-test method and system | |
| CN109283451A (en) | A kind of integrated circuit non-defective unit detection system and method | |
| KR101270179B1 (en) | Method and apparatus for cascade memory | |
| US9513912B2 (en) | Memory controllers | |
| CN113157334A (en) | FPGA multi-version program loading method | |
| Bernardi et al. | Using infrastructure IPs to support SW-based self-test of processor cores | |
| CN113946481B (en) | RISC-V kernel MCU debugging downloading program method and debugger | |
| CN113994434A (en) | Direct memory access using JTAG cell addressing | |
| CN115933579A (en) | ATE-based DSP chip test system | |
| CN101908016A (en) | Method for managing debugging information and break point of multi-core embedded device | |
| CN106874577A (en) | A kind of memory compiler | |
| US11984177B2 (en) | Memory component provided with a test interface |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |