CN108695233B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN108695233B CN108695233B CN201710233250.3A CN201710233250A CN108695233B CN 108695233 B CN108695233 B CN 108695233B CN 201710233250 A CN201710233250 A CN 201710233250A CN 108695233 B CN108695233 B CN 108695233B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
Abstract
The invention provides a semiconductor device and a manufacturing method thereof.A gas gap is formed on the side wall of a metal gate electrode layer of a metal gate laminated structure, so that the parasitic capacitance between the metal gate electrode and a subsequently formed source-drain region conductive structure is reduced, and the performance of the device is improved.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing technologies, and in particular, to a semiconductor device and a method for manufacturing the same.
Background
With the continuous development of integrated-circuit (IC) manufacturing technology, the feature size of Metal-Oxide-Semiconductor (MOS) devices is also getting smaller and smaller. With the feature size of the MOS device entering 45nm technology node and below, in order to greatly reduce gate tunneling current and gate resistance, eliminate polysilicon depletion effect, improve device reliability, and alleviate fermi level pinning effect, it has become common knowledge in the industry to use a high-K metal gate (HKMG) structure of a high-K gate dielectric layer/metal gate electrode instead of a conventional silicon dioxide/polysilicon gate stack structure.
However, in the conventional gate stack structure of the high-K gate dielectric layer and the metal gate electrode, the vertical sidewall of the gate opening is also covered with the high-K gate dielectric layer and the work function layer, which results in an increase in the parasitic capacitance between the source/drain contact hole and the metal gate electrode. This may degrade device performance such as reduced switching speed, increased signal delay or power consumption, etc. On the other hand, even for devices whose performance requirements are not high, it is desirable to obtain low power consumption, and therefore it is also desirable to reduce the parasitic capacitance.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, which can reduce the parasitic capacitance between a metal gate electrode and a source-drain region conductive structure and improve the performance of the device.
In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate with a first interlayer dielectric layer formed on the surface, wherein a metal gate stack structure is formed in the first interlayer dielectric layer and comprises a metal gate electrode layer and a work function layer surrounding the side wall of the metal gate electrode layer, the top of the metal gate electrode layer is not higher than that of the first interlayer dielectric layer, and the top of the work function layer is lower than that of the metal gate electrode layer;
forming a sacrificial layer on the top of the work function layer, wherein the top of the sacrificial layer is not higher than the top of the metal gate electrode layer;
forming a capping layer above the metal gate electrode layer and the sacrificial layer;
removing the sacrificial layer to form an air gap between the capping layer and the work function layer.
Optionally, the step of providing the semiconductor substrate includes:
providing a semiconductor substrate with a first interlayer dielectric layer formed on the surface, wherein a metal gate laminated structure with the top flush with the top of the first interlayer dielectric layer is formed in the first interlayer dielectric layer, and the metal gate laminated structure comprises a metal gate electrode layer and a work function layer surrounding the side wall of the metal gate electrode layer;
and etching back the metal gate electrode layer and the work function layer, or only etching back the work function layer, so that the top of the work function layer is lower than that of the metal gate electrode layer.
Optionally, when the metal gate electrode layer and the work function layer are etched back, the etch-back depth of the work function layer is 2-6 times that of the metal gate electrode layer.
Optionally, the sacrificial layer is an organic polymer capable of thermal decomposition.
Alternatively, the organic polymer is capable of thermal decomposition at temperatures above 300 ℃.
Optionally, the step of forming the sacrificial layer includes: depositing a sacrificial layer on the first interlayer dielectric layer and the surface of the metal grid laminated structure; and etching back the sacrificial layer until the top of the sacrificial layer is not higher than the metal gate electrode layer.
Optionally, the sacrificial layer is etched back by a dry etching process.
Optionally, the capping layer includes an oxide layer and a nitride layer sequentially formed on the surfaces of the metal gate electrode layer and the sacrificial layer.
Optionally, the forming process of the capping layer includes:
forming an oxide layer above the first interlayer dielectric layer, the sacrificial layer and the metal gate laminated structure by adopting a process with the temperature lower than 200 ℃;
depositing a nitride layer on the surface of the oxide layer;
and removing the redundant nitride layer and the redundant oxide layer above the first interlayer dielectric layer by adopting a chemical mechanical planarization process.
Optionally, the air gap is formed by removing the sacrificial layer through an annealing process, an ultraviolet light irradiation process, or an infrared light irradiation process.
Optionally, when a semiconductor substrate with a first interlayer dielectric layer formed on a surface thereof is provided, the work function layer covers the sidewall of the metal gate electrode layer, and also partially or completely covers the bottom of the metal gate electrode layer, and a high-K gate dielectric layer is further provided between the work function layer and the semiconductor substrate.
Optionally, the semiconductor device is a fin transistor.
Optionally, after forming the air gap, a second interlayer dielectric layer is formed on the surface of the capping layer and the first interlayer dielectric layer.
Optionally, the dielectric constants of the first interlayer dielectric layer and the second interlayer dielectric layer are both lower than the dielectric constant of the capping layer.
The present invention also provides a semiconductor device comprising:
a semiconductor substrate;
the first interlayer dielectric layer is positioned on the surface of the semiconductor substrate;
the metal gate stack structure is positioned in the first interlayer dielectric layer and comprises a metal gate electrode layer and a work function layer surrounding the side wall of the metal gate electrode layer, the top of the metal gate electrode layer is not higher than the top of the first interlayer dielectric layer, and the top of the work function layer is lower than the top of the metal gate electrode layer;
and the sealing cover layer is positioned above the metal gate electrode layer, and an air gap is formed between the sealing cover layer and the work function layer.
Optionally, the capping layer includes an oxide layer and a nitride layer sequentially formed on the surface of the metal gate electrode layer.
Optionally, the work function layer covers the sidewall of the metal gate electrode layer, partially or completely covers the bottom of the metal gate electrode layer, and a high-K gate dielectric layer is further disposed between the work function layer and the semiconductor substrate.
Optionally, the semiconductor device further includes a second interlayer dielectric layer covering the capping layer and the surface of the first interlayer dielectric layer.
Optionally, the dielectric constants of the first interlayer dielectric layer and the second interlayer dielectric layer are both lower than the dielectric constant of the capping layer.
Optionally, the semiconductor device is a fin transistor.
Compared with the prior art, the technical scheme of the invention has the following technical effects:
1. an air gap is formed in a space formed by the height difference between the work function layer of the metal gate laminated structure and the metal gate electrode layer, so that the air gap is formed between the metal gate electrode and the conductive structures such as the contact hole of the source drain region, the metal silicide or the metal interconnecting wire, the parasitic capacitance between the source drain contact hole and the metal gate electrode is greatly reduced, and the performance of the device is improved.
2. The mechanical property at the air gap is ensured by forming a capping layer with a dielectric constant higher than that of the first interlayer dielectric layer and the second interlayer dielectric layer above the air gap, such as a laminated structure of a low-temperature oxide layer and a silicon nitride layer, so that the electrical stability and reliability of the device are ensured.
Drawings
FIG. 1 is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention;
fig. 2A to 2H are schematic device cross-sectional structures in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
In order to avoid the influence of the metal material of the metal gate electrode on other structures of the MOS device, in the prior art, a metal gate stack structure formed by the metal gate electrode and the high-K gate dielectric layer is usually manufactured by a gate replacement (replacement gate) process. In the process, before a source-drain region is formed, a dummy gate (dummy gate) made of polysilicon is formed at a gate electrode position to be formed, and the dummy gate is used for self-alignment process treatment such as forming the source-drain region; after forming the source and drain regions, removing the virtual grid and forming a grid opening at the position of the virtual grid; then, sequentially filling a high-K gate dielectric layer, a work function layer (for adjusting threshold voltage) and a metal gate electrode layer in the gate opening, so as to form a metal gate laminated structure; and then, depositing interlayer dielectric layers for manufacturing the source and drain region conductive structures on the metal gate laminated structure and the surfaces of the devices on the two sides of the metal gate laminated structure, and manufacturing the conductive structures such as contact holes, contact plugs or M0 layers of metal interconnection lines and the like aligned to the source and drain regions by using the interlayer dielectric layers. Because the metal gate electrode is manufactured after the source and drain regions are formed, the number of subsequent processes is reduced, and the problem that metal materials are not suitable for high-temperature treatment is avoided.
However, many problems still exist in fabricating MOS devices using the above gate replacement process, and these problems become more serious as the gate length is further reduced. For example, in a metal gate stack structure formed by the gate replacement process, the vertical sidewall of the gate opening is also covered with a high-K gate dielectric layer and a work function layer, which results in an increase in parasitic capacitance between the source and drain regions and the metal gate electrode. And unnecessary parasitic capacitance increases affect device performance.
The semiconductor device and the manufacturing method thereof have the core idea that after the metal gate laminated structure is formed and before the interlayer dielectric layer for manufacturing the source drain region conductive structure is formed, the air gap is manufactured by utilizing the space formed by the height difference between the metal gate electrode layer and the work function layer in the metal gate laminated structure, so that the parasitic capacitance between the metal gate electrode and the source drain region is reduced, and the device performance is improved.
The present invention will be described in more detail with reference to the accompanying drawings, which are included to illustrate embodiments of the present invention.
Referring to fig. 1, the present embodiment provides a method for manufacturing a semiconductor device, including the following steps:
s1, providing a semiconductor substrate with a first interlayer dielectric layer formed on the surface, wherein a metal gate stack structure is formed in the first interlayer dielectric layer and comprises a metal gate electrode layer and a work function layer surrounding the side wall of the metal gate electrode layer, the top of the metal gate electrode layer is not higher than that of the first interlayer dielectric layer, and the top of the work function layer is lower than that of the metal gate electrode layer;
s2, forming a sacrificial layer on the top of the work function layer, wherein the top of the sacrificial layer is not higher than the top of the metal gate electrode layer;
s3, forming a sealing cover layer above the metal gate electrode layer and the sacrificial layer;
s4, removing the sacrificial layer to form an air gap between the capping layer and the work function layer.
Referring to fig. 2A, in step S1, the step of providing the semiconductor substrate having the first interlayer dielectric layer 201 and the metal gate stack structure (including the metal gate electrode layer 205, the work function layer 204, the high-K gate dielectric layer 203, and the sidewall spacers 202) includes:
s11, a semiconductor substrate 200 is provided, the semiconductor substrate 200 may be of any type known in the electronic arts, such as bulk silicon, semiconductor-on-insulator (SOI), silicon germanium-on-insulator (sige-on-insulator), FIN-type, or any other type. Preferably FIN type, that is, the semiconductor substrate 200 has FINs (FIN) perpendicular to the surface, and a FinFET device (i.e., a FIN-type transistor device, which is three-dimensional) is fabricated using the FINs to improve the device performance, and the FIN is specifically formed by: a semiconductor epitaxial layer (e.g., a SiGe layer or a Si layer) with a certain thickness is epitaxially grown on the surface of the semiconductor substrate 200, and the semiconductor epitaxial layer is vertically etched to form a fin of the FinFET. Then, a gate dielectric layer, a polysilicon layer and a silicon nitride mask layer are sequentially deposited on the surface of the semiconductor substrate 200 by a known deposition process, such as CVD (chemical vapor deposition), atomic layer deposition, sputtering, etc., wherein the deposition thickness of the polysilicon layer determines the height of a metal gate stack structure to be formed subsequently, and the gate dielectric layer may be silicon dioxide, silicon nitride, silicon oxynitride or a high-K dielectric having a dielectric constant K greater than that of silicon dioxide.
S12, forming a grid pattern on the photoresist layer through spin coating photoresist on the silicon nitride mask layer and through a photoetching process including exposure and development, and then etching the silicon nitride hard mask layer through a dry etching process by using the photoresist as a mask so as to transfer the grid pattern onto the silicon nitride hard mask layer and remove the photoresist layer; then, taking the silicon nitride hard mask layer as a mask, and sequentially etching the polysilicon layer and the gate dielectric layer from top to bottom through a dry etching process so as to form a virtual gate structure on the fin;
s13, depositing sidewall materials on the semiconductor substrate 200 and the surface of the dummy gate structure by a chemical vapor deposition process, and etching the sidewall materials by a dry etching process to form the sidewall 202 surrounding the dummy gate structure, wherein the silicon nitride hard mask layer protects the dummy gate structure below during the etching of the sidewall 202; the silicon nitride hard mask layer is then removed by a chemical mechanical planarization process or the like.
S14, taking the virtual gate structure and the side wall 202 as masks, and directly performing source and drain region ion implantation (including light doping and heavy doping) and annealing activation in the fins on the two sides of the virtual gate structure and the side wall 202 to form a source and drain region; or, etching the fins on the two sides of the dummy gate structure and the sidewall 202 by a dry etching process or by a combination of the dry etching process and a wet etching process to form a source-drain trench, then performing a semiconductor layer epitaxy different from a fin material on the source-drain trench by a selective epitaxy process, performing ion doping on the epitaxial semiconductor layer in an epitaxy process or performing ion implantation on the semiconductor layer after the epitaxy, and annealing to form the source-drain region.
S15, depositing the first interlayer dielectric layer 201 on the surface of the semiconductor substrate, the dummy gate structure and the sidewall spacers 202 by a known deposition process, such as CVD (chemical vapor deposition), atomic layer deposition, sputtering, etc., and planarizing the top of the first interlayer dielectric layer 201 until the surface of the polysilicon layer of the dummy gate structure is exposed. The first interlayer dielectric layer 201 is a low-K dielectric material having a dielectric constant (which may be lower than 2.0) lower than that of silicon dioxide, such as an organic porous material.
And S16, removing the polysilicon layer of the virtual gate structure or removing the polysilicon layer of the virtual gate structure and the lower gate dielectric layer by adopting a wet etching process or a dry etching process or a process combining the dry etching process and the wet etching process to form a gate opening.
S17, when the gate dielectric layer remaining after removing the polysilicon layer of the dummy gate structure in step S16 is a high-K dielectric, the work function layer 204 and the metal gate electrode layer 205 may be directly and sequentially formed in the gate opening, and the gate dielectric layer at the bottom of the gate opening is used as the high-K gate dielectric layer 203. When the dummy gate structure is completely removed in step S16 or the gate dielectric layer remaining after the polysilicon layer of the dummy gate structure is removed in step S16 is not a high-K dielectric, the high-K gate dielectric layer 203, the work function layer 204, and the metal gate electrode layer 205 are sequentially deposited in the gate opening. While the work function layer 204 and the metal gate electrode layer 205 are sequentially deposited in the gate opening, the work function layer 204 and the metal gate electrode layer 205 are also formed on the top of the sidewall 202 and the first interlayer dielectric layer 201, and then the top of the metal gate electrode layer 205 is planarized by using a Chemical Mechanical Planarization (CMP) process until the top of the first interlayer dielectric layer 201 is exposed, so that a metal gate stack structure flush with the top of the first interlayer dielectric layer 201 is formed.
The high-K gate dielectric layer 203 may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, with hafnium oxide, zirconium oxide, titanium oxide, and aluminum oxide being particularly preferred. high-K gate dielectric layer 203 may be formed on the bottom of the gate opening and on all sidewalls of the gate opening by using a deposition method such as a Chemical Vapor Deposition (CVD), low pressure CVD, atomic layer CVD, or Physical Vapor Deposition (PVD) process. Preferably, an atomic layer CVD process is used so that the flow rates, temperatures, and pressures of the metal oxide precursor (e.g., metal chloride) and steam in the reactor can be controlled to produce an atomically smooth interface and desired thickness between the gate opening surface and the high-K gate dielectric layer 203.
The work function layer 204 may be formed by an atomic layer CVD process or a PVD process. Work function layer 204 may comprise one or more layers and when used to form an NMOS transistor, sufficient elements with relatively low electronegativity (electronegativity less than about 1.7) should be used, such as the lanthanide metals, scandium, zirconium, hafnium, aluminum, titanium, tantalum, niobium, tungsten, and other potentially useful elements including alkali metals and alkaline earth metals, where alkali metals refer to the metal elements in column 1, i.e., group ia of the transverse periodic table, including, starting from cycle 2, elemental lithium (Li) No. 3, elemental sodium (Na) No. 11, elemental potassium (K) No. 19, elemental rubidium (Rb) No. 37, elemental cesium (Cs) No. 55, and elemental francium (Fr) No. 87; alkaline earth metal refers to the metal element of column 2, i.e., group iia of the transverse periodic table, and includes, from cycle 2, beryllium (Be) element 4, magnesium (Mg) element 12, calcium (Ca) element 20, strontium (Sr) element 38, barium (Ba) element 56, francium (Ra) element 88, it can Be seen that the work function layer 204 for forming NMOS transistors can Be titanium nitride, thallium nitride, titanium aluminum alloy, titanium aluminum nitride, and tungsten nitride, while when forming PMOS transistors, sufficient elements with relatively high electronegativity (electronegativity value greater than about 2.8) should Be used (e.g., nitrogen, chlorine, oxygen, fluorine, and bromine), it can Be seen that the work function layer 204 for forming PMOS transistors can Be titanium nitride, thallium nitride, tungsten nitride, and the like.
The metal gate electrode layer 205 may be formed by an atomic layer CVD process, a PVD process, a sputtering deposition process, or the like, and any metal-containing conductive material of the metal gate electrode layer 205 (i.e., a gate electrode that does not contain a large amount of silicon or polysilicon) may include one or more of aluminum, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum, tungsten, ruthenium, palladium, molybdenum, niobium, and alloys of these and other elements, metal carbides (e.g., titanium carbide, zirconium carbide, tantalum carbide, tungsten carbide, and thallium carbide), metal nitrides (e.g., tantalum nitride, titanium nitride, thallium nitride), metal silicides (e.g., tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, thallium silicide nitride silicide).
S18, referring to FIG. 2B, the metal gate electrode layer 205 and the work function layer 204 in the metal gate stack structure may be selectively etched back to different degrees, so that the top of the metal gate electrode layer 205 is higher than the top of the work function layer 204 and lower than the top of the first interlayer dielectric layer 201, a gate back etching groove is formed, a back etching process may be performed by dry etching or wet etching, the back etching depth of the work function layer 204 may be 2-6 times the back etching depth of the metal gate electrode layer 205, for example, the back etching depth of the metal gate electrode layer 205 is 100A-300A, and the back etching depth of the work function layer 204 is 300A-600A. Under the condition that the metal gate electrode layer 205 and the work function layer 204 are etched back, the part of the subsequently formed capping layer above the metal gate electrode layer 205 is not higher than the top of the first interlayer dielectric layer 201; in other embodiments of the present invention, only the work function layer 204 may be etched back, and the top of the metal gate electrode layer 205 is kept flush with the top of the first interlayer dielectric layer 201, and the portion of the capping layer formed in the subsequent step S3 above the metal gate electrode layer 205 is higher than the top of the first interlayer dielectric layer 201, which is equivalent to a convex cap, and an air gap may also be formed above the work function layer, and finally the parasitic capacitance between the metal gate electrode and the conductive structure of the source/drain region is reduced, and then a second interlayer dielectric layer with a planarized top surface covering the first interlayer dielectric layer 201 and the capping layer may be formed to provide a planar process surface for the subsequent process.
In step S2, referring to fig. 2C, a sacrificial layer 206 is deposited on the surface of the first interlayer dielectric layer 201 and the surface of the gate etch-back trench by a low temperature chemical vapor deposition process, wherein the sacrificial layer 206 is a decomposable material, typically an organic polymer, which is thermally decomposed at a thermal decomposition temperature of 300 ℃. The process parameters for depositing the sacrificial layer comprise: the power is 100W-2000W, the methane gas flow is 5 SCCM-100 SCCM, the pressure is 5 mtorr-100 mtorr, and the process time is 6 s-100 s. Since the thickness of the work function layer 204 on the sidewall of the gate opening is thin, for example 25 a-200 a, below the 20nm technology node, and the etch back depth of the work function layer 204 is relatively large, at this time, the width of the space (or referred to as a gap) formed by the height difference between the metal gate electrode layer 205 and the work function layer 204 is narrow, that is, the space is a slit with a high aspect ratio, when the sacrificial layer 206 made of a thermally decomposable organic polymer material is deposited by using cryochemical vapor deposition, the sacrificial layer 206 mainly covers the surfaces of the metal gate electrode layer 205, the high K203 and the first interlayer dielectric layer 201, and easily covers the space between the metal gate electrode layer 205 and the work function layer 204 to form an air gap, and automatically sinks and fills in the space between the metal gate electrode layer 205 and the work function layer 204 due to the gravity effect, the flowability and the adhesion of the thermally decomposable organic polymer film deposited by cryochemical vapor deposition, when the sacrificial layer 206 has a certain thickness on the surface of the first interlayer dielectric layer 201, the bottom of the sacrificial layer may reach the surface of the work function layer 204, or the sacrificial layer 206 may not reach the surface of the work function layer 204 and has a certain gap with the surface of the work function layer 204, so that the thickness of the work function layer 204 on the sidewall of the metal gate electrode layer and the material and deposition thickness of the sacrificial layer 206 determine whether there is a gap between the top of the work function layer 204 and the sacrificial layer 206, and it is obvious that when the thickness of the work function layer 204 on the sidewall of the metal gate electrode layer is sufficiently thick, the sacrificial layer 206 may generally be directly deposited on the top surface of the work function layer 204 without generating a gap with the top surface of the work function layer 204.
Then, referring to fig. 2D, the deposited sacrificial layer 206 is etched back by using a dry etching process until the top of the sacrificial layer 206 is not higher than the top of the metal gate electrode layer 205, for example, the top of the sacrificial layer 206 is lower than the top of the metal gate electrode layer 205 by 50 a to 100 a, and the process parameters of etching back the sacrificial layer 206 include: the power is 100W-2000W, the flow of oxygen is 20 SCCM-200 SCCM, the pressure is 5 mtorr-100 mtorr, and the process time is 6 s-100 s. After the etching back of the sacrificial layer 206 is finished, the sacrificial layer 206 with a certain thickness only exists in the space between the metal gate electrode layer 205 and the work function layer 204 in the gate etching back groove, and the surface of the first interlayer dielectric layer 201 does not have the sacrificial layer 206.
In step S3, first, referring to fig. 2E, an oxide layer 207 and a nitride layer 208 are sequentially deposited on the surfaces of the first interlayer dielectric layer 201, the sidewall 202, and the metal gate electrode layer 205 by using a low temperature chemical vapor deposition process or an atomic layer deposition process with a process temperature lower than 200 ℃, as materials of a capping layer, where, when the top of the sacrificial layer 206 is greatly lower than the top of the metal gate electrode layer 205, due to the limitation of the spatial dimension and the process technology capability, the oxide layer 207 may be suspended above the sacrificial layer 206 or may directly contact the upper surface of the sacrificial layer 206, the deposition thickness of the oxide layer 207 is 20 a to 50 a, and the deposition thickness of the nitride layer 208 is 400 a to 1000 a, similar to the deposition process of the sacrificial layer 206. Then, referring to fig. 2F, a chemical mechanical planarization process is used to remove the excess nitride layer 208 and the excess oxide layer 207 above the first interlayer dielectric layer 201, so that the nitride layer 208 and the oxide layer 207 are only filled in the gate etch-back trench, and the top surface of the nitride layer 208 is flush with the top surface of the first interlayer dielectric layer 201, thereby forming a capping layer, i.e., the capping layer includes the nitride layer 208 and the oxide layer 207 remaining after the chemical mechanical planarization process. In other embodiments of the present invention, the top of the middle region of the capping layer may also be lower or higher than the top of the first interlayer dielectric layer 201, and the peripheral region covers the surface of the first interlayer dielectric layer 201.
Referring to fig. 2G, in step S4, the remaining sacrificial layer is thermally decomposed by an annealing process or an ultraviolet light irradiation process or an infrared light irradiation process, so that a communicating air gap 209 is formed between the oxide layer 207 of the capping layer and the underlying work function layer 204. The temperature required to thermally decompose the remaining sacrificial layer may vary depending on the chemical deposition temperature of the sacrificial layer and the thickness dimension of the sacrificial layer. The capping layer is used to form the air gap 209, and on the other hand, can provide a process surface flush with the top of the first interlayer dielectric layer 201, and the dielectric constant of the capping layer is generally higher than that of the first interlayer dielectric layer 201 (generally, a low-K dielectric with a dielectric constant lower than 2.0) and a subsequently formed second interlayer dielectric layer (generally, a low-K dielectric with a dielectric constant lower than 2.0), so that the capping layer can play a role of supporting the subsequent layers to ensure the mechanical strength of the device. The air gap 209 has a lower dielectric constant so that parasitic capacitance can be reduced.
Referring to fig. 2H, after forming the air gap 209, first, a second interlayer dielectric layer 210 may be deposited on the capping layer (i.e., the nitride layer 208 and the oxide layer 207) and the surface of the first interlayer dielectric layer 201 by a chemical vapor deposition process, and the second interlayer dielectric layer 210 may be a low-K dielectric having a dielectric constant lower than that of silicon dioxide, and may be made of the same material as the first interlayer dielectric layer 201. Then, sequentially etching the second interlayer dielectric layer 210 and the first interlayer dielectric layer 201 above the source-drain region by a dry etching process to form a wiring groove or a contact hole which is aligned with the source-drain region and exposes the surface of the source-drain region; then, a metal conductive material and the like are deposited in the formed wiring trench or the contact hole to form a metal interconnection line (M0), a metal silicide contact (contact) or a contact plug (plug) and other conductive structures 211, and the conductive structures 211 are in electrical contact with the source and drain regions and used for leading the source and drain regions outwards.
In other embodiments of the present invention, when the sacrificial layer is a material that is not thermally decomposable, a material that can be removed by a process such as wet etching may be selected and then selectively removed by a process such as wet etching.
Referring to fig. 2H, the present embodiment further provides a semiconductor device, which may be a fin-type transistor, and may be a common high-K metal gate transistor device, including a semiconductor substrate 200, a first interlayer dielectric layer 201, a metal gate stack structure, a capping layer, a second interlayer dielectric layer 210, and a conductive structure 211.
The first interlayer dielectric layer 201 is located on the surface of the semiconductor substrate 200, wherein a gate opening exposing the surface of the semiconductor substrate 200 is formed. The metal gate stack structure is filled in the gate opening of the first interlayer dielectric layer 201, and includes a metal gate electrode layer 205, and a work function layer 204, a high-K gate dielectric layer 203, and a sidewall 202 surrounding the sidewall of the metal gate electrode layer 205 in sequence, wherein the top of the metal gate electrode layer 205 is not higher than the top of the first interlayer dielectric layer 201, and the top of the work function layer 204 is lower than the top of the metal gate electrode layer 205. In this embodiment, the work function layer 204 partially or completely covers the bottom of the metal gate electrode layer 205, besides completely covering the sidewall of the metal gate electrode layer 205, and a high-K gate dielectric layer 203 is further disposed between the work function layer 204 and the semiconductor substrate 200. In addition, source/drain regions are formed in the semiconductor substrate 200 on both sides of the sidewall spacers 202.
The capping layer in this embodiment includes an oxide layer 207 and a nitride layer 208 sequentially covering the surface of the metal gate electrode layer 205, and an air gap is formed between the bottom of the oxide layer 207 and the top of the work function layer 204, and when the top of the metal gate electrode layer 205 is lower than the first interlayer dielectric layer 201, the capping layer is preferably located in the gate opening and the top is flush with the first interlayer dielectric layer 201, so as to provide a flat process surface for forming the second interlayer dielectric layer 210. When the top of the metal gate electrode layer 205 is flush with the first interlayer dielectric layer 201, the capping layer covers the top of the gate opening, the middle region is in contact with the top of the metal gate electrode layer 205, the edge region is lapped on the top of the high-K gate dielectric layer 203, and the top of the capping layer is higher than the top of the first interlayer dielectric layer 201.
The second interlayer dielectric layer 210 covers the surfaces of the capping layer, the sidewall 202, the high-K gate dielectric layer 203 and the first interlayer dielectric layer 201, and the dielectric constants of the first interlayer dielectric layer 201 and the second interlayer dielectric layer 210 are preferably lower than the dielectric constant of the capping layer, so that the parasitic capacitance of the semiconductor device is reduced, and the performance of the semiconductor device is improved. The conductive structure 211 penetrates through the second interlayer dielectric layer 210 and the second interlayer dielectric layer 210, and the bottom of the conductive structure is electrically contacted with the source/drain regions in the semiconductor substrate 200 at the two sides of the sidewall 202.
In summary, according to the semiconductor device and the manufacturing method thereof of the present invention, an air gap is formed on the sidewall of the metal gate electrode layer in the metal gate stack structure, so that the parasitic capacitance between the metal gate electrode and the subsequently formed source/drain conductive structure is reduced, and the device performance is improved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (14)
1. A method of manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate with a first interlayer dielectric layer formed on the surface, wherein a metal gate stack structure is formed in the first interlayer dielectric layer and comprises a metal gate electrode layer and a work function layer surrounding the side wall of the metal gate electrode layer, the top of the metal gate electrode layer is not higher than that of the first interlayer dielectric layer, and the top of the work function layer is lower than that of the metal gate electrode layer;
forming a sacrificial layer on the top of the work function layer, wherein the top of the sacrificial layer is not higher than the top of the metal gate electrode layer, and a gap is formed between the bottom of the sacrificial layer and the top surface of the work function layer;
forming a capping layer above the metal gate electrode layer and the sacrificial layer;
removing the sacrificial layer to form an air gap between the capping layer and the work function layer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of providing the semiconductor substrate comprises:
providing a semiconductor substrate with a first interlayer dielectric layer formed on the surface, wherein a metal gate laminated structure with the top flush with the top of the first interlayer dielectric layer is formed in the first interlayer dielectric layer, and the metal gate laminated structure comprises a metal gate electrode layer and a work function layer surrounding the side wall of the metal gate electrode layer;
and etching back the metal gate electrode layer and the work function layer, or only etching back the work function layer, so that the top of the work function layer is lower than that of the metal gate electrode layer.
3. The method according to claim 2, wherein when the metal gate electrode layer and the work function layer are etched back, the etch-back depth of the work function layer is 2 times to 6 times the etch-back depth of the metal gate electrode layer.
4. The method for manufacturing a semiconductor device according to claim 1, wherein the sacrificial layer is an organic polymer capable of thermal decomposition.
5. The method for manufacturing a semiconductor device according to claim 4, wherein the organic polymer is thermally decomposable at a temperature of 300 ℃ or higher.
6. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the sacrifice layer includes: depositing a sacrificial layer on the first interlayer dielectric layer and the surface of the metal grid laminated structure; and etching back the sacrificial layer until the top of the sacrificial layer is not higher than the metal gate electrode layer.
7. The manufacturing method of a semiconductor device according to claim 6, wherein the sacrifice layer is etched back by a dry etching process.
8. The method for manufacturing a semiconductor device according to claim 1, wherein the capping layer comprises an oxide layer and a nitride layer which are sequentially formed on surfaces of the metal gate electrode layer and the sacrificial layer.
9. The method for manufacturing a semiconductor device according to claim 8, wherein the forming of the capping layer comprises:
forming an oxide layer above the first interlayer dielectric layer, the sacrificial layer and the metal gate laminated structure by adopting a process with the temperature lower than 200 ℃;
depositing a nitride layer on the surface of the oxide layer;
and removing the redundant nitride layer and the redundant oxide layer above the first interlayer dielectric layer by adopting a chemical mechanical planarization process.
10. The method for manufacturing a semiconductor device according to claim 1, wherein the air gap is formed by removing the sacrificial layer through an annealing process, an ultraviolet light irradiation process, or an infrared light irradiation process.
11. The method according to claim 1, wherein when the semiconductor substrate having the first interlayer dielectric layer formed on a surface thereof is provided, the work function layer partially or completely covers a bottom of the metal gate electrode layer in addition to a sidewall of the metal gate electrode layer, and a high-K gate dielectric layer is further provided between the work function layer and the semiconductor substrate.
12. The method of manufacturing the semiconductor device according to claim 1, wherein the semiconductor device is a fin transistor.
13. The method of manufacturing a semiconductor device according to claim 1, wherein a second interlayer dielectric layer is formed on the capping layer and the surface of the first interlayer dielectric layer after the air gap is formed.
14. The method for manufacturing a semiconductor device according to claim 13, wherein the dielectric constant of each of the first interlayer dielectric layer and the second interlayer dielectric layer is lower than the dielectric constant of the capping layer.
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| US20150221742A1 (en) * | 2014-02-04 | 2015-08-06 | Samsung Electronics Co., Ltd. | Semiconductor device and fabricating method thereof |
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| US20160204262A1 (en) * | 2014-01-28 | 2016-07-14 | Kang-ill Seo | Integrated circuit devices having air-gap spacers and methods of manufacturing the same |
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