CN108693404A - Link impedance detection chip and method - Google Patents
Link impedance detection chip and method Download PDFInfo
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- CN108693404A CN108693404A CN201710221938.XA CN201710221938A CN108693404A CN 108693404 A CN108693404 A CN 108693404A CN 201710221938 A CN201710221938 A CN 201710221938A CN 108693404 A CN108693404 A CN 108693404A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/08—Locating faults in cables, transmission lines, or networks
- G01R31/11—Locating faults in cables, transmission lines, or networks using pulse reflection methods
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- General Physics & Mathematics (AREA)
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Abstract
A kind of chip and link impedance detecting method, the chip are connected to another chip by hardware link.The chip generates step signal by signal generator and edge control device, the step signal is to the testing impedance circuit transmission for connecting hardware link with the transmission circuit of the chip and being connected between the processing circuit of the chip and the hardware link, the step signal reflects when by the different line impedance of resistance value in the hardware link, signal transmission after reflection is to the testing impedance circuit, the signal voltage value of the testing impedance circuit is passed through in the sampling of testing impedance circuit period property described in handled circuit control, and the line impedance at the different location in the hardware link is determined according to the sampled voltage that sampling time and each sampling time are sampled.
Description
Technical field
The present invention relates to link testing impedance field, more particularly to a kind of link impedance detection chip and method.
Background technology
One large-scale hardware system (such as cabinet in certain data center base station) generally can be by multiple module (examples
Such as, Field Replaceable Unit (Field Replace Unit, FRU)) composition.Each module needs to cooperate, between module
When collaborative work, the transmission of signal is needed, the carrier that these signals transmit is exactly hardware link.But when this hardware link goes out
When now abnormal, it is difficult to be accurately positioned out it is abnormal go out where.As shown in Figure 1, working as the hard of the chip B of FRU A chip A to FRU B
After exception occurs in part link, problem possibly is present at 10 positions (1 to 10 place of number in Fig. 1), and wherein position 1-5 is located at core
The transmission link of piece A, position 6-10 are located at the receives link of chip B.Existing way is to chip A to the hardware chain of chip B
The module of road is replaced one by one, such as first replaces FRU A, if abnormal disappearance, it is believed that FRU A are abnormal modules;If abnormal
It does not disappear, describes the problem out on backboard or FRU B, and then replace FRU B, after replacing FRU B, if abnormal disappearance, recognize
It is abnormal module for FRU B;If abnormal do not disappear, describe the problem out on backboard, then continues to replace backboard.
There are the following problems for the above method:Module can only be replaced one by one, it is difficult to ensure primary replacement in place, location efficiency
Low, customer perception is poor.In addition some exceptions are intermittences, and abnormal disappearance, actually FRU A be not after replacing FRU A
Must be abnormal root because problem root is because may be not exposed temporarily only on FRU B.Therefore after replacing FRU A, mistake
After a period of time, problem can expose again.
Invention content
A kind of link impedance detection chip of offer of the embodiment of the present invention and method, for the hardware chain to connecting two chips
The impedance of the position on road is tested, and whether the impedance to judge the hardware link position is abnormal.
First aspect of the embodiment of the present invention provides a kind of chip, and the chip is connected with another chip by hardware link
It connects.The embodiment of the present invention is by being improved chip, to be examined to the impedance of the hardware link each position by chip
It surveys.The chip includes processing circuit, transmission circuit.In order to test the impedance of the hardware link each position, this hair
Bright embodiment also adds edge control device and testing impedance circuit in the chips.Edge control device series connection with it is described
After signal generator in transmission circuit, the pulse signal for generating the signal generator is adjusted to step signal.
The testing impedance circuit is connected between the hardware link and the processing circuit.Signal described in the processing circuit controls
Generator generates pulse signal, controls the edge control device and pulse signal caused by the signal generator is adjusted to rank
Jump signal, and the step signal divides two-way to transmit, and hardware link described in a road direction is transmitted, all the way via the testing impedance circuit
Transmission, the step signal reflect when by the different line impedance of resistance value in the hardware link, the letter after reflection
Number it is transmitted to the testing impedance circuit.The resistance is passed through in the sampling of testing impedance circuit period property described in handled circuit control
The signal voltage value of anti-test circuit, and determined according to the sampled voltage that sampling time and each sampling time are sampled described hard
The line impedance at different location in part link.
By the way that edge control device and testing impedance circuit are added in the chips, it can be detected by chip and connect the chip
With the impedance of the circuit of different location in the hardware link of other chips, it can accurately and quickly orient impedance occur in this way
Abnormal circuit, so that it is determined that the module where the anomalous line, to be replaced to the module.
Optionally, the testing impedance circuit is connected to the hardware link by first switch, when the chip is normal
When work, the first switch cuts off the connection of the testing impedance circuit and the hardware link, described hard when needing to diagnose
When the exception of part link, the first switch connects the connection of the testing impedance circuit and the hardware link.
In this way, the chip can be made arbitrarily to switch between normal operating conditions and test mode, as long as by described
The chip is switched to the testing impedance circuit and can tested the hardware link by first switch.
Optionally, second switch is also associated between the first switch and the hardware link, the second switch
One hardware link is also associated with a correction impedance, before the testing impedance to the hardware link, is opened by described first
It closes and second switch connects the abnormity diagnosis circuit and the correction impedance, using the correction impedance as the hardware chain
The impedance value of the correction impedance is tested on road, by the reality of the correction impedance value tested and the correction impedance
Border impedance value is compared, and is obtained impedance adjustment coefficient, is adjusted to the line impedance tested according to the regulation coefficient.
Loss is usually present in circuit, and the loss of different chips also differs, so, before test, first pass through
The correction impedance tests out a compensation coefficient in advance, is corrected to the line impedance in the hardware link tested, with
Improve the accuracy of tested line impedance.
The hardware link is receives link, and the receives link is connected to the chip by the input terminal of the chip
Receiving circuit, the chip further include third switch, the transmission circuit pass through the second switch and the third switch
It is connected to the receives link.
The hardware link includes transmission link and receives link, is tested to the line impedance in transmission link
When, it can directly be tested, but when testing receives link, be needed institute using the scheme in above-mentioned realization method
It states hair receives link and is connected to the transmission circuit, thus need to switch the hair reception chain by second switch and third
Road is connected to the transmission circuit, in this way can be respectively to the circuit in the Sino-Russian transmission link of the hardware link and receives link
Impedance is tested.
Optionally, described in the sampled voltage that the processing circuit was sampled according to sampling time and each sampling time determines
When line impedance at the different location in hardware link, specially:
Emitting voltage is calculated, Vreflected=Vsample-Vincent, Vsample and Vincent are it is known that then can be with
Calculate Vreflected, wherein Vsample is sampled voltage, and Vincent is the voltage of step signal, and Vreflected is
Reflected voltage;
According to reflection coefficient formula ρ=Vreflected/Vincident, reflectance factor ρ is calculated, is further according to reflection
Number formula ρ=Vreflected/Vincident=(Z-Z0)/(Z+Z0), obtains Z=Z0 ((1+ ρ)/(1- ρ)), wherein Z is institute
The line impedance of test, Z0 design impedance for circuit;
Time T=(T2-T1)/2, T2 that step signal reaches one line impedance position of hardware link is testing impedance
For circuit sampling to the sampling instant of reflected voltage, T1 is the sampling instant that testing impedance circuit samples step signal for the first time,
Physical location of the line impedance in hardware link corresponding to the sampled voltage that sampling instant T2 is sampled:L
=(v*T), wherein v are propagation rate of the signal in system media.
According to above-mentioned calculation formula, the impedance of the circuit of each position in the hardware link can be accurately calculated.
Second aspect of the present invention provides a kind of impedance detecting method.The method is applied to a chip.The chip passes through
Hardware link is connected to another chip.The chip includes signal generator and edge control device, the signal generator
The pulse signal of generation is adjusted to step signal by the edge control device, and the chip is also connected with a testing impedance circuit.
The method includes:
It controls the signal generator and generates pulse signal, control the edge control device and produced the signal generator
Raw pulse signal is adjusted to step signal, and the step signal divides two-way to transmit, and hardware link described in a road direction is transmitted, all the way
Via the testing impedance circuit transmission, the step signal is when by the different line impedance of resistance value in the hardware link
It reflects, the signal transmission after reflection to the testing impedance circuit;
The signal voltage value of the testing impedance circuit, and root are passed through in the sampling for controlling the testing impedance circuit period property
The sampled voltage sampled according to sampling time and each sampling time determines the circuit at the different location in the hardware link
Impedance.
By the way that edge control device and testing impedance circuit are added in the chips, it can be detected by chip and connect the chip
With the impedance of the circuit of different location in the hardware link of other chips, it can accurately and quickly orient impedance occur in this way
Abnormal circuit, so that it is determined that the module where the anomalous line, to be replaced to the module.
Optionally, the sampled voltage sampled according to sampling time and each sampling time determines the hardware link
In different location at line impedance when, including:
Emitting voltage is calculated, Vreflected=Vsample-Vincent, Vsample and Vincent are it is known that then can be with
Calculate Vreflected, wherein Vsample is sampled voltage, and Vincent is the voltage of step signal, and Vreflected is
Reflected voltage;
According to reflection coefficient formula ρ=Vreflected/Vincident, reflectance factor ρ is calculated, is further according to reflection
Number formula ρ=Vreflected/Vincident=(Z-Z0)/(Z+Z0), obtains Z=Z0 ((1+ ρ)/(1- ρ)), wherein Z is institute
The line impedance of test, Z0 design impedance for circuit;
Time T=(T2-T0)/2, T2 that step signal reaches one line impedance of hardware link is testing impedance circuit sampling
To the sampling instant of reflected voltage, T0 is the sampling instant that testing impedance circuit samples step signal for the first time;
Physical location of the line impedance in hardware link corresponding to the sampled voltage that sampling instant T2 is sampled:L
=(v*T), wherein v are propagation rate of the signal in system media.
According to above-mentioned calculation formula, the impedance of the circuit of each position in the hardware link can be accurately calculated.
By the way that edge control device and testing impedance circuit are added in the chips, it can be detected by chip and connect the chip
With the impedance of the circuit of different location in the hardware link of other chips, hardware link can be accurately and quickly oriented in this way
The middle circuit for impedance exception occur, so that it is determined that the module where the anomalous line, to be replaced to the module.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described.
Fig. 1 is the schematic diagram of the hardware link between two chips.
Fig. 2 is the electrical block diagram for the chip that first embodiment of the invention provides.
Fig. 3 is the flow chart provided in an embodiment of the present invention for carrying out hardware link method for detecting abnormality.
Fig. 4 be in the embodiment of the present invention to the signal of hardware link sampled obtained by sampling time and sampled voltage
Relational graph.
Fig. 5 is the schematic diagram that the step signal in the embodiment of the present invention reflects in hardware link.
Fig. 6 is the relational graph of the line impedance and place on line in the hardware link determined in the embodiment of the present invention.
Fig. 7 by the embodiment of the present invention according to the line impedance tested judge hardware link whether the schematic diagram of failure.
Fig. 8 is the electrical block diagram for the chip that second embodiment of the invention provides.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes.
The embodiment of the present invention provides the hardware link between a kind of two chips of detection (such as described in background technology
Hardware link between chip A to chip B) abnormal method, link can be link disconnection, link short circuit, circuit extremely
Impedance is excessive etc..Two chips that can be communicated in hardware link or any chip interior increase an abnormity diagnosis mould
Block, when needing to diagnose the exception of the hardware link, the chip A or chip B use the abnormality diagnosis module
The impedance at multiple positions in the hardware link is tested out, and by the impedance tested out and design impedance (in circuit design
The impedance that set hardware link is met) it is compared, if Impedance measurement and the difference of design impedance are more than threshold value, institute
The position that the corresponding position of Impedance measurement is appearance exception, and the equipment needed replacing according to identified location determination are stated,
For example, in Fig. 1, if it is position 2, position 3 or position 8 abnormal position occur, then it is assumed that backboard is abnormal, replaces backboard.Such as
This, can accurately and quickly orient and occur abnormal position in hardware link.
To hardware link abnormality detection side that the embodiment of the present invention is provided still be illustrated with the hardware link in Fig. 1 below
Then method, the embodiment of the present invention pass through chip A diagnosis connection chips A by increasing abnormality diagnosis module in the chip A of FRUA
With occur the position of link exception in the transmission link or receives link of chip B.
As shown in Fig. 2, for the circuit structure 20 of first embodiment of the invention chips A.Chip A includes processing circuit
21, transmission circuit 22 and receiving circuit 23.What the processing circuit 21 was used to receive received signal (such as receiving circuit 23)
Signal is handled, and by processed signal by the output of transmission circuit 22 to the chip B being connect by transmission link with it.
The hardware link includes the transmission link that position 1,2,3,4,5 is formed and the receives link that position 6,7,8,9,10 is formed.
The transmission circuit 22 includes transmission buffer (FIFO) 221, encoder (Encoder) 222, signal generator
The elements such as (Pattern Generator) 223, first switch (such as selector MUX1) 224.When chip A is worked normally, place
Reason circuit 21 generate signal first cache to the transmission buffer 221, and via the encoder 222 encode after, by electricity
Other elements in road, such as polarity inverting units (polarity), deserializer (PISO), send balanced device (Pre/emp),
After the processing of the elements such as amplifier, exported through output end 225.The output end 225 is connected by transmission link shown in Fig. 1
To the chip B.
The first switch 224 connects the encoder 222 or described according to the command selection of the processing circuit 21
Signal generator 223, when chip A is worked normally, the encoder 222 is connected in the selection of the first switch 224, as chip A
When needing test, the signal generator 223 is connected in the first switch selection.
The embodiment of the present invention in order to the hardware link between detection chip A and chip B exception, in the first switch
An edge control device 226 is added between 224 and the signal generator 223, the edge control device 226 is used for will be described
The pulse signal that signal generator 223 generates is adjusted to a step signal.In addition, in the output end 225 and the processing
A testing impedance circuit is connected between circuit 21, the impedance is then that circuit includes second switch (such as selector MUX2) 24
And analog-digital converter (ADC) 25, wherein 24 one end of the second switch is connected to the output end 225, and other end is connected to
The analog-digital converter 25, the analog-digital converter 25 are connected to the processing circuit 21.
When the chip A is worked normally, the first switch 224 connects the encoder 222, the second switch 24
The connection of the analog-digital converter 25 and the output end 225 is disconnected, then the signal that processing circuit 21 generates directly passes through described
Output end 225 and the transmission link are transmitted to the chip B.
Burning has abnormality diagnosis procedure in the processing circuit 21, is detected when needing the exception to hardware link
When, the processing circuit 21 executes the abnormality diagnosis procedure, is carried out abnormality detection to hardware link, and the processing circuit passes through
The abnormality diagnosis procedure is run, method shown in Fig. 3 is executed:
Step S301, the processing circuit 21 send control command to first switch 224, second switch 24, signal and generate
Device 223 and edge control device 226 connect the signal generator to control the first switch 224, control the second switch
24 connect the ADC25 and the output end 225, control the signal generator 223 and generate pulse signal, control the edge
The signal that the signal generator exports is adjusted to an edge signal by controller 226.
The edge signal can divide two-way to transmit, and be transmitted to the processing by the second switch and the ADC all the way
Circuit 21 is transmitted to the chip B by the output end and the hardware link all the way.
During the edge signal is transmitted to the chip B, if there are the lines of different resistance values in hardware link
Lu Shi, then when being transmitted to the critical localisation of the different circuit of resistance value signal reflex can occur for signal, if for example, hardware link
It is the critical localisation of the different circuit of resistance value at position 2, then signal reflex can occur when being transmitted at position 2 for signal, instead
The signal penetrated is transmitted to the processing circuit 21 by second switch and the ADC, and the signal for continuing transmission is being transferred to position 3
When place, since position 3 is also the critical localisation of the different circuit of resistance value, then can similarly it reflect.
Step S302, the processing circuit 21 periodically controls the ADC25 and samples the signal voltage received, and remembers
The relationship of sampled voltage and sampling time is recorded, sampled voltage and the relationship in sampling time can be as shown in the schematic diagram of fig. 3.
Wherein, when voltage does not reflect, i.e., when the impedance of circuit does not change in hardware link, then the voltage sampled is to send out
The initial voltage (Vincent) of the number of delivering letters (the i.e. described edge signal), when voltage emits, i.e., the circuit in hardware link
When impedance changes, then the voltage that samples can be higher or lower than initial voltage, as sampling instant t1, t2 in Fig. 4, t3,
The voltage that t4 is sampled.
It is corresponding to calculate sampling instant according to the correspondence of the sampled voltage and sampling time that are recorded by step S303
Line impedance.
Due to that during signal transmission, signal reflex only can occur at the different position of impedance, so calculating
When the corresponding line impedance of sampling instant, when also can only calculate sampling corresponding higher or lower than the sampled voltage of initial voltage
The impedance at quarter.
The method for calculating the corresponding impedance of sampling instant is specially:
Obtain the corresponding sampled voltage of sampling instant, sampled voltage (Vsample)=initial voltage (Vincent)+reflection
Voltage (Vreflected).Then Vreflected=Vsample-Vincent, Vsample and Vincent are it is known that can then count
Calculate Vreflected.
After obtaining reflected voltage Vreflected, according to reflection coefficient formula ρ=Vreflected/Vincident, it can count
Calculate reflectance factor ρ.Further according to reflection coefficient formula ρ=Vreflected/Vincident=(Z-Z0)/(Z+Z0), can be obtained
Z=Z0 ((1+ ρ)/(1- ρ)).Wherein Z is the corresponding impedances of sampling instant T, and Z0 is to be designed for hardware link in circuit design
Impedance, generally 50 ohm.
Step S304, after calculating sampling instant corresponding impedance, the circuit that sampling is calculated according to sampling instant hinders
Resist the position L in hardware link.
As shown in fig. 5, it is assumed that processing circuit 20 samples voltage for the first time at the T0 moment, in T2 instance samples to hardware chain
The reflected voltage of a certain line impedance in road, by T2 instance samples to reflection signal be to transmit a signal to up to line impedance institute
It is collected that ADC25 is again returned to after place physical location L, then can extrapolate transmit a signal to up to hardware link position 3 when
Between T=(T2-T0)/2.
In this way, calculating the method for position L of the line impedance that signal reflex occurs in hardware link such as according to time T
Under:
According to the relationship of distance and time and speed:L=v*t.It can obtain the voltage that ADC25 is sampled in sampling instant T2
The physical location of corresponding line impedance:L=(v*T), wherein v are propagation rate of the signal in system media, it and light
There are certain relationships by fast C:V=C/ ((ε) 1/2), wherein ε are system known media matter electric constant, i.e. L=(C*T)/(ε) 1/2.
After calculating the corresponding impedance in each position, you can figure shown in fig. 6 is obtained, it can be clearly from figure
The impedance for going out each position in hardware link, by the impedance of each position compared with designing impedance, when the impedance of certain position is being set
It counts in +/- 10% range of impedance, the system of 50ohm as, impedance is between 45ohm~55ohm, then Z can be identified as normally
State, as shown in the B in Fig. 7, if impedance approaching infinity is big, i.e. the case where A in Fig. 7, then explanation is open circuit, if impedance
Close to 0hm, then illustrate short circuit, i.e. the case where C in Fig. 7, both of which is abnormal conditions, is in addition more than in impedance
+ the 10% of impedance, and not infinity are designed ,-the 10% of design impedance is less than, but when not being close to 0hm, then illustrate circuit
Impedance exceeds normal range (NR), then needs to be replaced the module where the circuit.
It should be noted that the corresponding impedance in each position calculated can be stored in the memory of IC, managing
When the management equipment of the IC starts, the data in memory can be called, user is presented the data to, user can be based on shown
Data judge out of order position in hardware link.
By the above method, the position broken down in hardware link can accurately and be quickly judged.
In the second embodiment of the present invention, as shown in figure 8, the transmission circuit further comprises 26 (example of third switch
Such as MUX3), the third switch 26 is connected between the second switch 24 and the output end 225, in the receiving circuit
The 4th switch, the input of an output end of the third switch and the 4th switch are connected between 23 and the input terminal
End connection, forms Article 4 circuit, other circuits are connected to identical in first embodiment.
When chip A is worked normally, the 4th switch 27 connects the receiving circuit 23 and the input terminal 226, makes
The signal inputted by the input terminal 226 is transmitted to the processing circuit 21 by the receiving circuit 23.
When the exception for needing the output link between chip A and chip B diagnoses, the third switch 26 is connected
The transmission circuit 22 and the output end 225.The second switch connects the ADC25 and the transmission circuit 22, so
The exception of output link can be diagnosed.
When the exception for needing the input link between chip A and chip B diagnoses, the third is opened and 26 and institute
It states the 4th switch 27 and connects the transmission circuit 22 and the input terminal 226, in this way, can be to the input terminal 226 of the chip A
Line anomalies in the input link connected are detected.The method of abnormality detection is identical as in first embodiment,
This is repeated no more.
Since circuit has loss during transmission, further a correction resistance can be connected in output end 225
28, before carrying out hardware link diagnosis, the transmission circuit 22 and the correction can be connected by the third switch 26
Then resistance 28 calculates the Impedance measurement of the correction resistance 28 in circuit, with the test by method shown in Fig. 3
The practical impedance of impedance divided by the correction resistance, then can be obtained a compensation coefficient Δ, in this way, in calculating hardware link
Impedance measurement when, then can divided by the compensation coefficient, to be corrected to Impedance measurement, with the impedance after correction again go judge pair
It answers the impedance of position whether abnormal, increases the accuracy rate of judgement.
It is provided for the embodiments of the invention data backup device above and method is described in detail, it is used herein
Principle and implementation of the present invention are described for specific case, and the explanation of above example is only intended to help to understand
The method and its core concept of the present invention;Meanwhile for those of ordinary skill in the art, according to the thought of the present invention, having
There will be changes in body embodiment and application range, in conclusion the content of the present specification should not be construed as to the present invention
Limitation.
Claims (7)
1. a kind of chip is connected to another chip, including processing circuit, transmission circuit, the transmission by hardware link
Circuit is connected between the processing circuit and the hardware link, and the transmission circuit includes signal generator, for generating
Pulse signal, which is characterized in that the chip further includes:
Edge control device is connect with the signal generator;
Testing impedance circuit is connected between the hardware link and the processing circuit;
Signal generator described in the processing circuit controls generates pulse signal, controls the edge control device and produces the signal
Pulse signal is adjusted to step signal caused by raw device, and the step signal divides two-way to transmit, hardware link described in a road direction
It transmits, testing impedance circuit transmission described in a road direction, the step signal is by the different line of resistance value in the hardware link
It is reflected when road, the signal transmission after reflection to the testing impedance circuit;
The signal voltage of the testing impedance circuit is passed through in the sampling of testing impedance circuit period property described in handled circuit control
Value, and determined at the different location in the hardware link according to the sampled voltage that sampling time and each sampling time are sampled
Circuit impedance.
2. chip as described in claim 1, which is characterized in that the testing impedance circuit is connected to described by first switch
Hardware link, when the chip works normally, the first switch cuts off the testing impedance circuit and the hardware link
Connection, when needing to diagnose the exception of the hardware link, the first switch connect the testing impedance circuit with it is described
The connection of hardware link.
3. chip as claimed in claim 2, which is characterized in that be also associated between the first switch and the hardware link
One hardware link of second switch, the second switch is also associated with a correction impedance, in the impedance to the hardware link
Before test, the abnormity diagnosis circuit and the correction impedance are connected by the first switch and the second switch, by institute
Correction impedance is stated as the hardware link, the impedance value of the correction impedance is tested, the correction that will be tested
Impedance value obtains impedance adjustment coefficient, according to the regulation coefficient to being surveyed compared with the real impedance values of the correction impedance
The line impedance of examination is adjusted.
4. chip as claimed in claim 2, which is characterized in that the hardware link is receives link, and the receives link is logical
The input terminal for crossing the chip is connected to the receiving circuit of the chip, and the chip further includes third switch, the transmission electricity
Road is connected to the receives link by the second switch and third switch.
5. the chip as described in claim any one, which is characterized in that the processing circuit is according to the sampling time and each
When the sampled voltage that sampling time is sampled determines the line impedance at the different location in the hardware link, specially:
Emitting voltage is calculated, Vreflected=Vsample-Vincent, Vsample and Vincent are it is known that can then calculate
Go out Vreflected, wherein Vsample is sampled voltage, and Vincent is the voltage of step signal, and Vreflected is reflection
Voltage;
According to reflection coefficient formula ρ=Vreflected/Vincident, reflectance factor ρ is calculated, further according to reflectance factor public affairs
Formula ρ=Vreflected/Vincident=(Z-Z0)/(Z+Z0) obtains Z=Z0 ((1+ ρ)/(1- ρ)), and wherein Z is is tested
Line impedance, Z0 designs impedance for circuit;
Time T=(T2-T1)/2, T2 that step signal reaches one line impedance position of hardware link is testing impedance circuit
The sampling instant of reflected voltage is sampled, T1 is the sampling instant that testing impedance circuit samples step signal for the first time,
Physical location of the line impedance in hardware link corresponding to the sampled voltage that sampling instant T2 is sampled:L=(v*
), T wherein v is propagation rate of the signal in system media.
6. a kind of impedance detecting method is applied to a chip, the chip is connected to another chip by hardware link, wraps
Signal generator and edge control device are included, the pulse signal that the signal generator generates is adjusted to by the edge control device
Step signal, the chip are also connected with a testing impedance circuit, the method includes:
It controls the signal generator and generates pulse signal, controlling the edge control device will be caused by the signal generator
Pulse signal is adjusted to step signal, and the step signal divides two-way to transmit, and hardware link described in a road direction is transmitted, a road direction institute
Testing impedance circuit transmission is stated, the step signal reflects when by the different circuit of resistance value in the hardware link,
Signal transmission after reflection is to the testing impedance circuit;
The sampling of the testing impedance circuit period property is controlled by the signal voltage value of the testing impedance circuit, and according to adopting
The sampled voltage that sample time and each sampling time are sampled determines the resistance of the circuit at the different location in the hardware link
It is anti-.
7. impedance detecting method as claimed in claim 6, which is characterized in that described according to the sampling time and each sampling time
When the sampled voltage sampled determines the impedance of the circuit at the different location in the hardware link, including:
Emitting voltage is calculated, Vreflected=Vsample-Vincent, Vsample and Vincent are it is known that can then calculate
Go out Vreflected, wherein Vsample is sampled voltage, and Vincent is the voltage of step signal, and Vreflected is reflection
Voltage;
According to reflection coefficient formula ρ=Vreflected/Vincident, reflectance factor ρ is calculated, further according to reflectance factor public affairs
Formula ρ=Vreflected/Vincident=(Z-Z0)/(Z+Z0) obtains Z=Z0 ((1+ ρ)/(1- ρ)), and wherein Z is is tested
Line impedance, Z0 designs impedance for circuit;
Time T=(T2-T0)/2, T2 that step signal reaches one line impedance of hardware link is testing impedance circuit sampling to instead
The sampling instant of radio pressure, T0 are the sampling instant that testing impedance circuit samples step signal for the first time;
Physical location of the line impedance in hardware link corresponding to the sampled voltage that sampling instant T2 is sampled:L=(v*
), T wherein v is propagation rate of the signal in system media.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710221938.XA CN108693404A (en) | 2017-04-06 | 2017-04-06 | Link impedance detection chip and method |
| PCT/CN2018/077163 WO2018184431A1 (en) | 2017-04-06 | 2018-02-24 | Link impedance detection chip and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710221938.XA CN108693404A (en) | 2017-04-06 | 2017-04-06 | Link impedance detection chip and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108693404A true CN108693404A (en) | 2018-10-23 |
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ID=63713134
Family Applications (1)
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| CN201710221938.XA Pending CN108693404A (en) | 2017-04-06 | 2017-04-06 | Link impedance detection chip and method |
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| WO (1) | WO2018184431A1 (en) |
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| CN111381104A (en) * | 2018-12-29 | 2020-07-07 | 中兴通讯股份有限公司 | Method and device for measuring impedance of transmission channel |
| CN113567801A (en) * | 2020-04-28 | 2021-10-29 | 南宁富桂精密工业有限公司 | Wire detection device and wire detection method |
| CN113899952A (en) * | 2021-10-26 | 2022-01-07 | 西安微电子技术研究所 | Automatic impedance testing system and method |
| CN116070560A (en) * | 2022-12-30 | 2023-05-05 | 成都电科星拓科技有限公司 | Chip small batch limit condition construction and verification architecture |
| WO2024002027A1 (en) * | 2022-06-29 | 2024-01-04 | 深圳市中兴微电子技术有限公司 | Method and system for online monitoring of interconnect impedance |
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| CN111381104A (en) * | 2018-12-29 | 2020-07-07 | 中兴通讯股份有限公司 | Method and device for measuring impedance of transmission channel |
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| CN116070560A (en) * | 2022-12-30 | 2023-05-05 | 成都电科星拓科技有限公司 | Chip small batch limit condition construction and verification architecture |
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| Publication number | Publication date |
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| WO2018184431A1 (en) | 2018-10-11 |
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